2 * Device Tree Source for DRA7xx clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 atl_clkin0_ck: atl_clkin0_ck {
13 compatible = "fixed-clock";
14 clock-frequency = <0>;
17 atl_clkin1_ck: atl_clkin1_ck {
19 compatible = "fixed-clock";
20 clock-frequency = <0>;
23 atl_clkin2_ck: atl_clkin2_ck {
25 compatible = "fixed-clock";
26 clock-frequency = <0>;
29 atlclkin3_ck: atlclkin3_ck {
31 compatible = "fixed-clock";
32 clock-frequency = <0>;
35 hdmi_clkin_ck: hdmi_clkin_ck {
37 compatible = "fixed-clock";
38 clock-frequency = <0>;
41 mlb_clkin_ck: mlb_clkin_ck {
43 compatible = "fixed-clock";
44 clock-frequency = <0>;
47 mlbp_clkin_ck: mlbp_clkin_ck {
49 compatible = "fixed-clock";
50 clock-frequency = <0>;
53 pciesref_acs_clk_ck: pciesref_acs_clk_ck {
55 compatible = "fixed-clock";
56 clock-frequency = <100000000>;
59 ref_clkin0_ck: ref_clkin0_ck {
61 compatible = "fixed-clock";
62 clock-frequency = <0>;
65 ref_clkin1_ck: ref_clkin1_ck {
67 compatible = "fixed-clock";
68 clock-frequency = <0>;
71 ref_clkin2_ck: ref_clkin2_ck {
73 compatible = "fixed-clock";
74 clock-frequency = <0>;
77 ref_clkin3_ck: ref_clkin3_ck {
79 compatible = "fixed-clock";
80 clock-frequency = <0>;
83 rmii_clk_ck: rmii_clk_ck {
85 compatible = "fixed-clock";
86 clock-frequency = <0>;
89 sdvenc_clkin_ck: sdvenc_clkin_ck {
91 compatible = "fixed-clock";
92 clock-frequency = <0>;
95 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
97 compatible = "fixed-clock";
98 clock-frequency = <32768>;
101 sys_32k_ck: sys_32k_ck {
103 compatible = "fixed-clock";
104 clock-frequency = <32768>;
107 virt_12000000_ck: virt_12000000_ck {
109 compatible = "fixed-clock";
110 clock-frequency = <12000000>;
113 virt_13000000_ck: virt_13000000_ck {
115 compatible = "fixed-clock";
116 clock-frequency = <13000000>;
119 virt_16800000_ck: virt_16800000_ck {
121 compatible = "fixed-clock";
122 clock-frequency = <16800000>;
125 virt_19200000_ck: virt_19200000_ck {
127 compatible = "fixed-clock";
128 clock-frequency = <19200000>;
131 virt_20000000_ck: virt_20000000_ck {
133 compatible = "fixed-clock";
134 clock-frequency = <20000000>;
137 virt_26000000_ck: virt_26000000_ck {
139 compatible = "fixed-clock";
140 clock-frequency = <26000000>;
143 virt_27000000_ck: virt_27000000_ck {
145 compatible = "fixed-clock";
146 clock-frequency = <27000000>;
149 virt_38400000_ck: virt_38400000_ck {
151 compatible = "fixed-clock";
152 clock-frequency = <38400000>;
155 sys_clkin2: sys_clkin2 {
157 compatible = "fixed-clock";
158 clock-frequency = <22579200>;
161 usb_otg_clkin_ck: usb_otg_clkin_ck {
163 compatible = "fixed-clock";
164 clock-frequency = <0>;
167 video1_clkin_ck: video1_clkin_ck {
169 compatible = "fixed-clock";
170 clock-frequency = <0>;
173 video1_m2_clkin_ck: video1_m2_clkin_ck {
175 compatible = "fixed-clock";
176 clock-frequency = <0>;
179 video2_clkin_ck: video2_clkin_ck {
181 compatible = "fixed-clock";
182 clock-frequency = <0>;
185 video2_m2_clkin_ck: video2_m2_clkin_ck {
187 compatible = "fixed-clock";
188 clock-frequency = <0>;
191 dpll_abe_ck: dpll_abe_ck {
193 compatible = "ti,omap4-dpll-m4xen-clock";
194 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
195 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
198 dpll_abe_x2_ck: dpll_abe_x2_ck {
200 compatible = "ti,omap4-dpll-x2-clock";
201 clocks = <&dpll_abe_ck>;
204 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
206 compatible = "ti,divider-clock";
207 clocks = <&dpll_abe_x2_ck>;
209 ti,autoidle-shift = <8>;
211 ti,index-starts-at-one;
212 ti,invert-autoidle-bit;
217 compatible = "ti,divider-clock";
218 clocks = <&dpll_abe_m2x2_ck>;
221 ti,index-power-of-two;
224 dpll_abe_m2_ck: dpll_abe_m2_ck {
226 compatible = "ti,divider-clock";
227 clocks = <&dpll_abe_ck>;
229 ti,autoidle-shift = <8>;
231 ti,index-starts-at-one;
232 ti,invert-autoidle-bit;
235 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
237 compatible = "ti,divider-clock";
238 clocks = <&dpll_abe_x2_ck>;
240 ti,autoidle-shift = <8>;
242 ti,index-starts-at-one;
243 ti,invert-autoidle-bit;
246 dpll_core_ck: dpll_core_ck {
248 compatible = "ti,omap4-dpll-core-clock";
249 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
250 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
253 dpll_core_x2_ck: dpll_core_x2_ck {
255 compatible = "ti,omap4-dpll-x2-clock";
256 clocks = <&dpll_core_ck>;
259 dpll_core_h12x2_ck: dpll_core_h12x2_ck {
261 compatible = "ti,divider-clock";
262 clocks = <&dpll_core_x2_ck>;
264 ti,autoidle-shift = <8>;
266 ti,index-starts-at-one;
267 ti,invert-autoidle-bit;
270 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
272 compatible = "fixed-factor-clock";
273 clocks = <&dpll_core_h12x2_ck>;
278 dpll_mpu_ck: dpll_mpu_ck {
280 compatible = "ti,omap4-dpll-clock";
281 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
282 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
285 dpll_mpu_m2_ck: dpll_mpu_m2_ck {
287 compatible = "ti,divider-clock";
288 clocks = <&dpll_mpu_ck>;
290 ti,autoidle-shift = <8>;
292 ti,index-starts-at-one;
293 ti,invert-autoidle-bit;
296 mpu_dclk_div: mpu_dclk_div {
298 compatible = "fixed-factor-clock";
299 clocks = <&dpll_mpu_m2_ck>;
304 dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
306 compatible = "fixed-factor-clock";
307 clocks = <&dpll_core_h12x2_ck>;
312 dpll_dsp_ck: dpll_dsp_ck {
314 compatible = "ti,omap4-dpll-clock";
315 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
316 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
319 dpll_dsp_m2_ck: dpll_dsp_m2_ck {
321 compatible = "ti,divider-clock";
322 clocks = <&dpll_dsp_ck>;
324 ti,autoidle-shift = <8>;
326 ti,index-starts-at-one;
327 ti,invert-autoidle-bit;
330 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
332 compatible = "fixed-factor-clock";
333 clocks = <&dpll_core_h12x2_ck>;
338 dpll_iva_ck: dpll_iva_ck {
340 compatible = "ti,omap4-dpll-clock";
341 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
342 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
345 dpll_iva_m2_ck: dpll_iva_m2_ck {
347 compatible = "ti,divider-clock";
348 clocks = <&dpll_iva_ck>;
350 ti,autoidle-shift = <8>;
352 ti,index-starts-at-one;
353 ti,invert-autoidle-bit;
358 compatible = "fixed-factor-clock";
359 clocks = <&dpll_iva_m2_ck>;
364 dpll_gpu_ck: dpll_gpu_ck {
366 compatible = "ti,omap4-dpll-clock";
367 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
368 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
371 dpll_gpu_m2_ck: dpll_gpu_m2_ck {
373 compatible = "ti,divider-clock";
374 clocks = <&dpll_gpu_ck>;
376 ti,autoidle-shift = <8>;
378 ti,index-starts-at-one;
379 ti,invert-autoidle-bit;
382 dpll_core_m2_ck: dpll_core_m2_ck {
384 compatible = "ti,divider-clock";
385 clocks = <&dpll_core_ck>;
387 ti,autoidle-shift = <8>;
389 ti,index-starts-at-one;
390 ti,invert-autoidle-bit;
393 core_dpll_out_dclk_div: core_dpll_out_dclk_div {
395 compatible = "fixed-factor-clock";
396 clocks = <&dpll_core_m2_ck>;
401 dpll_ddr_ck: dpll_ddr_ck {
403 compatible = "ti,omap4-dpll-clock";
404 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
405 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
408 dpll_ddr_m2_ck: dpll_ddr_m2_ck {
410 compatible = "ti,divider-clock";
411 clocks = <&dpll_ddr_ck>;
413 ti,autoidle-shift = <8>;
415 ti,index-starts-at-one;
416 ti,invert-autoidle-bit;
419 dpll_gmac_ck: dpll_gmac_ck {
421 compatible = "ti,omap4-dpll-clock";
422 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
423 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
426 dpll_gmac_m2_ck: dpll_gmac_m2_ck {
428 compatible = "ti,divider-clock";
429 clocks = <&dpll_gmac_ck>;
431 ti,autoidle-shift = <8>;
433 ti,index-starts-at-one;
434 ti,invert-autoidle-bit;
437 video2_dclk_div: video2_dclk_div {
439 compatible = "fixed-factor-clock";
440 clocks = <&video2_m2_clkin_ck>;
445 video1_dclk_div: video1_dclk_div {
447 compatible = "fixed-factor-clock";
448 clocks = <&video1_m2_clkin_ck>;
453 hdmi_dclk_div: hdmi_dclk_div {
455 compatible = "fixed-factor-clock";
456 clocks = <&hdmi_clkin_ck>;
461 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
463 compatible = "fixed-factor-clock";
464 clocks = <&dpll_abe_m3x2_ck>;
469 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
471 compatible = "fixed-factor-clock";
472 clocks = <&dpll_abe_m3x2_ck>;
477 eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
479 compatible = "fixed-factor-clock";
480 clocks = <&dpll_core_h12x2_ck>;
485 dpll_eve_ck: dpll_eve_ck {
487 compatible = "ti,omap4-dpll-clock";
488 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
489 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
492 dpll_eve_m2_ck: dpll_eve_m2_ck {
494 compatible = "ti,divider-clock";
495 clocks = <&dpll_eve_ck>;
497 ti,autoidle-shift = <8>;
499 ti,index-starts-at-one;
500 ti,invert-autoidle-bit;
503 eve_dclk_div: eve_dclk_div {
505 compatible = "fixed-factor-clock";
506 clocks = <&dpll_eve_m2_ck>;
511 dpll_core_h13x2_ck: dpll_core_h13x2_ck {
513 compatible = "ti,divider-clock";
514 clocks = <&dpll_core_x2_ck>;
516 ti,autoidle-shift = <8>;
518 ti,index-starts-at-one;
519 ti,invert-autoidle-bit;
522 dpll_core_h14x2_ck: dpll_core_h14x2_ck {
524 compatible = "ti,divider-clock";
525 clocks = <&dpll_core_x2_ck>;
527 ti,autoidle-shift = <8>;
529 ti,index-starts-at-one;
530 ti,invert-autoidle-bit;
533 dpll_core_h22x2_ck: dpll_core_h22x2_ck {
535 compatible = "ti,divider-clock";
536 clocks = <&dpll_core_x2_ck>;
538 ti,autoidle-shift = <8>;
540 ti,index-starts-at-one;
541 ti,invert-autoidle-bit;
544 dpll_core_h23x2_ck: dpll_core_h23x2_ck {
546 compatible = "ti,divider-clock";
547 clocks = <&dpll_core_x2_ck>;
549 ti,autoidle-shift = <8>;
551 ti,index-starts-at-one;
552 ti,invert-autoidle-bit;
555 dpll_core_h24x2_ck: dpll_core_h24x2_ck {
557 compatible = "ti,divider-clock";
558 clocks = <&dpll_core_x2_ck>;
560 ti,autoidle-shift = <8>;
562 ti,index-starts-at-one;
563 ti,invert-autoidle-bit;
566 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
568 compatible = "ti,omap4-dpll-x2-clock";
569 clocks = <&dpll_ddr_ck>;
572 dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
574 compatible = "ti,divider-clock";
575 clocks = <&dpll_ddr_x2_ck>;
577 ti,autoidle-shift = <8>;
579 ti,index-starts-at-one;
580 ti,invert-autoidle-bit;
583 dpll_dsp_x2_ck: dpll_dsp_x2_ck {
585 compatible = "ti,omap4-dpll-x2-clock";
586 clocks = <&dpll_dsp_ck>;
589 dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
591 compatible = "ti,divider-clock";
592 clocks = <&dpll_dsp_x2_ck>;
594 ti,autoidle-shift = <8>;
596 ti,index-starts-at-one;
597 ti,invert-autoidle-bit;
600 dpll_gmac_x2_ck: dpll_gmac_x2_ck {
602 compatible = "ti,omap4-dpll-x2-clock";
603 clocks = <&dpll_gmac_ck>;
606 dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
608 compatible = "ti,divider-clock";
609 clocks = <&dpll_gmac_x2_ck>;
611 ti,autoidle-shift = <8>;
613 ti,index-starts-at-one;
614 ti,invert-autoidle-bit;
617 dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
619 compatible = "ti,divider-clock";
620 clocks = <&dpll_gmac_x2_ck>;
622 ti,autoidle-shift = <8>;
624 ti,index-starts-at-one;
625 ti,invert-autoidle-bit;
628 dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
630 compatible = "ti,divider-clock";
631 clocks = <&dpll_gmac_x2_ck>;
633 ti,autoidle-shift = <8>;
635 ti,index-starts-at-one;
636 ti,invert-autoidle-bit;
639 dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
641 compatible = "ti,divider-clock";
642 clocks = <&dpll_gmac_x2_ck>;
644 ti,autoidle-shift = <8>;
646 ti,index-starts-at-one;
647 ti,invert-autoidle-bit;
650 gmii_m_clk_div: gmii_m_clk_div {
652 compatible = "fixed-factor-clock";
653 clocks = <&dpll_gmac_h11x2_ck>;
658 hdmi_clk2_div: hdmi_clk2_div {
660 compatible = "fixed-factor-clock";
661 clocks = <&hdmi_clkin_ck>;
666 hdmi_div_clk: hdmi_div_clk {
668 compatible = "fixed-factor-clock";
669 clocks = <&hdmi_clkin_ck>;
674 l3_iclk_div: l3_iclk_div {
676 compatible = "fixed-factor-clock";
677 clocks = <&dpll_core_h12x2_ck>;
682 l4_root_clk_div: l4_root_clk_div {
684 compatible = "fixed-factor-clock";
685 clocks = <&l3_iclk_div>;
690 video1_clk2_div: video1_clk2_div {
692 compatible = "fixed-factor-clock";
693 clocks = <&video1_clkin_ck>;
698 video1_div_clk: video1_div_clk {
700 compatible = "fixed-factor-clock";
701 clocks = <&video1_clkin_ck>;
706 video2_clk2_div: video2_clk2_div {
708 compatible = "fixed-factor-clock";
709 clocks = <&video2_clkin_ck>;
714 video2_div_clk: video2_div_clk {
716 compatible = "fixed-factor-clock";
717 clocks = <&video2_clkin_ck>;
722 ipu1_gfclk_mux: ipu1_gfclk_mux {
724 compatible = "ti,mux-clock";
725 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
730 mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
732 compatible = "ti,mux-clock";
733 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
738 mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
740 compatible = "ti,mux-clock";
741 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
746 mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
748 compatible = "ti,mux-clock";
749 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
754 timer5_gfclk_mux: timer5_gfclk_mux {
756 compatible = "ti,mux-clock";
757 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
762 timer6_gfclk_mux: timer6_gfclk_mux {
764 compatible = "ti,mux-clock";
765 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
770 timer7_gfclk_mux: timer7_gfclk_mux {
772 compatible = "ti,mux-clock";
773 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
778 timer8_gfclk_mux: timer8_gfclk_mux {
780 compatible = "ti,mux-clock";
781 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
786 uart6_gfclk_mux: uart6_gfclk_mux {
788 compatible = "ti,mux-clock";
789 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
796 compatible = "fixed-clock";
797 clock-frequency = <0>;
801 sys_clkin1: sys_clkin1 {
803 compatible = "ti,mux-clock";
804 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
806 ti,index-starts-at-one;
809 abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
811 compatible = "ti,mux-clock";
812 clocks = <&sys_clkin1>, <&sys_clkin2>;
816 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
818 compatible = "ti,mux-clock";
819 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
823 abe_dpll_clk_mux: abe_dpll_clk_mux {
825 compatible = "ti,mux-clock";
826 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
830 abe_24m_fclk: abe_24m_fclk {
832 compatible = "ti,divider-clock";
833 clocks = <&dpll_abe_m2x2_ck>;
835 ti,dividers = <8>, <16>;
838 aess_fclk: aess_fclk {
840 compatible = "ti,divider-clock";
846 abe_giclk_div: abe_giclk_div {
848 compatible = "ti,divider-clock";
849 clocks = <&aess_fclk>;
854 abe_lp_clk_div: abe_lp_clk_div {
856 compatible = "ti,divider-clock";
857 clocks = <&dpll_abe_m2x2_ck>;
859 ti,dividers = <16>, <32>;
862 abe_sys_clk_div: abe_sys_clk_div {
864 compatible = "ti,divider-clock";
865 clocks = <&sys_clkin1>;
870 adc_gfclk_mux: adc_gfclk_mux {
872 compatible = "ti,mux-clock";
873 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
877 sys_clk1_dclk_div: sys_clk1_dclk_div {
879 compatible = "ti,divider-clock";
880 clocks = <&sys_clkin1>;
883 ti,index-power-of-two;
886 sys_clk2_dclk_div: sys_clk2_dclk_div {
888 compatible = "ti,divider-clock";
889 clocks = <&sys_clkin2>;
892 ti,index-power-of-two;
895 per_abe_x1_dclk_div: per_abe_x1_dclk_div {
897 compatible = "ti,divider-clock";
898 clocks = <&dpll_abe_m2_ck>;
901 ti,index-power-of-two;
904 dsp_gclk_div: dsp_gclk_div {
906 compatible = "ti,divider-clock";
907 clocks = <&dpll_dsp_m2_ck>;
910 ti,index-power-of-two;
915 compatible = "ti,divider-clock";
916 clocks = <&dpll_gpu_m2_ck>;
919 ti,index-power-of-two;
922 emif_phy_dclk_div: emif_phy_dclk_div {
924 compatible = "ti,divider-clock";
925 clocks = <&dpll_ddr_m2_ck>;
928 ti,index-power-of-two;
931 gmac_250m_dclk_div: gmac_250m_dclk_div {
933 compatible = "ti,divider-clock";
934 clocks = <&dpll_gmac_m2_ck>;
937 ti,index-power-of-two;
940 l3init_480m_dclk_div: l3init_480m_dclk_div {
942 compatible = "ti,divider-clock";
943 clocks = <&dpll_usb_m2_ck>;
946 ti,index-power-of-two;
949 usb_otg_dclk_div: usb_otg_dclk_div {
951 compatible = "ti,divider-clock";
952 clocks = <&usb_otg_clkin_ck>;
955 ti,index-power-of-two;
958 sata_dclk_div: sata_dclk_div {
960 compatible = "ti,divider-clock";
961 clocks = <&sys_clkin1>;
964 ti,index-power-of-two;
967 pcie2_dclk_div: pcie2_dclk_div {
969 compatible = "ti,divider-clock";
970 clocks = <&dpll_pcie_ref_m2_ck>;
973 ti,index-power-of-two;
976 pcie_dclk_div: pcie_dclk_div {
978 compatible = "ti,divider-clock";
979 clocks = <&apll_pcie_m2_ck>;
982 ti,index-power-of-two;
985 emu_dclk_div: emu_dclk_div {
987 compatible = "ti,divider-clock";
988 clocks = <&sys_clkin1>;
991 ti,index-power-of-two;
994 secure_32k_dclk_div: secure_32k_dclk_div {
996 compatible = "ti,divider-clock";
997 clocks = <&secure_32k_clk_src_ck>;
1000 ti,index-power-of-two;
1003 clkoutmux0_clk_mux: clkoutmux0_clk_mux {
1005 compatible = "ti,mux-clock";
1006 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1010 clkoutmux1_clk_mux: clkoutmux1_clk_mux {
1012 compatible = "ti,mux-clock";
1013 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1017 clkoutmux2_clk_mux: clkoutmux2_clk_mux {
1019 compatible = "ti,mux-clock";
1020 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1024 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1026 compatible = "fixed-factor-clock";
1027 clocks = <&sys_clkin1>;
1034 compatible = "ti,mux-clock";
1035 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1039 hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
1041 compatible = "ti,mux-clock";
1042 clocks = <&sys_clkin1>, <&sys_clkin2>;
1048 compatible = "ti,divider-clock";
1049 clocks = <&mlb_clkin_ck>;
1052 ti,index-power-of-two;
1055 mlbp_clk: mlbp_clk {
1057 compatible = "ti,divider-clock";
1058 clocks = <&mlbp_clkin_ck>;
1061 ti,index-power-of-two;
1064 per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
1066 compatible = "ti,divider-clock";
1067 clocks = <&dpll_abe_m2_ck>;
1070 ti,index-power-of-two;
1073 timer_sys_clk_div: timer_sys_clk_div {
1075 compatible = "ti,divider-clock";
1076 clocks = <&sys_clkin1>;
1081 video1_dpll_clk_mux: video1_dpll_clk_mux {
1083 compatible = "ti,mux-clock";
1084 clocks = <&sys_clkin1>, <&sys_clkin2>;
1088 video2_dpll_clk_mux: video2_dpll_clk_mux {
1090 compatible = "ti,mux-clock";
1091 clocks = <&sys_clkin1>, <&sys_clkin2>;
1095 wkupaon_iclk_mux: wkupaon_iclk_mux {
1097 compatible = "ti,mux-clock";
1098 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1102 gpio1_dbclk: gpio1_dbclk {
1104 compatible = "ti,gate-clock";
1105 clocks = <&sys_32k_ck>;
1110 dcan1_sys_clk_mux: dcan1_sys_clk_mux {
1112 compatible = "ti,mux-clock";
1113 clocks = <&sys_clkin1>, <&sys_clkin2>;
1114 ti,bit-shift = <24>;
1118 timer1_gfclk_mux: timer1_gfclk_mux {
1120 compatible = "ti,mux-clock";
1121 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1122 ti,bit-shift = <24>;
1126 uart10_gfclk_mux: uart10_gfclk_mux {
1128 compatible = "ti,mux-clock";
1129 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1130 ti,bit-shift = <24>;
1135 dpll_pcie_ref_ck: dpll_pcie_ref_ck {
1137 compatible = "ti,omap4-dpll-clock";
1138 clocks = <&sys_clkin1>, <&sys_clkin1>;
1139 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1142 dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
1144 compatible = "ti,divider-clock";
1145 clocks = <&dpll_pcie_ref_ck>;
1147 ti,autoidle-shift = <8>;
1149 ti,index-starts-at-one;
1150 ti,invert-autoidle-bit;
1153 apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1154 compatible = "ti,mux-clock";
1155 clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
1161 apll_pcie_ck: apll_pcie_ck {
1163 compatible = "ti,dra7-apll-clock";
1164 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1165 reg = <0x021c>, <0x0220>;
1168 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1169 compatible = "ti,divider-clock";
1170 clocks = <&apll_pcie_ck>;
1177 optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
1178 compatible = "ti,gate-clock";
1179 clocks = <&apll_pcie_ck>;
1185 optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
1186 compatible = "ti,gate-clock";
1187 clocks = <&optfclk_pciephy_div>;
1190 ti,bit-shift = <10>;
1193 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1195 compatible = "fixed-factor-clock";
1196 clocks = <&apll_pcie_ck>;
1201 apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1203 compatible = "fixed-factor-clock";
1204 clocks = <&apll_pcie_ck>;
1209 apll_pcie_m2_ck: apll_pcie_m2_ck {
1211 compatible = "fixed-factor-clock";
1212 clocks = <&apll_pcie_ck>;
1217 dpll_per_ck: dpll_per_ck {
1219 compatible = "ti,omap4-dpll-clock";
1220 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1221 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1224 dpll_per_m2_ck: dpll_per_m2_ck {
1226 compatible = "ti,divider-clock";
1227 clocks = <&dpll_per_ck>;
1229 ti,autoidle-shift = <8>;
1231 ti,index-starts-at-one;
1232 ti,invert-autoidle-bit;
1235 func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1237 compatible = "fixed-factor-clock";
1238 clocks = <&dpll_per_m2_ck>;
1243 dpll_usb_ck: dpll_usb_ck {
1245 compatible = "ti,omap4-dpll-j-type-clock";
1246 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1247 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1250 dpll_usb_m2_ck: dpll_usb_m2_ck {
1252 compatible = "ti,divider-clock";
1253 clocks = <&dpll_usb_ck>;
1255 ti,autoidle-shift = <8>;
1257 ti,index-starts-at-one;
1258 ti,invert-autoidle-bit;
1261 dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
1263 compatible = "ti,divider-clock";
1264 clocks = <&dpll_pcie_ref_ck>;
1266 ti,autoidle-shift = <8>;
1268 ti,index-starts-at-one;
1269 ti,invert-autoidle-bit;
1272 dpll_per_x2_ck: dpll_per_x2_ck {
1274 compatible = "ti,omap4-dpll-x2-clock";
1275 clocks = <&dpll_per_ck>;
1278 dpll_per_h11x2_ck: dpll_per_h11x2_ck {
1280 compatible = "ti,divider-clock";
1281 clocks = <&dpll_per_x2_ck>;
1283 ti,autoidle-shift = <8>;
1285 ti,index-starts-at-one;
1286 ti,invert-autoidle-bit;
1289 dpll_per_h12x2_ck: dpll_per_h12x2_ck {
1291 compatible = "ti,divider-clock";
1292 clocks = <&dpll_per_x2_ck>;
1294 ti,autoidle-shift = <8>;
1296 ti,index-starts-at-one;
1297 ti,invert-autoidle-bit;
1300 dpll_per_h13x2_ck: dpll_per_h13x2_ck {
1302 compatible = "ti,divider-clock";
1303 clocks = <&dpll_per_x2_ck>;
1305 ti,autoidle-shift = <8>;
1307 ti,index-starts-at-one;
1308 ti,invert-autoidle-bit;
1311 dpll_per_h14x2_ck: dpll_per_h14x2_ck {
1313 compatible = "ti,divider-clock";
1314 clocks = <&dpll_per_x2_ck>;
1316 ti,autoidle-shift = <8>;
1318 ti,index-starts-at-one;
1319 ti,invert-autoidle-bit;
1322 dpll_per_m2x2_ck: dpll_per_m2x2_ck {
1324 compatible = "ti,divider-clock";
1325 clocks = <&dpll_per_x2_ck>;
1327 ti,autoidle-shift = <8>;
1329 ti,index-starts-at-one;
1330 ti,invert-autoidle-bit;
1333 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1335 compatible = "fixed-factor-clock";
1336 clocks = <&dpll_usb_ck>;
1341 func_128m_clk: func_128m_clk {
1343 compatible = "fixed-factor-clock";
1344 clocks = <&dpll_per_h11x2_ck>;
1349 func_12m_fclk: func_12m_fclk {
1351 compatible = "fixed-factor-clock";
1352 clocks = <&dpll_per_m2x2_ck>;
1357 func_24m_clk: func_24m_clk {
1359 compatible = "fixed-factor-clock";
1360 clocks = <&dpll_per_m2_ck>;
1365 func_48m_fclk: func_48m_fclk {
1367 compatible = "fixed-factor-clock";
1368 clocks = <&dpll_per_m2x2_ck>;
1373 func_96m_fclk: func_96m_fclk {
1375 compatible = "fixed-factor-clock";
1376 clocks = <&dpll_per_m2x2_ck>;
1381 l3init_60m_fclk: l3init_60m_fclk {
1383 compatible = "ti,divider-clock";
1384 clocks = <&dpll_usb_m2_ck>;
1386 ti,dividers = <1>, <8>;
1389 dss_32khz_clk: dss_32khz_clk {
1391 compatible = "ti,gate-clock";
1392 clocks = <&sys_32k_ck>;
1393 ti,bit-shift = <11>;
1397 dss_48mhz_clk: dss_48mhz_clk {
1399 compatible = "ti,gate-clock";
1400 clocks = <&func_48m_fclk>;
1405 dss_dss_clk: dss_dss_clk {
1407 compatible = "ti,gate-clock";
1408 clocks = <&dpll_per_h12x2_ck>;
1413 dss_hdmi_clk: dss_hdmi_clk {
1415 compatible = "ti,gate-clock";
1416 clocks = <&hdmi_dpll_clk_mux>;
1417 ti,bit-shift = <10>;
1421 dss_video1_clk: dss_video1_clk {
1423 compatible = "ti,gate-clock";
1424 clocks = <&video1_dpll_clk_mux>;
1425 ti,bit-shift = <12>;
1429 dss_video2_clk: dss_video2_clk {
1431 compatible = "ti,gate-clock";
1432 clocks = <&video2_dpll_clk_mux>;
1433 ti,bit-shift = <13>;
1437 gpio2_dbclk: gpio2_dbclk {
1439 compatible = "ti,gate-clock";
1440 clocks = <&sys_32k_ck>;
1445 gpio3_dbclk: gpio3_dbclk {
1447 compatible = "ti,gate-clock";
1448 clocks = <&sys_32k_ck>;
1453 gpio4_dbclk: gpio4_dbclk {
1455 compatible = "ti,gate-clock";
1456 clocks = <&sys_32k_ck>;
1461 gpio5_dbclk: gpio5_dbclk {
1463 compatible = "ti,gate-clock";
1464 clocks = <&sys_32k_ck>;
1469 gpio6_dbclk: gpio6_dbclk {
1471 compatible = "ti,gate-clock";
1472 clocks = <&sys_32k_ck>;
1477 gpio7_dbclk: gpio7_dbclk {
1479 compatible = "ti,gate-clock";
1480 clocks = <&sys_32k_ck>;
1485 gpio8_dbclk: gpio8_dbclk {
1487 compatible = "ti,gate-clock";
1488 clocks = <&sys_32k_ck>;
1493 mmc1_clk32k: mmc1_clk32k {
1495 compatible = "ti,gate-clock";
1496 clocks = <&sys_32k_ck>;
1501 mmc2_clk32k: mmc2_clk32k {
1503 compatible = "ti,gate-clock";
1504 clocks = <&sys_32k_ck>;
1509 mmc3_clk32k: mmc3_clk32k {
1511 compatible = "ti,gate-clock";
1512 clocks = <&sys_32k_ck>;
1517 mmc4_clk32k: mmc4_clk32k {
1519 compatible = "ti,gate-clock";
1520 clocks = <&sys_32k_ck>;
1525 sata_ref_clk: sata_ref_clk {
1527 compatible = "ti,gate-clock";
1528 clocks = <&sys_clkin1>;
1533 usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
1535 compatible = "ti,gate-clock";
1536 clocks = <&dpll_usb_clkdcoldo>;
1541 usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
1543 compatible = "ti,gate-clock";
1544 clocks = <&dpll_usb_clkdcoldo>;
1549 usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
1551 compatible = "ti,gate-clock";
1552 clocks = <&sys_32k_ck>;
1557 usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
1559 compatible = "ti,gate-clock";
1560 clocks = <&sys_32k_ck>;
1565 usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
1567 compatible = "ti,gate-clock";
1568 clocks = <&sys_32k_ck>;
1573 atl_dpll_clk_mux: atl_dpll_clk_mux {
1575 compatible = "ti,mux-clock";
1576 clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
1577 ti,bit-shift = <24>;
1581 atl_gfclk_mux: atl_gfclk_mux {
1583 compatible = "ti,mux-clock";
1584 clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
1585 ti,bit-shift = <26>;
1589 gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
1591 compatible = "ti,divider-clock";
1592 clocks = <&dpll_gmac_m2_ck>;
1593 ti,bit-shift = <24>;
1598 gmac_rft_clk_mux: gmac_rft_clk_mux {
1600 compatible = "ti,mux-clock";
1601 clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
1602 ti,bit-shift = <25>;
1606 gpu_core_gclk_mux: gpu_core_gclk_mux {
1608 compatible = "ti,mux-clock";
1609 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1610 ti,bit-shift = <24>;
1614 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
1616 compatible = "ti,mux-clock";
1617 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1618 ti,bit-shift = <26>;
1622 l3instr_ts_gclk_div: l3instr_ts_gclk_div {
1624 compatible = "ti,divider-clock";
1625 clocks = <&wkupaon_iclk_mux>;
1626 ti,bit-shift = <24>;
1628 ti,dividers = <8>, <16>, <32>;
1631 mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
1633 compatible = "ti,mux-clock";
1634 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1635 ti,bit-shift = <28>;
1639 mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
1641 compatible = "ti,mux-clock";
1642 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1643 ti,bit-shift = <28>;
1647 mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
1649 compatible = "ti,mux-clock";
1650 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1651 ti,bit-shift = <22>;
1655 mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
1657 compatible = "ti,mux-clock";
1658 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1659 ti,bit-shift = <24>;
1663 mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
1665 compatible = "ti,mux-clock";
1666 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1667 ti,bit-shift = <22>;
1671 mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
1673 compatible = "ti,mux-clock";
1674 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1675 ti,bit-shift = <24>;
1679 mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
1681 compatible = "ti,mux-clock";
1682 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1683 ti,bit-shift = <22>;
1687 mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
1689 compatible = "ti,mux-clock";
1690 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1691 ti,bit-shift = <24>;
1695 mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
1697 compatible = "ti,mux-clock";
1698 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1699 ti,bit-shift = <22>;
1703 mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
1705 compatible = "ti,mux-clock";
1706 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1707 ti,bit-shift = <24>;
1711 mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
1713 compatible = "ti,mux-clock";
1714 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1715 ti,bit-shift = <22>;
1719 mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
1721 compatible = "ti,mux-clock";
1722 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1723 ti,bit-shift = <24>;
1727 mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
1729 compatible = "ti,mux-clock";
1730 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1731 ti,bit-shift = <22>;
1735 mcasp8_ahclk_mux: mcasp8_ahclk_mux {
1737 compatible = "ti,mux-clock";
1738 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1739 ti,bit-shift = <22>;
1743 mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
1745 compatible = "ti,mux-clock";
1746 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1747 ti,bit-shift = <24>;
1751 mmc1_fclk_mux: mmc1_fclk_mux {
1753 compatible = "ti,mux-clock";
1754 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1755 ti,bit-shift = <24>;
1759 mmc1_fclk_div: mmc1_fclk_div {
1761 compatible = "ti,divider-clock";
1762 clocks = <&mmc1_fclk_mux>;
1763 ti,bit-shift = <25>;
1766 ti,index-power-of-two;
1769 mmc2_fclk_mux: mmc2_fclk_mux {
1771 compatible = "ti,mux-clock";
1772 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1773 ti,bit-shift = <24>;
1777 mmc2_fclk_div: mmc2_fclk_div {
1779 compatible = "ti,divider-clock";
1780 clocks = <&mmc2_fclk_mux>;
1781 ti,bit-shift = <25>;
1784 ti,index-power-of-two;
1787 mmc3_gfclk_mux: mmc3_gfclk_mux {
1789 compatible = "ti,mux-clock";
1790 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1791 ti,bit-shift = <24>;
1795 mmc3_gfclk_div: mmc3_gfclk_div {
1797 compatible = "ti,divider-clock";
1798 clocks = <&mmc3_gfclk_mux>;
1799 ti,bit-shift = <25>;
1802 ti,index-power-of-two;
1805 mmc4_gfclk_mux: mmc4_gfclk_mux {
1807 compatible = "ti,mux-clock";
1808 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1809 ti,bit-shift = <24>;
1813 mmc4_gfclk_div: mmc4_gfclk_div {
1815 compatible = "ti,divider-clock";
1816 clocks = <&mmc4_gfclk_mux>;
1817 ti,bit-shift = <25>;
1820 ti,index-power-of-two;
1823 qspi_gfclk_mux: qspi_gfclk_mux {
1825 compatible = "ti,mux-clock";
1826 clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
1827 ti,bit-shift = <24>;
1831 qspi_gfclk_div: qspi_gfclk_div {
1833 compatible = "ti,divider-clock";
1834 clocks = <&qspi_gfclk_mux>;
1835 ti,bit-shift = <25>;
1838 ti,index-power-of-two;
1841 timer10_gfclk_mux: timer10_gfclk_mux {
1843 compatible = "ti,mux-clock";
1844 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1845 ti,bit-shift = <24>;
1849 timer11_gfclk_mux: timer11_gfclk_mux {
1851 compatible = "ti,mux-clock";
1852 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1853 ti,bit-shift = <24>;
1857 timer13_gfclk_mux: timer13_gfclk_mux {
1859 compatible = "ti,mux-clock";
1860 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1861 ti,bit-shift = <24>;
1865 timer14_gfclk_mux: timer14_gfclk_mux {
1867 compatible = "ti,mux-clock";
1868 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1869 ti,bit-shift = <24>;
1873 timer15_gfclk_mux: timer15_gfclk_mux {
1875 compatible = "ti,mux-clock";
1876 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1877 ti,bit-shift = <24>;
1881 timer16_gfclk_mux: timer16_gfclk_mux {
1883 compatible = "ti,mux-clock";
1884 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1885 ti,bit-shift = <24>;
1889 timer2_gfclk_mux: timer2_gfclk_mux {
1891 compatible = "ti,mux-clock";
1892 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1893 ti,bit-shift = <24>;
1897 timer3_gfclk_mux: timer3_gfclk_mux {
1899 compatible = "ti,mux-clock";
1900 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1901 ti,bit-shift = <24>;
1905 timer4_gfclk_mux: timer4_gfclk_mux {
1907 compatible = "ti,mux-clock";
1908 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1909 ti,bit-shift = <24>;
1913 timer9_gfclk_mux: timer9_gfclk_mux {
1915 compatible = "ti,mux-clock";
1916 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1917 ti,bit-shift = <24>;
1921 uart1_gfclk_mux: uart1_gfclk_mux {
1923 compatible = "ti,mux-clock";
1924 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1925 ti,bit-shift = <24>;
1929 uart2_gfclk_mux: uart2_gfclk_mux {
1931 compatible = "ti,mux-clock";
1932 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1933 ti,bit-shift = <24>;
1937 uart3_gfclk_mux: uart3_gfclk_mux {
1939 compatible = "ti,mux-clock";
1940 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1941 ti,bit-shift = <24>;
1945 uart4_gfclk_mux: uart4_gfclk_mux {
1947 compatible = "ti,mux-clock";
1948 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1949 ti,bit-shift = <24>;
1953 uart5_gfclk_mux: uart5_gfclk_mux {
1955 compatible = "ti,mux-clock";
1956 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1957 ti,bit-shift = <24>;
1961 uart7_gfclk_mux: uart7_gfclk_mux {
1963 compatible = "ti,mux-clock";
1964 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1965 ti,bit-shift = <24>;
1969 uart8_gfclk_mux: uart8_gfclk_mux {
1971 compatible = "ti,mux-clock";
1972 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1973 ti,bit-shift = <24>;
1977 uart9_gfclk_mux: uart9_gfclk_mux {
1979 compatible = "ti,mux-clock";
1980 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1981 ti,bit-shift = <24>;
1985 vip1_gclk_mux: vip1_gclk_mux {
1987 compatible = "ti,mux-clock";
1988 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1989 ti,bit-shift = <24>;
1993 vip2_gclk_mux: vip2_gclk_mux {
1995 compatible = "ti,mux-clock";
1996 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1997 ti,bit-shift = <24>;
2001 vip3_gclk_mux: vip3_gclk_mux {
2003 compatible = "ti,mux-clock";
2004 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2005 ti,bit-shift = <24>;
2010 &cm_core_clockdomains {
2011 coreaon_clkdm: coreaon_clkdm {
2012 compatible = "ti,clockdomain";
2013 clocks = <&dpll_usb_ck>;