2 * Device Tree Source for the EMEV2 SoC
4 * Copyright (C) 2012 Renesas Solutions Corp.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include "skeleton.dtsi"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "renesas,emev2";
17 interrupt-parent = <&gic>;
35 compatible = "arm,cortex-a9";
37 clock-frequency = <533000000>;
41 compatible = "arm,cortex-a9";
43 clock-frequency = <533000000>;
47 gic: interrupt-controller@e0020000 {
48 compatible = "arm,pl390";
50 #interrupt-cells = <3>;
51 reg = <0xe0028000 0x1000>,
56 compatible = "arm,cortex-a9-pmu";
57 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
62 compatible = "renesas,emev2-smu";
63 reg = <0xe0110000 0x10000>;
68 compatible = "fixed-clock";
69 clock-frequency = <32768>;
72 iic0_sclkdiv: iic0_sclkdiv {
73 compatible = "renesas,emev2-smu-clkdiv";
78 iic0_sclk: iic0_sclk {
79 compatible = "renesas,emev2-smu-gclk";
81 clocks = <&iic0_sclkdiv>;
84 iic1_sclkdiv: iic1_sclkdiv {
85 compatible = "renesas,emev2-smu-clkdiv";
90 iic1_sclk: iic1_sclk {
91 compatible = "renesas,emev2-smu-gclk";
93 clocks = <&iic1_sclkdiv>;
97 compatible = "fixed-factor-clock";
103 usia_u0_sclkdiv: usia_u0_sclkdiv {
104 compatible = "renesas,emev2-smu-clkdiv";
109 usib_u1_sclkdiv: usib_u1_sclkdiv {
110 compatible = "renesas,emev2-smu-clkdiv";
115 usib_u2_sclkdiv: usib_u2_sclkdiv {
116 compatible = "renesas,emev2-smu-clkdiv";
121 usib_u3_sclkdiv: usib_u3_sclkdiv {
122 compatible = "renesas,emev2-smu-clkdiv";
127 usia_u0_sclk: usia_u0_sclk {
128 compatible = "renesas,emev2-smu-gclk";
130 clocks = <&usia_u0_sclkdiv>;
133 usib_u1_sclk: usib_u1_sclk {
134 compatible = "renesas,emev2-smu-gclk";
136 clocks = <&usib_u1_sclkdiv>;
139 usib_u2_sclk: usib_u2_sclk {
140 compatible = "renesas,emev2-smu-gclk";
142 clocks = <&usib_u2_sclkdiv>;
145 usib_u3_sclk: usib_u3_sclk {
146 compatible = "renesas,emev2-smu-gclk";
148 clocks = <&usib_u3_sclkdiv>;
152 compatible = "renesas,emev2-smu-gclk";
160 compatible = "renesas,em-sti";
161 reg = <0xe0180000 0x54>;
162 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&sti_sclk>;
164 clock-names = "sclk";
167 uart0: serial@e1020000 {
168 compatible = "renesas,em-uart";
169 reg = <0xe1020000 0x38>;
170 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&usia_u0_sclk>;
172 clock-names = "sclk";
175 uart1: serial@e1030000 {
176 compatible = "renesas,em-uart";
177 reg = <0xe1030000 0x38>;
178 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&usib_u1_sclk>;
180 clock-names = "sclk";
183 uart2: serial@e1040000 {
184 compatible = "renesas,em-uart";
185 reg = <0xe1040000 0x38>;
186 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&usib_u2_sclk>;
188 clock-names = "sclk";
191 uart3: serial@e1050000 {
192 compatible = "renesas,em-uart";
193 reg = <0xe1050000 0x38>;
194 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&usib_u3_sclk>;
196 clock-names = "sclk";
200 compatible = "renesas,pfc-emev2";
201 reg = <0xe0140200 0x100>;
204 gpio0: gpio@e0050000 {
205 compatible = "renesas,em-gio";
206 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
207 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
210 gpio-ranges = <&pfc 0 0 32>;
213 interrupt-controller;
214 #interrupt-cells = <2>;
216 gpio1: gpio@e0050080 {
217 compatible = "renesas,em-gio";
218 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
219 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
222 gpio-ranges = <&pfc 0 32 32>;
225 interrupt-controller;
226 #interrupt-cells = <2>;
228 gpio2: gpio@e0050100 {
229 compatible = "renesas,em-gio";
230 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
231 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
234 gpio-ranges = <&pfc 0 64 32>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
240 gpio3: gpio@e0050180 {
241 compatible = "renesas,em-gio";
242 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
243 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
246 gpio-ranges = <&pfc 0 96 32>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
252 gpio4: gpio@e0050200 {
253 compatible = "renesas,em-gio";
254 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
255 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
258 gpio-ranges = <&pfc 0 128 31>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
266 #address-cells = <1>;
268 compatible = "renesas,iic-emev2";
269 reg = <0xe0070000 0x28>;
270 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
271 clocks = <&iic0_sclk>;
272 clock-names = "sclk";
277 #address-cells = <1>;
279 compatible = "renesas,iic-emev2";
280 reg = <0xe10a0000 0x28>;
281 interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
282 clocks = <&iic1_sclk>;
283 clock-names = "sclk";