arch/arm/boot/dts/exynos3250.dtsi

   1 /*
   2  * Samsung's Exynos3250 SoC device tree source
   3  *
   4  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include "skeleton.dtsi"
  21 #include <dt-bindings/clock/exynos3250.h>
  22
  23 / {
  24         compatible = "samsung,exynos3250";
  25         interrupt-parent = <&gic>;
  26
  27         aliases {
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 mshc0 = &mshc_0;
  31                 mshc1 = &mshc_1;
  32                 spi0 = &spi_0;
  33                 spi1 = &spi_1;
  34                 i2c0 = &i2c_0;
  35                 i2c1 = &i2c_1;
  36                 i2c2 = &i2c_2;
  37                 i2c3 = &i2c_3;
  38                 i2c4 = &i2c_4;
  39                 i2c5 = &i2c_5;
  40                 i2c6 = &i2c_6;
  41                 i2c7 = &i2c_7;
  42         };
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 cpu0: cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a7";
  51                         reg = <0>;
  52                         clock-frequency = <1000000000>;
  53                 };
  54
  55                 cpu1: cpu@1 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a7";
  58                         reg = <1>;
  59                         clock-frequency = <1000000000>;
  60                 };
  61         };
  62
  63         soc: soc {
  64                 compatible = "simple-bus";
  65                 #address-cells = <1>;
  66                 #size-cells = <1>;
  67                 ranges;
  68
  69                 fixed-rate-clocks {
  70                         #address-cells = <1>;
  71                         #size-cells = <0>;
  72
  73                         xusbxti: clock@0 {
  74                                 compatible = "fixed-clock";
  75                                 #address-cells = <1>;
  76                                 #size-cells = <0>;
  77                                 reg = <0>;
  78                                 clock-frequency = <0>;
  79                                 #clock-cells = <0>;
  80                                 clock-output-names = "xusbxti";
  81                         };
  82
  83                         xxti: clock@1 {
  84                                 compatible = "fixed-clock";
  85                                 reg = <1>;
  86                                 clock-frequency = <0>;
  87                                 #clock-cells = <0>;
  88                                 clock-output-names = "xxti";
  89                         };
  90
  91                         xtcxo: clock@2 {
  92                                 compatible = "fixed-clock";
  93                                 reg = <2>;
  94                                 clock-frequency = <0>;
  95                                 #clock-cells = <0>;
  96                                 clock-output-names = "xtcxo";
  97                         };
  98                 };
  99
 100                 sysram@02020000 {
 101                         compatible = "mmio-sram";
 102                         reg = <0x02020000 0x40000>;
 103                         #address-cells = <1>;
 104                         #size-cells = <1>;
 105                         ranges = <0 0x02020000 0x40000>;
 106
 107                         smp-sysram@0 {
 108                                 compatible = "samsung,exynos4210-sysram";
 109                                 reg = <0x0 0x1000>;
 110                         };
 111
 112                         smp-sysram@3f000 {
 113                                 compatible = "samsung,exynos4210-sysram-ns";
 114                                 reg = <0x3f000 0x1000>;
 115                         };
 116                 };
 117
 118                 chipid@10000000 {
 119                         compatible = "samsung,exynos4210-chipid";
 120                         reg = <0x10000000 0x100>;
 121                 };
 122
 123                 sys_reg: syscon@10010000 {
 124                         compatible = "samsung,exynos3-sysreg", "syscon";
 125                         reg = <0x10010000 0x400>;
 126                 };
 127
 128                 pmu_system_controller: system-controller@10020000 {
 129                         compatible = "samsung,exynos3250-pmu", "syscon";
 130                         reg = <0x10020000 0x4000>;
 131                 };
 132
 133                 pd_cam: cam-power-domain@10023C00 {
 134                         compatible = "samsung,exynos4210-pd";
 135                         reg = <0x10023C00 0x20>;
 136                 };
 137
 138                 pd_mfc: mfc-power-domain@10023C40 {
 139                         compatible = "samsung,exynos4210-pd";
 140                         reg = <0x10023C40 0x20>;
 141                 };
 142
 143                 pd_g3d: g3d-power-domain@10023C60 {
 144                         compatible = "samsung,exynos4210-pd";
 145                         reg = <0x10023C60 0x20>;
 146                 };
 147
 148                 pd_lcd0: lcd0-power-domain@10023C80 {
 149                         compatible = "samsung,exynos4210-pd";
 150                         reg = <0x10023C80 0x20>;
 151                 };
 152
 153                 pd_isp: isp-power-domain@10023CA0 {
 154                         compatible = "samsung,exynos4210-pd";
 155                         reg = <0x10023CA0 0x20>;
 156                 };
 157
 158                 cmu: clock-controller@10030000 {
 159                         compatible = "samsung,exynos3250-cmu";
 160                         reg = <0x10030000 0x20000>;
 161                         #clock-cells = <1>;
 162                 };
 163
 164                 rtc: rtc@10070000 {
 165                         compatible = "samsung,s3c6410-rtc";
 166                         reg = <0x10070000 0x100>;
 167                         interrupts = <0 73 0>, <0 74 0>;
 168                         status = "disabled";
 169                 };
 170
 171                 gic: interrupt-controller@10481000 {
 172                         compatible = "arm,cortex-a15-gic";
 173                         #interrupt-cells = <3>;
 174                         interrupt-controller;
 175                         reg = <0x10481000 0x1000>,
 176                               <0x10482000 0x1000>,
 177                               <0x10484000 0x2000>,
 178                               <0x10486000 0x2000>;
 179                         interrupts = <1 9 0xf04>;
 180                 };
 181
 182                 mct@10050000 {
 183                         compatible = "samsung,exynos4210-mct";
 184                         reg = <0x10050000 0x800>;
 185                         interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
 186                                      <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
 187                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 188                         clock-names = "fin_pll", "mct";
 189                 };
 190
 191                 pinctrl_1: pinctrl@11000000 {
 192                         compatible = "samsung,exynos3250-pinctrl";
 193                         reg = <0x11000000 0x1000>;
 194                         interrupts = <0 225 0>;
 195
 196                         wakeup-interrupt-controller {
 197                                 compatible = "samsung,exynos4210-wakeup-eint";
 198                                 interrupt-parent = <&gic>;
 199                                 interrupts = <0 48 0>;
 200                         };
 201                 };
 202
 203                 pinctrl_0: pinctrl@11400000 {
 204                         compatible = "samsung,exynos3250-pinctrl";
 205                         reg = <0x11400000 0x1000>;
 206                         interrupts = <0 240 0>;
 207                 };
 208
 209                 mshc_0: mshc@12510000 {
 210                         compatible = "samsung,exynos5250-dw-mshc";
 211                         reg = <0x12510000 0x1000>;
 212                         interrupts = <0 142 0>;
 213                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 214                         clock-names = "biu", "ciu";
 215                         fifo-depth = <0x80>;
 216                         #address-cells = <1>;
 217                         #size-cells = <0>;
 218                         status = "disabled";
 219                 };
 220
 221                 mshc_1: mshc@12520000 {
 222                         compatible = "samsung,exynos5250-dw-mshc";
 223                         reg = <0x12520000 0x1000>;
 224                         interrupts = <0 143 0>;
 225                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 226                         clock-names = "biu", "ciu";
 227                         fifo-depth = <0x80>;
 228                         #address-cells = <1>;
 229                         #size-cells = <0>;
 230                         status = "disabled";
 231                 };
 232
 233                 amba {
 234                         compatible = "arm,amba-bus";
 235                         #address-cells = <1>;
 236                         #size-cells = <1>;
 237                         interrupt-parent = <&gic>;
 238                         ranges;
 239
 240                         pdma0: pdma@12680000 {
 241                                 compatible = "arm,pl330", "arm,primecell";
 242                                 reg = <0x12680000 0x1000>;
 243                                 interrupts = <0 138 0>;
 244                                 clocks = <&cmu CLK_PDMA0>;
 245                                 clock-names = "apb_pclk";
 246                                 #dma-cells = <1>;
 247                                 #dma-channels = <8>;
 248                                 #dma-requests = <32>;
 249                         };
 250
 251                         pdma1: pdma@12690000 {
 252                                 compatible = "arm,pl330", "arm,primecell";
 253                                 reg = <0x12690000 0x1000>;
 254                                 interrupts = <0 139 0>;
 255                                 clocks = <&cmu CLK_PDMA1>;
 256                                 clock-names = "apb_pclk";
 257                                 #dma-cells = <1>;
 258                                 #dma-channels = <8>;
 259                                 #dma-requests = <32>;
 260                         };
 261                 };
 262
 263                 adc: adc@126C0000 {
 264                         compatible = "samsung,exynos-adc-v3";
 265                         reg = <0x126C0000 0x100>, <0x10020718 0x4>;
 266                         interrupts = <0 137 0>;
 267                         clock-names = "adc", "sclk_tsadc";
 268                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 269                         #io-channel-cells = <1>;
 270                         io-channel-ranges;
 271                         status = "disabled";
 272                 };
 273
 274                 serial_0: serial@13800000 {
 275                         compatible = "samsung,exynos4210-uart";
 276                         reg = <0x13800000 0x100>;
 277                         interrupts = <0 109 0>;
 278                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 279                         clock-names = "uart", "clk_uart_baud0";
 280                         status = "disabled";
 281                 };
 282
 283                 serial_1: serial@13810000 {
 284                         compatible = "samsung,exynos4210-uart";
 285                         reg = <0x13810000 0x100>;
 286                         interrupts = <0 110 0>;
 287                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 288                         clock-names = "uart", "clk_uart_baud0";
 289                         status = "disabled";
 290                 };
 291
 292                 i2c_0: i2c@13860000 {
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295                         compatible = "samsung,s3c2440-i2c";
 296                         reg = <0x13860000 0x100>;
 297                         interrupts = <0 113 0>;
 298                         clocks = <&cmu CLK_I2C0>;
 299                         clock-names = "i2c";
 300                         pinctrl-names = "default";
 301                         pinctrl-0 = <&i2c0_bus>;
 302                         status = "disabled";
 303                 };
 304
 305                 i2c_1: i2c@13870000 {
 306                         #address-cells = <1>;
 307                         #size-cells = <0>;
 308                         compatible = "samsung,s3c2440-i2c";
 309                         reg = <0x13870000 0x100>;
 310                         interrupts = <0 114 0>;
 311                         clocks = <&cmu CLK_I2C1>;
 312                         clock-names = "i2c";
 313                         pinctrl-names = "default";
 314                         pinctrl-0 = <&i2c1_bus>;
 315                         status = "disabled";
 316                 };
 317
 318                 i2c_2: i2c@13880000 {
 319                         #address-cells = <1>;
 320                         #size-cells = <0>;
 321                         compatible = "samsung,s3c2440-i2c";
 322                         reg = <0x13880000 0x100>;
 323                         interrupts = <0 115 0>;
 324                         clocks = <&cmu CLK_I2C2>;
 325                         clock-names = "i2c";
 326                         pinctrl-names = "default";
 327                         pinctrl-0 = <&i2c2_bus>;
 328                         status = "disabled";
 329                 };
 330
 331                 i2c_3: i2c@13890000 {
 332                         #address-cells = <1>;
 333                         #size-cells = <0>;
 334                         compatible = "samsung,s3c2440-i2c";
 335                         reg = <0x13890000 0x100>;
 336                         interrupts = <0 116 0>;
 337                         clocks = <&cmu CLK_I2C3>;
 338                         clock-names = "i2c";
 339                         pinctrl-names = "default";
 340                         pinctrl-0 = <&i2c3_bus>;
 341                         status = "disabled";
 342                 };
 343
 344                 i2c_4: i2c@138A0000 {
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         compatible = "samsung,s3c2440-i2c";
 348                         reg = <0x138A0000 0x100>;
 349                         interrupts = <0 117 0>;
 350                         clocks = <&cmu CLK_I2C4>;
 351                         clock-names = "i2c";
 352                         pinctrl-names = "default";
 353                         pinctrl-0 = <&i2c4_bus>;
 354                         status = "disabled";
 355                 };
 356
 357                 i2c_5: i2c@138B0000 {
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         compatible = "samsung,s3c2440-i2c";
 361                         reg = <0x138B0000 0x100>;
 362                         interrupts = <0 118 0>;
 363                         clocks = <&cmu CLK_I2C5>;
 364                         clock-names = "i2c";
 365                         pinctrl-names = "default";
 366                         pinctrl-0 = <&i2c5_bus>;
 367                         status = "disabled";
 368                 };
 369
 370                 i2c_6: i2c@138C0000 {
 371                         #address-cells = <1>;
 372                         #size-cells = <0>;
 373                         compatible = "samsung,s3c2440-i2c";
 374                         reg = <0x138C0000 0x100>;
 375                         interrupts = <0 119 0>;
 376                         clocks = <&cmu CLK_I2C6>;
 377                         clock-names = "i2c";
 378                         pinctrl-names = "default";
 379                         pinctrl-0 = <&i2c6_bus>;
 380                         status = "disabled";
 381                 };
 382
 383                 i2c_7: i2c@138D0000 {
 384                         #address-cells = <1>;
 385                         #size-cells = <0>;
 386                         compatible = "samsung,s3c2440-i2c";
 387                         reg = <0x138D0000 0x100>;
 388                         interrupts = <0 120 0>;
 389                         clocks = <&cmu CLK_I2C7>;
 390                         clock-names = "i2c";
 391                         pinctrl-names = "default";
 392                         pinctrl-0 = <&i2c7_bus>;
 393                         status = "disabled";
 394                 };
 395
 396                 spi_0: spi@13920000 {
 397                         compatible = "samsung,exynos4210-spi";
 398                         reg = <0x13920000 0x100>;
 399                         interrupts = <0 121 0>;
 400                         dmas = <&pdma0 7>, <&pdma0 6>;
 401                         dma-names = "tx", "rx";
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 405                         clock-names = "spi", "spi_busclk0";
 406                         samsung,spi-src-clk = <0>;
 407                         pinctrl-names = "default";
 408                         pinctrl-0 = <&spi0_bus>;
 409                         status = "disabled";
 410                 };
 411
 412                 spi_1: spi@13930000 {
 413                         compatible = "samsung,exynos4210-spi";
 414                         reg = <0x13930000 0x100>;
 415                         interrupts = <0 122 0>;
 416                         dmas = <&pdma1 7>, <&pdma1 6>;
 417                         dma-names = "tx", "rx";
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 421                         clock-names = "spi", "spi_busclk0";
 422                         samsung,spi-src-clk = <0>;
 423                         pinctrl-names = "default";
 424                         pinctrl-0 = <&spi1_bus>;
 425                         status = "disabled";
 426                 };
 427
 428                 pwm: pwm@139D0000 {
 429                         compatible = "samsung,exynos4210-pwm";
 430                         reg = <0x139D0000 0x1000>;
 431                         interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
 432                                      <0 107 0>, <0 108 0>;
 433                         #pwm-cells = <3>;
 434                         status = "disabled";
 435                 };
 436
 437                 pmu {
 438                         compatible = "arm,cortex-a7-pmu";
 439                         interrupts = <0 18 0>, <0 19 0>;
 440                 };
 441         };
 442 };
 443
 444 #include "exynos3250-pinctrl.dtsi"