arch/arm/boot/dts/exynos3250.dtsi

   1 /*
   2  * Samsung's Exynos3250 SoC device tree source
   3  *
   4  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include "exynos4-cpu-thermal.dtsi"
  21 #include "exynos-syscon-restart.dtsi"
  22 #include <dt-bindings/clock/exynos3250.h>
  23 #include <dt-bindings/interrupt-controller/irq.h>
  24
  25 / {
  26         compatible = "samsung,exynos3250";
  27         interrupt-parent = <&gic>;
  28         #address-cells = <1>;
  29         #size-cells = <1>;
  30
  31         aliases {
  32                 pinctrl0 = &pinctrl_0;
  33                 pinctrl1 = &pinctrl_1;
  34                 mshc0 = &mshc_0;
  35                 mshc1 = &mshc_1;
  36                 mshc2 = &mshc_2;
  37                 spi0 = &spi_0;
  38                 spi1 = &spi_1;
  39                 i2c0 = &i2c_0;
  40                 i2c1 = &i2c_1;
  41                 i2c2 = &i2c_2;
  42                 i2c3 = &i2c_3;
  43                 i2c4 = &i2c_4;
  44                 i2c5 = &i2c_5;
  45                 i2c6 = &i2c_6;
  46                 i2c7 = &i2c_7;
  47                 serial0 = &serial_0;
  48                 serial1 = &serial_1;
  49                 serial2 = &serial_2;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55
  56                 cpu0: cpu@0 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a7";
  59                         reg = <0>;
  60                         clock-frequency = <1000000000>;
  61                         clocks = <&cmu CLK_ARM_CLK>;
  62                         clock-names = "cpu";
  63                         #cooling-cells = <2>;
  64
  65                         operating-points = <
  66                                 1000000 1150000
  67                                 900000  1112500
  68                                 800000  1075000
  69                                 700000  1037500
  70                                 600000  1000000
  71                                 500000  962500
  72                                 400000  925000
  73                                 300000  887500
  74                                 200000  850000
  75                                 100000  850000
  76                         >;
  77                 };
  78
  79                 cpu1: cpu@1 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a7";
  82                         reg = <1>;
  83                         clock-frequency = <1000000000>;
  84                 };
  85         };
  86
  87         soc: soc {
  88                 compatible = "simple-bus";
  89                 #address-cells = <1>;
  90                 #size-cells = <1>;
  91                 ranges;
  92
  93                 fixed-rate-clocks {
  94                         #address-cells = <1>;
  95                         #size-cells = <0>;
  96
  97                         xusbxti: clock@0 {
  98                                 compatible = "fixed-clock";
  99                                 #address-cells = <1>;
 100                                 #size-cells = <0>;
 101                                 reg = <0>;
 102                                 clock-frequency = <0>;
 103                                 #clock-cells = <0>;
 104                                 clock-output-names = "xusbxti";
 105                         };
 106
 107                         xxti: clock@1 {
 108                                 compatible = "fixed-clock";
 109                                 reg = <1>;
 110                                 clock-frequency = <0>;
 111                                 #clock-cells = <0>;
 112                                 clock-output-names = "xxti";
 113                         };
 114
 115                         xtcxo: clock@2 {
 116                                 compatible = "fixed-clock";
 117                                 reg = <2>;
 118                                 clock-frequency = <0>;
 119                                 #clock-cells = <0>;
 120                                 clock-output-names = "xtcxo";
 121                         };
 122                 };
 123
 124                 sysram@02020000 {
 125                         compatible = "mmio-sram";
 126                         reg = <0x02020000 0x40000>;
 127                         #address-cells = <1>;
 128                         #size-cells = <1>;
 129                         ranges = <0 0x02020000 0x40000>;
 130
 131                         smp-sysram@0 {
 132                                 compatible = "samsung,exynos4210-sysram";
 133                                 reg = <0x0 0x1000>;
 134                         };
 135
 136                         smp-sysram@3f000 {
 137                                 compatible = "samsung,exynos4210-sysram-ns";
 138                                 reg = <0x3f000 0x1000>;
 139                         };
 140                 };
 141
 142                 chipid@10000000 {
 143                         compatible = "samsung,exynos4210-chipid";
 144                         reg = <0x10000000 0x100>;
 145                 };
 146
 147                 sys_reg: syscon@10010000 {
 148                         compatible = "samsung,exynos3-sysreg", "syscon";
 149                         reg = <0x10010000 0x400>;
 150                 };
 151
 152                 pmu_system_controller: system-controller@10020000 {
 153                         compatible = "samsung,exynos3250-pmu", "syscon";
 154                         reg = <0x10020000 0x4000>;
 155                         interrupt-controller;
 156                         #interrupt-cells = <3>;
 157                         interrupt-parent = <&gic>;
 158                 };
 159
 160                 mipi_phy: video-phy {
 161                         compatible = "samsung,s5pv210-mipi-video-phy";
 162                         #phy-cells = <1>;
 163                         syscon = <&pmu_system_controller>;
 164                 };
 165
 166                 pd_cam: cam-power-domain@10023C00 {
 167                         compatible = "samsung,exynos4210-pd";
 168                         reg = <0x10023C00 0x20>;
 169                         #power-domain-cells = <0>;
 170                 };
 171
 172                 pd_mfc: mfc-power-domain@10023C40 {
 173                         compatible = "samsung,exynos4210-pd";
 174                         reg = <0x10023C40 0x20>;
 175                         #power-domain-cells = <0>;
 176                 };
 177
 178                 pd_g3d: g3d-power-domain@10023C60 {
 179                         compatible = "samsung,exynos4210-pd";
 180                         reg = <0x10023C60 0x20>;
 181                         #power-domain-cells = <0>;
 182                 };
 183
 184                 pd_lcd0: lcd0-power-domain@10023C80 {
 185                         compatible = "samsung,exynos4210-pd";
 186                         reg = <0x10023C80 0x20>;
 187                         #power-domain-cells = <0>;
 188                 };
 189
 190                 pd_isp: isp-power-domain@10023CA0 {
 191                         compatible = "samsung,exynos4210-pd";
 192                         reg = <0x10023CA0 0x20>;
 193                         #power-domain-cells = <0>;
 194                 };
 195
 196                 cmu: clock-controller@10030000 {
 197                         compatible = "samsung,exynos3250-cmu";
 198                         reg = <0x10030000 0x20000>;
 199                         #clock-cells = <1>;
 200                         assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
 201                                           <&cmu CLK_MOUT_ACLK_266_SUB>;
 202                         assigned-clock-parents = <&cmu CLK_FIN_PLL>,
 203                                                  <&cmu CLK_FIN_PLL>;
 204                 };
 205
 206                 cmu_dmc: clock-controller@105C0000 {
 207                         compatible = "samsung,exynos3250-cmu-dmc";
 208                         reg = <0x105C0000 0x2000>;
 209                         #clock-cells = <1>;
 210                 };
 211
 212                 rtc: rtc@10070000 {
 213                         compatible = "samsung,s3c6410-rtc";
 214                         reg = <0x10070000 0x100>;
 215                         interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <0 74 IRQ_TYPE_LEVEL_HIGH>;
 217                         interrupt-parent = <&pmu_system_controller>;
 218                         status = "disabled";
 219                 };
 220
 221                 tmu: tmu@100C0000 {
 222                         compatible = "samsung,exynos3250-tmu";
 223                         reg = <0x100C0000 0x100>;
 224                         interrupts = <0 216 IRQ_TYPE_LEVEL_HIGH>;
 225                         clocks = <&cmu CLK_TMU_APBIF>;
 226                         clock-names = "tmu_apbif";
 227                         #include "exynos4412-tmu-sensor-conf.dtsi"
 228                         status = "disabled";
 229                 };
 230
 231                 gic: interrupt-controller@10481000 {
 232                         compatible = "arm,cortex-a15-gic";
 233                         #interrupt-cells = <3>;
 234                         interrupt-controller;
 235                         reg = <0x10481000 0x1000>,
 236                               <0x10482000 0x1000>,
 237                               <0x10484000 0x2000>,
 238                               <0x10486000 0x2000>;
 239                         interrupts = <1 9 0xf04>;
 240                 };
 241
 242                 mct@10050000 {
 243                         compatible = "samsung,exynos4210-mct";
 244                         reg = <0x10050000 0x800>;
 245                         interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <0 219 IRQ_TYPE_LEVEL_HIGH>,
 247                                      <0 220 IRQ_TYPE_LEVEL_HIGH>,
 248                                      <0 221 IRQ_TYPE_LEVEL_HIGH>,
 249                                      <0 223 IRQ_TYPE_LEVEL_HIGH>,
 250                                      <0 226 IRQ_TYPE_LEVEL_HIGH>,
 251                                      <0 227 IRQ_TYPE_LEVEL_HIGH>,
 252                                      <0 228 IRQ_TYPE_LEVEL_HIGH>;
 253                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 254                         clock-names = "fin_pll", "mct";
 255                 };
 256
 257                 pinctrl_1: pinctrl@11000000 {
 258                         compatible = "samsung,exynos3250-pinctrl";
 259                         reg = <0x11000000 0x1000>;
 260                         interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
 261
 262                         wakeup-interrupt-controller {
 263                                 compatible = "samsung,exynos4210-wakeup-eint";
 264                                 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 265                         };
 266                 };
 267
 268                 pinctrl_0: pinctrl@11400000 {
 269                         compatible = "samsung,exynos3250-pinctrl";
 270                         reg = <0x11400000 0x1000>;
 271                         interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
 272                 };
 273
 274                 jpeg: codec@11830000 {
 275                         compatible = "samsung,exynos3250-jpeg";
 276                         reg = <0x11830000 0x1000>;
 277                         interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH>;
 278                         clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
 279                         clock-names = "jpeg", "sclk";
 280                         power-domains = <&pd_cam>;
 281                         assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
 282                         assigned-clock-rates = <0>, <150000000>;
 283                         assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
 284                         iommus = <&sysmmu_jpeg>;
 285                         status = "disabled";
 286                 };
 287
 288                 sysmmu_jpeg: sysmmu@11A60000 {
 289                         compatible = "samsung,exynos-sysmmu";
 290                         reg = <0x11a60000 0x1000>;
 291                         interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>,
 292                                      <0 161 IRQ_TYPE_LEVEL_HIGH>;
 293                         clock-names = "sysmmu", "master";
 294                         clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
 295                         power-domains = <&pd_cam>;
 296                         #iommu-cells = <0>;
 297                 };
 298
 299                 fimd: fimd@11c00000 {
 300                         compatible = "samsung,exynos3250-fimd";
 301                         reg = <0x11c00000 0x30000>;
 302                         interrupt-names = "fifo", "vsync", "lcd_sys";
 303                         interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <0 85 IRQ_TYPE_LEVEL_HIGH>,
 305                                      <0 86 IRQ_TYPE_LEVEL_HIGH>;
 306                         clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
 307                         clock-names = "sclk_fimd", "fimd";
 308                         power-domains = <&pd_lcd0>;
 309                         iommus = <&sysmmu_fimd0>;
 310                         samsung,sysreg = <&sys_reg>;
 311                         status = "disabled";
 312                 };
 313
 314                 dsi_0: dsi@11C80000 {
 315                         compatible = "samsung,exynos3250-mipi-dsi";
 316                         reg = <0x11C80000 0x10000>;
 317                         interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 318                         samsung,phy-type = <0>;
 319                         power-domains = <&pd_lcd0>;
 320                         phys = <&mipi_phy 1>;
 321                         phy-names = "dsim";
 322                         clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
 323                         clock-names = "bus_clk", "pll_clk";
 324                         #address-cells = <1>;
 325                         #size-cells = <0>;
 326                         status = "disabled";
 327                 };
 328
 329                 sysmmu_fimd0: sysmmu@11E20000 {
 330                         compatible = "samsung,exynos-sysmmu";
 331                         reg = <0x11e20000 0x1000>;
 332                         interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>,
 333                                      <0 81 IRQ_TYPE_LEVEL_HIGH>;
 334                         clock-names = "sysmmu", "master";
 335                         clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
 336                         power-domains = <&pd_lcd0>;
 337                         #iommu-cells = <0>;
 338                 };
 339
 340                 hsotg: hsotg@12480000 {
 341                         compatible = "snps,dwc2";
 342                         reg = <0x12480000 0x20000>;
 343                         interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
 344                         clocks = <&cmu CLK_USBOTG>;
 345                         clock-names = "otg";
 346                         phys = <&exynos_usbphy 0>;
 347                         phy-names = "usb2-phy";
 348                         status = "disabled";
 349                 };
 350
 351                 mshc_0: mshc@12510000 {
 352                         compatible = "samsung,exynos5420-dw-mshc";
 353                         reg = <0x12510000 0x1000>;
 354                         interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
 355                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 356                         clock-names = "biu", "ciu";
 357                         fifo-depth = <0x80>;
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         status = "disabled";
 361                 };
 362
 363                 mshc_1: mshc@12520000 {
 364                         compatible = "samsung,exynos5420-dw-mshc";
 365                         reg = <0x12520000 0x1000>;
 366                         interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
 367                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 368                         clock-names = "biu", "ciu";
 369                         fifo-depth = <0x80>;
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         status = "disabled";
 373                 };
 374
 375                 mshc_2: mshc@12530000 {
 376                         compatible = "samsung,exynos5250-dw-mshc";
 377                         reg = <0x12530000 0x1000>;
 378                         interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 379                         clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
 380                         clock-names = "biu", "ciu";
 381                         fifo-depth = <0x80>;
 382                         #address-cells = <1>;
 383                         #size-cells = <0>;
 384                         status = "disabled";
 385                 };
 386
 387                 exynos_usbphy: exynos-usbphy@125B0000 {
 388                         compatible = "samsung,exynos3250-usb2-phy";
 389                         reg = <0x125B0000 0x100>;
 390                         samsung,pmureg-phandle = <&pmu_system_controller>;
 391                         clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
 392                         clock-names = "phy", "ref";
 393                         #phy-cells = <1>;
 394                         status = "disabled";
 395                 };
 396
 397                 amba {
 398                         compatible = "simple-bus";
 399                         #address-cells = <1>;
 400                         #size-cells = <1>;
 401                         ranges;
 402
 403                         pdma0: pdma@12680000 {
 404                                 compatible = "arm,pl330", "arm,primecell";
 405                                 reg = <0x12680000 0x1000>;
 406                                 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
 407                                 clocks = <&cmu CLK_PDMA0>;
 408                                 clock-names = "apb_pclk";
 409                                 #dma-cells = <1>;
 410                                 #dma-channels = <8>;
 411                                 #dma-requests = <32>;
 412                         };
 413
 414                         pdma1: pdma@12690000 {
 415                                 compatible = "arm,pl330", "arm,primecell";
 416                                 reg = <0x12690000 0x1000>;
 417                                 interrupts = <0 139 IRQ_TYPE_LEVEL_HIGH>;
 418                                 clocks = <&cmu CLK_PDMA1>;
 419                                 clock-names = "apb_pclk";
 420                                 #dma-cells = <1>;
 421                                 #dma-channels = <8>;
 422                                 #dma-requests = <32>;
 423                         };
 424                 };
 425
 426                 adc: adc@126C0000 {
 427                         compatible = "samsung,exynos3250-adc",
 428                                      "samsung,exynos-adc-v2";
 429                         reg = <0x126C0000 0x100>;
 430                         interrupts = <0 137 IRQ_TYPE_LEVEL_HIGH>;
 431                         clock-names = "adc", "sclk";
 432                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 433                         #io-channel-cells = <1>;
 434                         io-channel-ranges;
 435                         samsung,syscon-phandle = <&pmu_system_controller>;
 436                         status = "disabled";
 437                 };
 438
 439                 mfc: codec@13400000 {
 440                         compatible = "samsung,mfc-v7";
 441                         reg = <0x13400000 0x10000>;
 442                         interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
 443                         clock-names = "mfc", "sclk_mfc";
 444                         clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
 445                         power-domains = <&pd_mfc>;
 446                         iommus = <&sysmmu_mfc>;
 447                 };
 448
 449                 sysmmu_mfc: sysmmu@13620000 {
 450                         compatible = "samsung,exynos-sysmmu";
 451                         reg = <0x13620000 0x1000>;
 452                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>,
 453                                      <0 98 IRQ_TYPE_LEVEL_HIGH>;
 454                         clock-names = "sysmmu", "master";
 455                         clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
 456                         power-domains = <&pd_mfc>;
 457                         #iommu-cells = <0>;
 458                 };
 459
 460                 serial_0: serial@13800000 {
 461                         compatible = "samsung,exynos4210-uart";
 462                         reg = <0x13800000 0x100>;
 463                         interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 464                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 465                         clock-names = "uart", "clk_uart_baud0";
 466                         pinctrl-names = "default";
 467                         pinctrl-0 = <&uart0_data &uart0_fctl>;
 468                         status = "disabled";
 469                 };
 470
 471                 serial_1: serial@13810000 {
 472                         compatible = "samsung,exynos4210-uart";
 473                         reg = <0x13810000 0x100>;
 474                         interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 475                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 476                         clock-names = "uart", "clk_uart_baud0";
 477                         pinctrl-names = "default";
 478                         pinctrl-0 = <&uart1_data>;
 479                         status = "disabled";
 480                 };
 481
 482                 serial_2: serial@13820000 {
 483                         compatible = "samsung,exynos4210-uart";
 484                         reg = <0x13820000 0x100>;
 485                         interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 486                         clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
 487                         clock-names = "uart", "clk_uart_baud0";
 488                         pinctrl-names = "default";
 489                         pinctrl-0 = <&uart2_data>;
 490                         status = "disabled";
 491                 };
 492
 493                 i2c_0: i2c@13860000 {
 494                         #address-cells = <1>;
 495                         #size-cells = <0>;
 496                         compatible = "samsung,s3c2440-i2c";
 497                         reg = <0x13860000 0x100>;
 498                         interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
 499                         clocks = <&cmu CLK_I2C0>;
 500                         clock-names = "i2c";
 501                         pinctrl-names = "default";
 502                         pinctrl-0 = <&i2c0_bus>;
 503                         status = "disabled";
 504                 };
 505
 506                 i2c_1: i2c@13870000 {
 507                         #address-cells = <1>;
 508                         #size-cells = <0>;
 509                         compatible = "samsung,s3c2440-i2c";
 510                         reg = <0x13870000 0x100>;
 511                         interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 512                         clocks = <&cmu CLK_I2C1>;
 513                         clock-names = "i2c";
 514                         pinctrl-names = "default";
 515                         pinctrl-0 = <&i2c1_bus>;
 516                         status = "disabled";
 517                 };
 518
 519                 i2c_2: i2c@13880000 {
 520                         #address-cells = <1>;
 521                         #size-cells = <0>;
 522                         compatible = "samsung,s3c2440-i2c";
 523                         reg = <0x13880000 0x100>;
 524                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&cmu CLK_I2C2>;
 526                         clock-names = "i2c";
 527                         pinctrl-names = "default";
 528                         pinctrl-0 = <&i2c2_bus>;
 529                         status = "disabled";
 530                 };
 531
 532                 i2c_3: i2c@13890000 {
 533                         #address-cells = <1>;
 534                         #size-cells = <0>;
 535                         compatible = "samsung,s3c2440-i2c";
 536                         reg = <0x13890000 0x100>;
 537                         interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
 538                         clocks = <&cmu CLK_I2C3>;
 539                         clock-names = "i2c";
 540                         pinctrl-names = "default";
 541                         pinctrl-0 = <&i2c3_bus>;
 542                         status = "disabled";
 543                 };
 544
 545                 i2c_4: i2c@138A0000 {
 546                         #address-cells = <1>;
 547                         #size-cells = <0>;
 548                         compatible = "samsung,s3c2440-i2c";
 549                         reg = <0x138A0000 0x100>;
 550                         interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
 551                         clocks = <&cmu CLK_I2C4>;
 552                         clock-names = "i2c";
 553                         pinctrl-names = "default";
 554                         pinctrl-0 = <&i2c4_bus>;
 555                         status = "disabled";
 556                 };
 557
 558                 i2c_5: i2c@138B0000 {
 559                         #address-cells = <1>;
 560                         #size-cells = <0>;
 561                         compatible = "samsung,s3c2440-i2c";
 562                         reg = <0x138B0000 0x100>;
 563                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&cmu CLK_I2C5>;
 565                         clock-names = "i2c";
 566                         pinctrl-names = "default";
 567                         pinctrl-0 = <&i2c5_bus>;
 568                         status = "disabled";
 569                 };
 570
 571                 i2c_6: i2c@138C0000 {
 572                         #address-cells = <1>;
 573                         #size-cells = <0>;
 574                         compatible = "samsung,s3c2440-i2c";
 575                         reg = <0x138C0000 0x100>;
 576                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 577                         clocks = <&cmu CLK_I2C6>;
 578                         clock-names = "i2c";
 579                         pinctrl-names = "default";
 580                         pinctrl-0 = <&i2c6_bus>;
 581                         status = "disabled";
 582                 };
 583
 584                 i2c_7: i2c@138D0000 {
 585                         #address-cells = <1>;
 586                         #size-cells = <0>;
 587                         compatible = "samsung,s3c2440-i2c";
 588                         reg = <0x138D0000 0x100>;
 589                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 590                         clocks = <&cmu CLK_I2C7>;
 591                         clock-names = "i2c";
 592                         pinctrl-names = "default";
 593                         pinctrl-0 = <&i2c7_bus>;
 594                         status = "disabled";
 595                 };
 596
 597                 spi_0: spi@13920000 {
 598                         compatible = "samsung,exynos4210-spi";
 599                         reg = <0x13920000 0x100>;
 600                         interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
 601                         dmas = <&pdma0 7>, <&pdma0 6>;
 602                         dma-names = "tx", "rx";
 603                         #address-cells = <1>;
 604                         #size-cells = <0>;
 605                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 606                         clock-names = "spi", "spi_busclk0";
 607                         samsung,spi-src-clk = <0>;
 608                         pinctrl-names = "default";
 609                         pinctrl-0 = <&spi0_bus>;
 610                         status = "disabled";
 611                 };
 612
 613                 spi_1: spi@13930000 {
 614                         compatible = "samsung,exynos4210-spi";
 615                         reg = <0x13930000 0x100>;
 616                         interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
 617                         dmas = <&pdma1 7>, <&pdma1 6>;
 618                         dma-names = "tx", "rx";
 619                         #address-cells = <1>;
 620                         #size-cells = <0>;
 621                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 622                         clock-names = "spi", "spi_busclk0";
 623                         samsung,spi-src-clk = <0>;
 624                         pinctrl-names = "default";
 625                         pinctrl-0 = <&spi1_bus>;
 626                         status = "disabled";
 627                 };
 628
 629                 i2s2: i2s@13970000 {
 630                         compatible = "samsung,s3c6410-i2s";
 631                         reg = <0x13970000 0x100>;
 632                         interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
 633                         clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
 634                         clock-names = "iis", "i2s_opclk0";
 635                         dmas = <&pdma0 14>, <&pdma0 13>;
 636                         dma-names = "tx", "rx";
 637                         pinctrl-0 = <&i2s2_bus>;
 638                         pinctrl-names = "default";
 639                         status = "disabled";
 640                 };
 641
 642                 pwm: pwm@139D0000 {
 643                         compatible = "samsung,exynos4210-pwm";
 644                         reg = <0x139D0000 0x1000>;
 645                         interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>,
 646                                      <0 105 IRQ_TYPE_LEVEL_HIGH>,
 647                                      <0 106 IRQ_TYPE_LEVEL_HIGH>,
 648                                      <0 107 IRQ_TYPE_LEVEL_HIGH>,
 649                                      <0 108 IRQ_TYPE_LEVEL_HIGH>;
 650                         #pwm-cells = <3>;
 651                         status = "disabled";
 652                 };
 653
 654                 pmu {
 655                         compatible = "arm,cortex-a7-pmu";
 656                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>,
 657                                      <0 19 IRQ_TYPE_LEVEL_HIGH>;
 658                 };
 659
 660                 ppmu_dmc0: ppmu_dmc0@106a0000 {
 661                         compatible = "samsung,exynos-ppmu";
 662                         reg = <0x106a0000 0x2000>;
 663                         status = "disabled";
 664                 };
 665
 666                 ppmu_dmc1: ppmu_dmc1@106b0000 {
 667                         compatible = "samsung,exynos-ppmu";
 668                         reg = <0x106b0000 0x2000>;
 669                         status = "disabled";
 670                 };
 671
 672                 ppmu_cpu: ppmu_cpu@106c0000 {
 673                         compatible = "samsung,exynos-ppmu";
 674                         reg = <0x106c0000 0x2000>;
 675                         status = "disabled";
 676                 };
 677
 678                 ppmu_rightbus: ppmu_rightbus@112a0000 {
 679                         compatible = "samsung,exynos-ppmu";
 680                         reg = <0x112a0000 0x2000>;
 681                         clocks = <&cmu CLK_PPMURIGHT>;
 682                         clock-names = "ppmu";
 683                         status = "disabled";
 684                 };
 685
 686                 ppmu_leftbus: ppmu_leftbus0@116a0000 {
 687                         compatible = "samsung,exynos-ppmu";
 688                         reg = <0x116a0000 0x2000>;
 689                         clocks = <&cmu CLK_PPMULEFT>;
 690                         clock-names = "ppmu";
 691                         status = "disabled";
 692                 };
 693
 694                 ppmu_camif: ppmu_camif@11ac0000 {
 695                         compatible = "samsung,exynos-ppmu";
 696                         reg = <0x11ac0000 0x2000>;
 697                         clocks = <&cmu CLK_PPMUCAMIF>;
 698                         clock-names = "ppmu";
 699                         status = "disabled";
 700                 };
 701
 702                 ppmu_lcd0: ppmu_lcd0@11e40000 {
 703                         compatible = "samsung,exynos-ppmu";
 704                         reg = <0x11e40000 0x2000>;
 705                         clocks = <&cmu CLK_PPMULCD0>;
 706                         clock-names = "ppmu";
 707                         status = "disabled";
 708                 };
 709
 710                 ppmu_fsys: ppmu_fsys@12630000 {
 711                         compatible = "samsung,exynos-ppmu";
 712                         reg = <0x12630000 0x2000>;
 713                         clocks = <&cmu CLK_PPMUFILE>;
 714                         clock-names = "ppmu";
 715                         status = "disabled";
 716                 };
 717
 718                 ppmu_g3d: ppmu_g3d@13220000 {
 719                         compatible = "samsung,exynos-ppmu";
 720                         reg = <0x13220000 0x2000>;
 721                         clocks = <&cmu CLK_PPMUG3D>;
 722                         clock-names = "ppmu";
 723                         status = "disabled";
 724                 };
 725
 726                 ppmu_mfc: ppmu_mfc@13660000 {
 727                         compatible = "samsung,exynos-ppmu";
 728                         reg = <0x13660000 0x2000>;
 729                         clocks = <&cmu CLK_PPMUMFC_L>;
 730                         clock-names = "ppmu";
 731                         status = "disabled";
 732                 };
 733
 734                 bus_dmc: bus_dmc {
 735                         compatible = "samsung,exynos-bus";
 736                         clocks = <&cmu_dmc CLK_DIV_DMC>;
 737                         clock-names = "bus";
 738                         operating-points-v2 = <&bus_dmc_opp_table>;
 739                         status = "disabled";
 740                 };
 741
 742                 bus_dmc_opp_table: opp_table1 {
 743                         compatible = "operating-points-v2";
 744                         opp-shared;
 745
 746                         opp@50000000 {
 747                                 opp-hz = /bits/ 64 <50000000>;
 748                                 opp-microvolt = <800000>;
 749                         };
 750                         opp@100000000 {
 751                                 opp-hz = /bits/ 64 <100000000>;
 752                                 opp-microvolt = <800000>;
 753                         };
 754                         opp@134000000 {
 755                                 opp-hz = /bits/ 64 <134000000>;
 756                                 opp-microvolt = <800000>;
 757                         };
 758                         opp@200000000 {
 759                                 opp-hz = /bits/ 64 <200000000>;
 760                                 opp-microvolt = <825000>;
 761                         };
 762                         opp@400000000 {
 763                                 opp-hz = /bits/ 64 <400000000>;
 764                                 opp-microvolt = <875000>;
 765                         };
 766                 };
 767
 768                 bus_leftbus: bus_leftbus {
 769                         compatible = "samsung,exynos-bus";
 770                         clocks = <&cmu CLK_DIV_GDL>;
 771                         clock-names = "bus";
 772                         operating-points-v2 = <&bus_leftbus_opp_table>;
 773                         status = "disabled";
 774                 };
 775
 776                 bus_rightbus: bus_rightbus {
 777                         compatible = "samsung,exynos-bus";
 778                         clocks = <&cmu CLK_DIV_GDR>;
 779                         clock-names = "bus";
 780                         operating-points-v2 = <&bus_leftbus_opp_table>;
 781                         status = "disabled";
 782                 };
 783
 784                 bus_lcd0: bus_lcd0 {
 785                         compatible = "samsung,exynos-bus";
 786                         clocks = <&cmu CLK_DIV_ACLK_160>;
 787                         clock-names = "bus";
 788                         operating-points-v2 = <&bus_leftbus_opp_table>;
 789                         status = "disabled";
 790                 };
 791
 792                 bus_fsys: bus_fsys {
 793                         compatible = "samsung,exynos-bus";
 794                         clocks = <&cmu CLK_DIV_ACLK_200>;
 795                         clock-names = "bus";
 796                         operating-points-v2 = <&bus_leftbus_opp_table>;
 797                         status = "disabled";
 798                 };
 799
 800                 bus_mcuisp: bus_mcuisp {
 801                         compatible = "samsung,exynos-bus";
 802                         clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
 803                         clock-names = "bus";
 804                         operating-points-v2 = <&bus_mcuisp_opp_table>;
 805                         status = "disabled";
 806                 };
 807
 808                 bus_isp: bus_isp {
 809                         compatible = "samsung,exynos-bus";
 810                         clocks = <&cmu CLK_DIV_ACLK_266>;
 811                         clock-names = "bus";
 812                         operating-points-v2 = <&bus_isp_opp_table>;
 813                         status = "disabled";
 814                 };
 815
 816                 bus_peril: bus_peril {
 817                         compatible = "samsung,exynos-bus";
 818                         clocks = <&cmu CLK_DIV_ACLK_100>;
 819                         clock-names = "bus";
 820                         operating-points-v2 = <&bus_peril_opp_table>;
 821                         status = "disabled";
 822                 };
 823
 824                 bus_mfc: bus_mfc {
 825                         compatible = "samsung,exynos-bus";
 826                         clocks = <&cmu CLK_SCLK_MFC>;
 827                         clock-names = "bus";
 828                         operating-points-v2 = <&bus_leftbus_opp_table>;
 829                         status = "disabled";
 830                 };
 831
 832                 bus_leftbus_opp_table: opp_table2 {
 833                         compatible = "operating-points-v2";
 834                         opp-shared;
 835
 836                         opp@50000000 {
 837                                 opp-hz = /bits/ 64 <50000000>;
 838                                 opp-microvolt = <900000>;
 839                         };
 840                         opp@80000000 {
 841                                 opp-hz = /bits/ 64 <80000000>;
 842                                 opp-microvolt = <900000>;
 843                         };
 844                         opp@100000000 {
 845                                 opp-hz = /bits/ 64 <100000000>;
 846                                 opp-microvolt = <1000000>;
 847                         };
 848                         opp@134000000 {
 849                                 opp-hz = /bits/ 64 <134000000>;
 850                                 opp-microvolt = <1000000>;
 851                         };
 852                         opp@200000000 {
 853                                 opp-hz = /bits/ 64 <200000000>;
 854                                 opp-microvolt = <1000000>;
 855                         };
 856                 };
 857
 858                 bus_mcuisp_opp_table: opp_table3 {
 859                         compatible = "operating-points-v2";
 860                         opp-shared;
 861
 862                         opp@50000000 {
 863                                 opp-hz = /bits/ 64 <50000000>;
 864                         };
 865                         opp@80000000 {
 866                                 opp-hz = /bits/ 64 <80000000>;
 867                         };
 868                         opp@100000000 {
 869                                 opp-hz = /bits/ 64 <100000000>;
 870                         };
 871                         opp@200000000 {
 872                                 opp-hz = /bits/ 64 <200000000>;
 873                         };
 874                         opp@400000000 {
 875                                 opp-hz = /bits/ 64 <400000000>;
 876                         };
 877                 };
 878
 879                 bus_isp_opp_table: opp_table4 {
 880                         compatible = "operating-points-v2";
 881                         opp-shared;
 882
 883                         opp@50000000 {
 884                                 opp-hz = /bits/ 64 <50000000>;
 885                         };
 886                         opp@80000000 {
 887                                 opp-hz = /bits/ 64 <80000000>;
 888                         };
 889                         opp@100000000 {
 890                                 opp-hz = /bits/ 64 <100000000>;
 891                         };
 892                         opp@200000000 {
 893                                 opp-hz = /bits/ 64 <200000000>;
 894                         };
 895                         opp@300000000 {
 896                                 opp-hz = /bits/ 64 <300000000>;
 897                         };
 898                 };
 899
 900                 bus_peril_opp_table: opp_table5 {
 901                         compatible = "operating-points-v2";
 902                         opp-shared;
 903
 904                         opp@50000000 {
 905                                 opp-hz = /bits/ 64 <50000000>;
 906                         };
 907                         opp@80000000 {
 908                                 opp-hz = /bits/ 64 <80000000>;
 909                         };
 910                         opp@100000000 {
 911                                 opp-hz = /bits/ 64 <100000000>;
 912                         };
 913                 };
 914         };
 915 };
 916
 917 #include "exynos3250-pinctrl.dtsi"