2 * Samsung's Exynos4 SoC series common device tree source
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
9 * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
10 * SoCs from Exynos4 series can include this file and provide values for SoCs
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
15 * nodes can be added to this file.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #include <dt-bindings/clock/exynos4.h>
23 #include <dt-bindings/clock/exynos-audss-clk.h>
24 #include "skeleton.dtsi"
27 interrupt-parent = <&gic>;
49 clock_audss: clock-controller@03810000 {
50 compatible = "samsung,exynos4210-audss-clock";
51 reg = <0x03810000 0x0C>;
56 compatible = "samsung,s5pv210-i2s";
57 reg = <0x03830000 0x100>;
58 clocks = <&clock_audss EXYNOS_I2S_BUS>;
60 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
61 dma-names = "tx", "rx", "tx-sec";
62 samsung,idma-addr = <0x03000000>;
67 compatible = "samsung,exynos4210-chipid";
68 reg = <0x10000000 0x100>;
71 mipi_phy: video-phy@10020710 {
72 compatible = "samsung,s5pv210-mipi-video-phy";
77 pd_mfc: mfc-power-domain@10023C40 {
78 compatible = "samsung,exynos4210-pd";
79 reg = <0x10023C40 0x20>;
82 pd_g3d: g3d-power-domain@10023C60 {
83 compatible = "samsung,exynos4210-pd";
84 reg = <0x10023C60 0x20>;
87 pd_lcd0: lcd0-power-domain@10023C80 {
88 compatible = "samsung,exynos4210-pd";
89 reg = <0x10023C80 0x20>;
92 pd_tv: tv-power-domain@10023C20 {
93 compatible = "samsung,exynos4210-pd";
94 reg = <0x10023C20 0x20>;
97 pd_cam: cam-power-domain@10023C00 {
98 compatible = "samsung,exynos4210-pd";
99 reg = <0x10023C00 0x20>;
102 pd_gps: gps-power-domain@10023CE0 {
103 compatible = "samsung,exynos4210-pd";
104 reg = <0x10023CE0 0x20>;
107 pd_gps_alive: gps-alive-power-domain@10023D00 {
108 compatible = "samsung,exynos4210-pd";
109 reg = <0x10023D00 0x20>;
112 gic: interrupt-controller@10490000 {
113 compatible = "arm,cortex-a9-gic";
114 #interrupt-cells = <3>;
115 interrupt-controller;
116 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
119 combiner: interrupt-controller@10440000 {
120 compatible = "samsung,exynos4210-combiner";
121 #interrupt-cells = <2>;
122 interrupt-controller;
123 reg = <0x10440000 0x1000>;
126 sys_reg: syscon@10010000 {
127 compatible = "samsung,exynos4-sysreg", "syscon";
128 reg = <0x10010000 0x400>;
131 pmu_system_controller: system-controller@10020000 {
132 compatible = "samsung,exynos4210-pmu", "syscon";
133 reg = <0x10020000 0x4000>;
136 dsi_0: dsi@11C80000 {
137 compatible = "samsung,exynos4210-mipi-dsi";
138 reg = <0x11C80000 0x10000>;
139 interrupts = <0 79 0>;
140 samsung,power-domain = <&pd_lcd0>;
141 phys = <&mipi_phy 1>;
143 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
144 clock-names = "bus_clk", "pll_clk";
146 #address-cells = <1>;
151 compatible = "samsung,fimc", "simple-bus";
153 #address-cells = <1>;
156 clock-output-names = "cam_a_clkout", "cam_b_clkout";
159 fimc_0: fimc@11800000 {
160 compatible = "samsung,exynos4210-fimc";
161 reg = <0x11800000 0x1000>;
162 interrupts = <0 84 0>;
163 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
164 clock-names = "fimc", "sclk_fimc";
165 samsung,power-domain = <&pd_cam>;
166 samsung,sysreg = <&sys_reg>;
170 fimc_1: fimc@11810000 {
171 compatible = "samsung,exynos4210-fimc";
172 reg = <0x11810000 0x1000>;
173 interrupts = <0 85 0>;
174 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
175 clock-names = "fimc", "sclk_fimc";
176 samsung,power-domain = <&pd_cam>;
177 samsung,sysreg = <&sys_reg>;
181 fimc_2: fimc@11820000 {
182 compatible = "samsung,exynos4210-fimc";
183 reg = <0x11820000 0x1000>;
184 interrupts = <0 86 0>;
185 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
186 clock-names = "fimc", "sclk_fimc";
187 samsung,power-domain = <&pd_cam>;
188 samsung,sysreg = <&sys_reg>;
192 fimc_3: fimc@11830000 {
193 compatible = "samsung,exynos4210-fimc";
194 reg = <0x11830000 0x1000>;
195 interrupts = <0 87 0>;
196 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
197 clock-names = "fimc", "sclk_fimc";
198 samsung,power-domain = <&pd_cam>;
199 samsung,sysreg = <&sys_reg>;
203 csis_0: csis@11880000 {
204 compatible = "samsung,exynos4210-csis";
205 reg = <0x11880000 0x4000>;
206 interrupts = <0 78 0>;
207 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
208 clock-names = "csis", "sclk_csis";
210 samsung,power-domain = <&pd_cam>;
211 phys = <&mipi_phy 0>;
214 #address-cells = <1>;
218 csis_1: csis@11890000 {
219 compatible = "samsung,exynos4210-csis";
220 reg = <0x11890000 0x4000>;
221 interrupts = <0 80 0>;
222 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
223 clock-names = "csis", "sclk_csis";
225 samsung,power-domain = <&pd_cam>;
226 phys = <&mipi_phy 2>;
229 #address-cells = <1>;
235 compatible = "samsung,s3c2410-wdt";
236 reg = <0x10060000 0x100>;
237 interrupts = <0 43 0>;
238 clocks = <&clock CLK_WDT>;
239 clock-names = "watchdog";
244 compatible = "samsung,s3c6410-rtc";
245 reg = <0x10070000 0x100>;
246 interrupts = <0 44 0>, <0 45 0>;
247 clocks = <&clock CLK_RTC>;
253 compatible = "samsung,s5pv210-keypad";
254 reg = <0x100A0000 0x100>;
255 interrupts = <0 109 0>;
256 clocks = <&clock CLK_KEYIF>;
257 clock-names = "keypad";
262 compatible = "samsung,exynos4210-sdhci";
263 reg = <0x12510000 0x100>;
264 interrupts = <0 73 0>;
265 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
266 clock-names = "hsmmc", "mmc_busclk.2";
271 compatible = "samsung,exynos4210-sdhci";
272 reg = <0x12520000 0x100>;
273 interrupts = <0 74 0>;
274 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
275 clock-names = "hsmmc", "mmc_busclk.2";
280 compatible = "samsung,exynos4210-sdhci";
281 reg = <0x12530000 0x100>;
282 interrupts = <0 75 0>;
283 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
284 clock-names = "hsmmc", "mmc_busclk.2";
289 compatible = "samsung,exynos4210-sdhci";
290 reg = <0x12540000 0x100>;
291 interrupts = <0 76 0>;
292 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
293 clock-names = "hsmmc", "mmc_busclk.2";
297 exynos_usbphy: exynos-usbphy@125B0000 {
298 compatible = "samsung,exynos4210-usb2-phy";
299 reg = <0x125B0000 0x100>;
300 samsung,pmureg-phandle = <&pmu_system_controller>;
301 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
302 clock-names = "phy", "ref";
308 compatible = "samsung,exynos4210-ehci";
309 reg = <0x12580000 0x100>;
310 interrupts = <0 70 0>;
311 clocks = <&clock CLK_USB_HOST>;
312 clock-names = "usbhost";
317 compatible = "samsung,exynos4210-ohci";
318 reg = <0x12590000 0x100>;
319 interrupts = <0 70 0>;
320 clocks = <&clock CLK_USB_HOST>;
321 clock-names = "usbhost";
326 compatible = "samsung,s5pv210-i2s";
327 reg = <0x13960000 0x100>;
328 clocks = <&clock CLK_I2S1>;
330 dmas = <&pdma1 12>, <&pdma1 11>;
331 dma-names = "tx", "rx";
336 compatible = "samsung,s5pv210-i2s";
337 reg = <0x13970000 0x100>;
338 clocks = <&clock CLK_I2S2>;
340 dmas = <&pdma0 14>, <&pdma0 13>;
341 dma-names = "tx", "rx";
345 mfc: codec@13400000 {
346 compatible = "samsung,mfc-v5";
347 reg = <0x13400000 0x10000>;
348 interrupts = <0 94 0>;
349 samsung,power-domain = <&pd_mfc>;
350 clocks = <&clock CLK_MFC>;
356 compatible = "samsung,exynos4210-uart";
357 reg = <0x13800000 0x100>;
358 interrupts = <0 52 0>;
359 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
360 clock-names = "uart", "clk_uart_baud0";
365 compatible = "samsung,exynos4210-uart";
366 reg = <0x13810000 0x100>;
367 interrupts = <0 53 0>;
368 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
369 clock-names = "uart", "clk_uart_baud0";
374 compatible = "samsung,exynos4210-uart";
375 reg = <0x13820000 0x100>;
376 interrupts = <0 54 0>;
377 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
378 clock-names = "uart", "clk_uart_baud0";
383 compatible = "samsung,exynos4210-uart";
384 reg = <0x13830000 0x100>;
385 interrupts = <0 55 0>;
386 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
387 clock-names = "uart", "clk_uart_baud0";
391 i2c_0: i2c@13860000 {
392 #address-cells = <1>;
394 compatible = "samsung,s3c2440-i2c";
395 reg = <0x13860000 0x100>;
396 interrupts = <0 58 0>;
397 clocks = <&clock CLK_I2C0>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&i2c0_bus>;
404 i2c_1: i2c@13870000 {
405 #address-cells = <1>;
407 compatible = "samsung,s3c2440-i2c";
408 reg = <0x13870000 0x100>;
409 interrupts = <0 59 0>;
410 clocks = <&clock CLK_I2C1>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&i2c1_bus>;
417 i2c_2: i2c@13880000 {
418 #address-cells = <1>;
420 compatible = "samsung,s3c2440-i2c";
421 reg = <0x13880000 0x100>;
422 interrupts = <0 60 0>;
423 clocks = <&clock CLK_I2C2>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&i2c2_bus>;
430 i2c_3: i2c@13890000 {
431 #address-cells = <1>;
433 compatible = "samsung,s3c2440-i2c";
434 reg = <0x13890000 0x100>;
435 interrupts = <0 61 0>;
436 clocks = <&clock CLK_I2C3>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&i2c3_bus>;
443 i2c_4: i2c@138A0000 {
444 #address-cells = <1>;
446 compatible = "samsung,s3c2440-i2c";
447 reg = <0x138A0000 0x100>;
448 interrupts = <0 62 0>;
449 clocks = <&clock CLK_I2C4>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&i2c4_bus>;
456 i2c_5: i2c@138B0000 {
457 #address-cells = <1>;
459 compatible = "samsung,s3c2440-i2c";
460 reg = <0x138B0000 0x100>;
461 interrupts = <0 63 0>;
462 clocks = <&clock CLK_I2C5>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&i2c5_bus>;
469 i2c_6: i2c@138C0000 {
470 #address-cells = <1>;
472 compatible = "samsung,s3c2440-i2c";
473 reg = <0x138C0000 0x100>;
474 interrupts = <0 64 0>;
475 clocks = <&clock CLK_I2C6>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&i2c6_bus>;
482 i2c_7: i2c@138D0000 {
483 #address-cells = <1>;
485 compatible = "samsung,s3c2440-i2c";
486 reg = <0x138D0000 0x100>;
487 interrupts = <0 65 0>;
488 clocks = <&clock CLK_I2C7>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&i2c7_bus>;
495 spi_0: spi@13920000 {
496 compatible = "samsung,exynos4210-spi";
497 reg = <0x13920000 0x100>;
498 interrupts = <0 66 0>;
499 dmas = <&pdma0 7>, <&pdma0 6>;
500 dma-names = "tx", "rx";
501 #address-cells = <1>;
503 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
504 clock-names = "spi", "spi_busclk0";
505 pinctrl-names = "default";
506 pinctrl-0 = <&spi0_bus>;
510 spi_1: spi@13930000 {
511 compatible = "samsung,exynos4210-spi";
512 reg = <0x13930000 0x100>;
513 interrupts = <0 67 0>;
514 dmas = <&pdma1 7>, <&pdma1 6>;
515 dma-names = "tx", "rx";
516 #address-cells = <1>;
518 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
519 clock-names = "spi", "spi_busclk0";
520 pinctrl-names = "default";
521 pinctrl-0 = <&spi1_bus>;
525 spi_2: spi@13940000 {
526 compatible = "samsung,exynos4210-spi";
527 reg = <0x13940000 0x100>;
528 interrupts = <0 68 0>;
529 dmas = <&pdma0 9>, <&pdma0 8>;
530 dma-names = "tx", "rx";
531 #address-cells = <1>;
533 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
534 clock-names = "spi", "spi_busclk0";
535 pinctrl-names = "default";
536 pinctrl-0 = <&spi2_bus>;
541 compatible = "samsung,exynos4210-pwm";
542 reg = <0x139D0000 0x1000>;
543 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
544 clocks = <&clock CLK_PWM>;
545 clock-names = "timers";
551 #address-cells = <1>;
553 compatible = "arm,amba-bus";
554 interrupt-parent = <&gic>;
557 pdma0: pdma@12680000 {
558 compatible = "arm,pl330", "arm,primecell";
559 reg = <0x12680000 0x1000>;
560 interrupts = <0 35 0>;
561 clocks = <&clock CLK_PDMA0>;
562 clock-names = "apb_pclk";
565 #dma-requests = <32>;
568 pdma1: pdma@12690000 {
569 compatible = "arm,pl330", "arm,primecell";
570 reg = <0x12690000 0x1000>;
571 interrupts = <0 36 0>;
572 clocks = <&clock CLK_PDMA1>;
573 clock-names = "apb_pclk";
576 #dma-requests = <32>;
579 mdma1: mdma@12850000 {
580 compatible = "arm,pl330", "arm,primecell";
581 reg = <0x12850000 0x1000>;
582 interrupts = <0 34 0>;
583 clocks = <&clock CLK_MDMA>;
584 clock-names = "apb_pclk";
591 fimd: fimd@11c00000 {
592 compatible = "samsung,exynos4210-fimd";
593 interrupt-parent = <&combiner>;
594 reg = <0x11c00000 0x20000>;
595 interrupt-names = "fifo", "vsync", "lcd_sys";
596 interrupts = <11 0>, <11 1>, <11 2>;
597 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
598 clock-names = "sclk_fimd", "fimd";
599 samsung,power-domain = <&pd_lcd0>;