arch/arm/boot/dts/exynos4.dtsi

   1 /*
   2  * Samsung's Exynos4 SoC series common device tree source
   3  *
   4  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2010-2011 Linaro Ltd.
   7  *              www.linaro.org
   8  *
   9  * Samsung's Exynos4 SoC series device nodes are listed in this file.  Particular
  10  * SoCs from Exynos4 series can include this file and provide values for SoCs
  11  * specfic bindings.
  12  *
  13  * Note: This file does not include device nodes for all the controllers in
  14  * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
  15  * nodes can be added to this file.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 #include <dt-bindings/clock/exynos4.h>
  23 #include <dt-bindings/clock/exynos-audss-clk.h>
  24 #include "skeleton.dtsi"
  25
  26 / {
  27         interrupt-parent = <&gic>;
  28
  29         aliases {
  30                 spi0 = &spi_0;
  31                 spi1 = &spi_1;
  32                 spi2 = &spi_2;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &i2c_4;
  38                 i2c5 = &i2c_5;
  39                 i2c6 = &i2c_6;
  40                 i2c7 = &i2c_7;
  41                 i2c8 = &i2c_8;
  42                 csis0 = &csis_0;
  43                 csis1 = &csis_1;
  44                 fimc0 = &fimc_0;
  45                 fimc1 = &fimc_1;
  46                 fimc2 = &fimc_2;
  47                 fimc3 = &fimc_3;
  48                 serial0 = &serial_0;
  49                 serial1 = &serial_1;
  50                 serial2 = &serial_2;
  51                 serial3 = &serial_3;
  52         };
  53
  54         clock_audss: clock-controller@03810000 {
  55                 compatible = "samsung,exynos4210-audss-clock";
  56                 reg = <0x03810000 0x0C>;
  57                 #clock-cells = <1>;
  58         };
  59
  60         i2s0: i2s@03830000 {
  61                 compatible = "samsung,s5pv210-i2s";
  62                 reg = <0x03830000 0x100>;
  63                 clocks = <&clock_audss EXYNOS_I2S_BUS>;
  64                 clock-names = "iis";
  65                 #clock-cells = <1>;
  66                 clock-output-names = "i2s_cdclk0";
  67                 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
  68                 dma-names = "tx", "rx", "tx-sec";
  69                 samsung,idma-addr = <0x03000000>;
  70                 #sound-dai-cells = <1>;
  71                 status = "disabled";
  72         };
  73
  74         chipid@10000000 {
  75                 compatible = "samsung,exynos4210-chipid";
  76                 reg = <0x10000000 0x100>;
  77         };
  78
  79         sromc@12570000 {
  80                 compatible = "samsung,exynos-srom";
  81                 reg = <0x12570000 0x14>;
  82         };
  83
  84         mipi_phy: video-phy@10020710 {
  85                 compatible = "samsung,s5pv210-mipi-video-phy";
  86                 #phy-cells = <1>;
  87                 syscon = <&pmu_system_controller>;
  88         };
  89
  90         pd_mfc: mfc-power-domain@10023C40 {
  91                 compatible = "samsung,exynos4210-pd";
  92                 reg = <0x10023C40 0x20>;
  93                 #power-domain-cells = <0>;
  94         };
  95
  96         pd_g3d: g3d-power-domain@10023C60 {
  97                 compatible = "samsung,exynos4210-pd";
  98                 reg = <0x10023C60 0x20>;
  99                 #power-domain-cells = <0>;
 100         };
 101
 102         pd_lcd0: lcd0-power-domain@10023C80 {
 103                 compatible = "samsung,exynos4210-pd";
 104                 reg = <0x10023C80 0x20>;
 105                 #power-domain-cells = <0>;
 106         };
 107
 108         pd_tv: tv-power-domain@10023C20 {
 109                 compatible = "samsung,exynos4210-pd";
 110                 reg = <0x10023C20 0x20>;
 111                 #power-domain-cells = <0>;
 112                 power-domains = <&pd_lcd0>;
 113         };
 114
 115         pd_cam: cam-power-domain@10023C00 {
 116                 compatible = "samsung,exynos4210-pd";
 117                 reg = <0x10023C00 0x20>;
 118                 #power-domain-cells = <0>;
 119         };
 120
 121         pd_gps: gps-power-domain@10023CE0 {
 122                 compatible = "samsung,exynos4210-pd";
 123                 reg = <0x10023CE0 0x20>;
 124                 #power-domain-cells = <0>;
 125         };
 126
 127         pd_gps_alive: gps-alive-power-domain@10023D00 {
 128                 compatible = "samsung,exynos4210-pd";
 129                 reg = <0x10023D00 0x20>;
 130                 #power-domain-cells = <0>;
 131         };
 132
 133         gic: interrupt-controller@10490000 {
 134                 compatible = "arm,cortex-a9-gic";
 135                 #interrupt-cells = <3>;
 136                 interrupt-controller;
 137                 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
 138         };
 139
 140         combiner: interrupt-controller@10440000 {
 141                 compatible = "samsung,exynos4210-combiner";
 142                 #interrupt-cells = <2>;
 143                 interrupt-controller;
 144                 reg = <0x10440000 0x1000>;
 145         };
 146
 147         pmu {
 148                 compatible = "arm,cortex-a9-pmu";
 149                 interrupt-parent = <&combiner>;
 150                 interrupts = <2 2>, <3 2>;
 151         };
 152
 153         sys_reg: syscon@10010000 {
 154                 compatible = "samsung,exynos4-sysreg", "syscon";
 155                 reg = <0x10010000 0x400>;
 156         };
 157
 158         pmu_system_controller: system-controller@10020000 {
 159                 compatible = "samsung,exynos4210-pmu", "syscon";
 160                 reg = <0x10020000 0x4000>;
 161                 interrupt-controller;
 162                 #interrupt-cells = <3>;
 163                 interrupt-parent = <&gic>;
 164         };
 165
 166         poweroff: syscon-poweroff {
 167                 compatible = "syscon-poweroff";
 168                 regmap = <&pmu_system_controller>;
 169                 offset = <0x330C>; /* PS_HOLD_CONTROL */
 170                 mask = <0x5200>; /* reset value */
 171         };
 172
 173         reboot: syscon-reboot {
 174                 compatible = "syscon-reboot";
 175                 regmap = <&pmu_system_controller>;
 176                 offset = <0x0400>; /* SWRESET */
 177                 mask = <0x1>;
 178         };
 179
 180         dsi_0: dsi@11C80000 {
 181                 compatible = "samsung,exynos4210-mipi-dsi";
 182                 reg = <0x11C80000 0x10000>;
 183                 interrupts = <0 79 0>;
 184                 power-domains = <&pd_lcd0>;
 185                 phys = <&mipi_phy 1>;
 186                 phy-names = "dsim";
 187                 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
 188                 clock-names = "bus_clk", "sclk_mipi";
 189                 status = "disabled";
 190                 #address-cells = <1>;
 191                 #size-cells = <0>;
 192         };
 193
 194         camera {
 195                 compatible = "samsung,fimc", "simple-bus";
 196                 status = "disabled";
 197                 #address-cells = <1>;
 198                 #size-cells = <1>;
 199                 #clock-cells = <1>;
 200                 clock-output-names = "cam_a_clkout", "cam_b_clkout";
 201                 ranges;
 202
 203                 fimc_0: fimc@11800000 {
 204                         compatible = "samsung,exynos4210-fimc";
 205                         reg = <0x11800000 0x1000>;
 206                         interrupts = <0 84 0>;
 207                         clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
 208                         clock-names = "fimc", "sclk_fimc";
 209                         power-domains = <&pd_cam>;
 210                         samsung,sysreg = <&sys_reg>;
 211                         iommus = <&sysmmu_fimc0>;
 212                         status = "disabled";
 213                 };
 214
 215                 fimc_1: fimc@11810000 {
 216                         compatible = "samsung,exynos4210-fimc";
 217                         reg = <0x11810000 0x1000>;
 218                         interrupts = <0 85 0>;
 219                         clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
 220                         clock-names = "fimc", "sclk_fimc";
 221                         power-domains = <&pd_cam>;
 222                         samsung,sysreg = <&sys_reg>;
 223                         iommus = <&sysmmu_fimc1>;
 224                         status = "disabled";
 225                 };
 226
 227                 fimc_2: fimc@11820000 {
 228                         compatible = "samsung,exynos4210-fimc";
 229                         reg = <0x11820000 0x1000>;
 230                         interrupts = <0 86 0>;
 231                         clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
 232                         clock-names = "fimc", "sclk_fimc";
 233                         power-domains = <&pd_cam>;
 234                         samsung,sysreg = <&sys_reg>;
 235                         iommus = <&sysmmu_fimc2>;
 236                         status = "disabled";
 237                 };
 238
 239                 fimc_3: fimc@11830000 {
 240                         compatible = "samsung,exynos4210-fimc";
 241                         reg = <0x11830000 0x1000>;
 242                         interrupts = <0 87 0>;
 243                         clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
 244                         clock-names = "fimc", "sclk_fimc";
 245                         power-domains = <&pd_cam>;
 246                         samsung,sysreg = <&sys_reg>;
 247                         iommus = <&sysmmu_fimc3>;
 248                         status = "disabled";
 249                 };
 250
 251                 csis_0: csis@11880000 {
 252                         compatible = "samsung,exynos4210-csis";
 253                         reg = <0x11880000 0x4000>;
 254                         interrupts = <0 78 0>;
 255                         clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
 256                         clock-names = "csis", "sclk_csis";
 257                         bus-width = <4>;
 258                         power-domains = <&pd_cam>;
 259                         phys = <&mipi_phy 0>;
 260                         phy-names = "csis";
 261                         status = "disabled";
 262                         #address-cells = <1>;
 263                         #size-cells = <0>;
 264                 };
 265
 266                 csis_1: csis@11890000 {
 267                         compatible = "samsung,exynos4210-csis";
 268                         reg = <0x11890000 0x4000>;
 269                         interrupts = <0 80 0>;
 270                         clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
 271                         clock-names = "csis", "sclk_csis";
 272                         bus-width = <2>;
 273                         power-domains = <&pd_cam>;
 274                         phys = <&mipi_phy 2>;
 275                         phy-names = "csis";
 276                         status = "disabled";
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279                 };
 280         };
 281
 282         watchdog: watchdog@10060000 {
 283                 compatible = "samsung,s3c2410-wdt";
 284                 reg = <0x10060000 0x100>;
 285                 interrupts = <0 43 0>;
 286                 clocks = <&clock CLK_WDT>;
 287                 clock-names = "watchdog";
 288                 status = "disabled";
 289         };
 290
 291         rtc: rtc@10070000 {
 292                 compatible = "samsung,s3c6410-rtc";
 293                 reg = <0x10070000 0x100>;
 294                 interrupt-parent = <&pmu_system_controller>;
 295                 interrupts = <0 44 0>, <0 45 0>;
 296                 clocks = <&clock CLK_RTC>;
 297                 clock-names = "rtc";
 298                 status = "disabled";
 299         };
 300
 301         keypad: keypad@100A0000 {
 302                 compatible = "samsung,s5pv210-keypad";
 303                 reg = <0x100A0000 0x100>;
 304                 interrupts = <0 109 0>;
 305                 clocks = <&clock CLK_KEYIF>;
 306                 clock-names = "keypad";
 307                 status = "disabled";
 308         };
 309
 310         sdhci_0: sdhci@12510000 {
 311                 compatible = "samsung,exynos4210-sdhci";
 312                 reg = <0x12510000 0x100>;
 313                 interrupts = <0 73 0>;
 314                 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 315                 clock-names = "hsmmc", "mmc_busclk.2";
 316                 status = "disabled";
 317         };
 318
 319         sdhci_1: sdhci@12520000 {
 320                 compatible = "samsung,exynos4210-sdhci";
 321                 reg = <0x12520000 0x100>;
 322                 interrupts = <0 74 0>;
 323                 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 324                 clock-names = "hsmmc", "mmc_busclk.2";
 325                 status = "disabled";
 326         };
 327
 328         sdhci_2: sdhci@12530000 {
 329                 compatible = "samsung,exynos4210-sdhci";
 330                 reg = <0x12530000 0x100>;
 331                 interrupts = <0 75 0>;
 332                 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 333                 clock-names = "hsmmc", "mmc_busclk.2";
 334                 status = "disabled";
 335         };
 336
 337         sdhci_3: sdhci@12540000 {
 338                 compatible = "samsung,exynos4210-sdhci";
 339                 reg = <0x12540000 0x100>;
 340                 interrupts = <0 76 0>;
 341                 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 342                 clock-names = "hsmmc", "mmc_busclk.2";
 343                 status = "disabled";
 344         };
 345
 346         exynos_usbphy: exynos-usbphy@125B0000 {
 347                 compatible = "samsung,exynos4210-usb2-phy";
 348                 reg = <0x125B0000 0x100>;
 349                 samsung,pmureg-phandle = <&pmu_system_controller>;
 350                 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
 351                 clock-names = "phy", "ref";
 352                 #phy-cells = <1>;
 353                 status = "disabled";
 354         };
 355
 356         hsotg: hsotg@12480000 {
 357                 compatible = "samsung,s3c6400-hsotg";
 358                 reg = <0x12480000 0x20000>;
 359                 interrupts = <0 71 0>;
 360                 clocks = <&clock CLK_USB_DEVICE>;
 361                 clock-names = "otg";
 362                 phys = <&exynos_usbphy 0>;
 363                 phy-names = "usb2-phy";
 364                 status = "disabled";
 365         };
 366
 367         ehci: ehci@12580000 {
 368                 compatible = "samsung,exynos4210-ehci";
 369                 reg = <0x12580000 0x100>;
 370                 interrupts = <0 70 0>;
 371                 clocks = <&clock CLK_USB_HOST>;
 372                 clock-names = "usbhost";
 373                 status = "disabled";
 374                 #address-cells = <1>;
 375                 #size-cells = <0>;
 376                 port@0 {
 377                     reg = <0>;
 378                     phys = <&exynos_usbphy 1>;
 379                     status = "disabled";
 380                 };
 381                 port@1 {
 382                     reg = <1>;
 383                     phys = <&exynos_usbphy 2>;
 384                     status = "disabled";
 385                 };
 386                 port@2 {
 387                     reg = <2>;
 388                     phys = <&exynos_usbphy 3>;
 389                     status = "disabled";
 390                 };
 391         };
 392
 393         ohci: ohci@12590000 {
 394                 compatible = "samsung,exynos4210-ohci";
 395                 reg = <0x12590000 0x100>;
 396                 interrupts = <0 70 0>;
 397                 clocks = <&clock CLK_USB_HOST>;
 398                 clock-names = "usbhost";
 399                 status = "disabled";
 400                 #address-cells = <1>;
 401                 #size-cells = <0>;
 402                 port@0 {
 403                     reg = <0>;
 404                     phys = <&exynos_usbphy 1>;
 405                     status = "disabled";
 406                 };
 407         };
 408
 409         i2s1: i2s@13960000 {
 410                 compatible = "samsung,s3c6410-i2s";
 411                 reg = <0x13960000 0x100>;
 412                 clocks = <&clock CLK_I2S1>;
 413                 clock-names = "iis";
 414                 #clock-cells = <1>;
 415                 clock-output-names = "i2s_cdclk1";
 416                 dmas = <&pdma1 12>, <&pdma1 11>;
 417                 dma-names = "tx", "rx";
 418                 #sound-dai-cells = <1>;
 419                 status = "disabled";
 420         };
 421
 422         i2s2: i2s@13970000 {
 423                 compatible = "samsung,s3c6410-i2s";
 424                 reg = <0x13970000 0x100>;
 425                 clocks = <&clock CLK_I2S2>;
 426                 clock-names = "iis";
 427                 #clock-cells = <1>;
 428                 clock-output-names = "i2s_cdclk2";
 429                 dmas = <&pdma0 14>, <&pdma0 13>;
 430                 dma-names = "tx", "rx";
 431                 #sound-dai-cells = <1>;
 432                 status = "disabled";
 433         };
 434
 435         mfc: codec@13400000 {
 436                 compatible = "samsung,mfc-v5";
 437                 reg = <0x13400000 0x10000>;
 438                 interrupts = <0 94 0>;
 439                 power-domains = <&pd_mfc>;
 440                 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
 441                 clock-names = "mfc", "sclk_mfc";
 442                 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 443                 iommu-names = "left", "right";
 444                 status = "disabled";
 445         };
 446
 447         serial_0: serial@13800000 {
 448                 compatible = "samsung,exynos4210-uart";
 449                 reg = <0x13800000 0x100>;
 450                 interrupts = <0 52 0>;
 451                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 452                 clock-names = "uart", "clk_uart_baud0";
 453                 dmas = <&pdma0 15>, <&pdma0 16>;
 454                 dma-names = "rx", "tx";
 455                 status = "disabled";
 456         };
 457
 458         serial_1: serial@13810000 {
 459                 compatible = "samsung,exynos4210-uart";
 460                 reg = <0x13810000 0x100>;
 461                 interrupts = <0 53 0>;
 462                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 463                 clock-names = "uart", "clk_uart_baud0";
 464                 dmas = <&pdma1 15>, <&pdma1 16>;
 465                 dma-names = "rx", "tx";
 466                 status = "disabled";
 467         };
 468
 469         serial_2: serial@13820000 {
 470                 compatible = "samsung,exynos4210-uart";
 471                 reg = <0x13820000 0x100>;
 472                 interrupts = <0 54 0>;
 473                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 474                 clock-names = "uart", "clk_uart_baud0";
 475                 dmas = <&pdma0 17>, <&pdma0 18>;
 476                 dma-names = "rx", "tx";
 477                 status = "disabled";
 478         };
 479
 480         serial_3: serial@13830000 {
 481                 compatible = "samsung,exynos4210-uart";
 482                 reg = <0x13830000 0x100>;
 483                 interrupts = <0 55 0>;
 484                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 485                 clock-names = "uart", "clk_uart_baud0";
 486                 dmas = <&pdma1 17>, <&pdma1 18>;
 487                 dma-names = "rx", "tx";
 488                 status = "disabled";
 489         };
 490
 491         i2c_0: i2c@13860000 {
 492                 #address-cells = <1>;
 493                 #size-cells = <0>;
 494                 compatible = "samsung,s3c2440-i2c";
 495                 reg = <0x13860000 0x100>;
 496                 interrupts = <0 58 0>;
 497                 clocks = <&clock CLK_I2C0>;
 498                 clock-names = "i2c";
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&i2c0_bus>;
 501                 status = "disabled";
 502         };
 503
 504         i2c_1: i2c@13870000 {
 505                 #address-cells = <1>;
 506                 #size-cells = <0>;
 507                 compatible = "samsung,s3c2440-i2c";
 508                 reg = <0x13870000 0x100>;
 509                 interrupts = <0 59 0>;
 510                 clocks = <&clock CLK_I2C1>;
 511                 clock-names = "i2c";
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&i2c1_bus>;
 514                 status = "disabled";
 515         };
 516
 517         i2c_2: i2c@13880000 {
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 compatible = "samsung,s3c2440-i2c";
 521                 reg = <0x13880000 0x100>;
 522                 interrupts = <0 60 0>;
 523                 clocks = <&clock CLK_I2C2>;
 524                 clock-names = "i2c";
 525                 pinctrl-names = "default";
 526                 pinctrl-0 = <&i2c2_bus>;
 527                 status = "disabled";
 528         };
 529
 530         i2c_3: i2c@13890000 {
 531                 #address-cells = <1>;
 532                 #size-cells = <0>;
 533                 compatible = "samsung,s3c2440-i2c";
 534                 reg = <0x13890000 0x100>;
 535                 interrupts = <0 61 0>;
 536                 clocks = <&clock CLK_I2C3>;
 537                 clock-names = "i2c";
 538                 pinctrl-names = "default";
 539                 pinctrl-0 = <&i2c3_bus>;
 540                 status = "disabled";
 541         };
 542
 543         i2c_4: i2c@138A0000 {
 544                 #address-cells = <1>;
 545                 #size-cells = <0>;
 546                 compatible = "samsung,s3c2440-i2c";
 547                 reg = <0x138A0000 0x100>;
 548                 interrupts = <0 62 0>;
 549                 clocks = <&clock CLK_I2C4>;
 550                 clock-names = "i2c";
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&i2c4_bus>;
 553                 status = "disabled";
 554         };
 555
 556         i2c_5: i2c@138B0000 {
 557                 #address-cells = <1>;
 558                 #size-cells = <0>;
 559                 compatible = "samsung,s3c2440-i2c";
 560                 reg = <0x138B0000 0x100>;
 561                 interrupts = <0 63 0>;
 562                 clocks = <&clock CLK_I2C5>;
 563                 clock-names = "i2c";
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&i2c5_bus>;
 566                 status = "disabled";
 567         };
 568
 569         i2c_6: i2c@138C0000 {
 570                 #address-cells = <1>;
 571                 #size-cells = <0>;
 572                 compatible = "samsung,s3c2440-i2c";
 573                 reg = <0x138C0000 0x100>;
 574                 interrupts = <0 64 0>;
 575                 clocks = <&clock CLK_I2C6>;
 576                 clock-names = "i2c";
 577                 pinctrl-names = "default";
 578                 pinctrl-0 = <&i2c6_bus>;
 579                 status = "disabled";
 580         };
 581
 582         i2c_7: i2c@138D0000 {
 583                 #address-cells = <1>;
 584                 #size-cells = <0>;
 585                 compatible = "samsung,s3c2440-i2c";
 586                 reg = <0x138D0000 0x100>;
 587                 interrupts = <0 65 0>;
 588                 clocks = <&clock CLK_I2C7>;
 589                 clock-names = "i2c";
 590                 pinctrl-names = "default";
 591                 pinctrl-0 = <&i2c7_bus>;
 592                 status = "disabled";
 593         };
 594
 595         i2c_8: i2c@138E0000 {
 596                 #address-cells = <1>;
 597                 #size-cells = <0>;
 598                 compatible = "samsung,s3c2440-hdmiphy-i2c";
 599                 reg = <0x138E0000 0x100>;
 600                 interrupts = <0 93 0>;
 601                 clocks = <&clock CLK_I2C_HDMI>;
 602                 clock-names = "i2c";
 603                 status = "disabled";
 604
 605                 hdmi_i2c_phy: hdmiphy@38 {
 606                         compatible = "exynos4210-hdmiphy";
 607                         reg = <0x38>;
 608                 };
 609         };
 610
 611         spi_0: spi@13920000 {
 612                 compatible = "samsung,exynos4210-spi";
 613                 reg = <0x13920000 0x100>;
 614                 interrupts = <0 66 0>;
 615                 dmas = <&pdma0 7>, <&pdma0 6>;
 616                 dma-names = "tx", "rx";
 617                 #address-cells = <1>;
 618                 #size-cells = <0>;
 619                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 620                 clock-names = "spi", "spi_busclk0";
 621                 pinctrl-names = "default";
 622                 pinctrl-0 = <&spi0_bus>;
 623                 status = "disabled";
 624         };
 625
 626         spi_1: spi@13930000 {
 627                 compatible = "samsung,exynos4210-spi";
 628                 reg = <0x13930000 0x100>;
 629                 interrupts = <0 67 0>;
 630                 dmas = <&pdma1 7>, <&pdma1 6>;
 631                 dma-names = "tx", "rx";
 632                 #address-cells = <1>;
 633                 #size-cells = <0>;
 634                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 635                 clock-names = "spi", "spi_busclk0";
 636                 pinctrl-names = "default";
 637                 pinctrl-0 = <&spi1_bus>;
 638                 status = "disabled";
 639         };
 640
 641         spi_2: spi@13940000 {
 642                 compatible = "samsung,exynos4210-spi";
 643                 reg = <0x13940000 0x100>;
 644                 interrupts = <0 68 0>;
 645                 dmas = <&pdma0 9>, <&pdma0 8>;
 646                 dma-names = "tx", "rx";
 647                 #address-cells = <1>;
 648                 #size-cells = <0>;
 649                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 650                 clock-names = "spi", "spi_busclk0";
 651                 pinctrl-names = "default";
 652                 pinctrl-0 = <&spi2_bus>;
 653                 status = "disabled";
 654         };
 655
 656         pwm: pwm@139D0000 {
 657                 compatible = "samsung,exynos4210-pwm";
 658                 reg = <0x139D0000 0x1000>;
 659                 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
 660                 clocks = <&clock CLK_PWM>;
 661                 clock-names = "timers";
 662                 #pwm-cells = <3>;
 663                 status = "disabled";
 664         };
 665
 666         amba {
 667                 #address-cells = <1>;
 668                 #size-cells = <1>;
 669                 compatible = "arm,amba-bus";
 670                 interrupt-parent = <&gic>;
 671                 ranges;
 672
 673                 pdma0: pdma@12680000 {
 674                         compatible = "arm,pl330", "arm,primecell";
 675                         reg = <0x12680000 0x1000>;
 676                         interrupts = <0 35 0>;
 677                         clocks = <&clock CLK_PDMA0>;
 678                         clock-names = "apb_pclk";
 679                         #dma-cells = <1>;
 680                         #dma-channels = <8>;
 681                         #dma-requests = <32>;
 682                 };
 683
 684                 pdma1: pdma@12690000 {
 685                         compatible = "arm,pl330", "arm,primecell";
 686                         reg = <0x12690000 0x1000>;
 687                         interrupts = <0 36 0>;
 688                         clocks = <&clock CLK_PDMA1>;
 689                         clock-names = "apb_pclk";
 690                         #dma-cells = <1>;
 691                         #dma-channels = <8>;
 692                         #dma-requests = <32>;
 693                 };
 694
 695                 mdma1: mdma@12850000 {
 696                         compatible = "arm,pl330", "arm,primecell";
 697                         reg = <0x12850000 0x1000>;
 698                         interrupts = <0 34 0>;
 699                         clocks = <&clock CLK_MDMA>;
 700                         clock-names = "apb_pclk";
 701                         #dma-cells = <1>;
 702                         #dma-channels = <8>;
 703                         #dma-requests = <1>;
 704                 };
 705         };
 706
 707         fimd: fimd@11c00000 {
 708                 compatible = "samsung,exynos4210-fimd";
 709                 interrupt-parent = <&combiner>;
 710                 reg = <0x11c00000 0x20000>;
 711                 interrupt-names = "fifo", "vsync", "lcd_sys";
 712                 interrupts = <11 0>, <11 1>, <11 2>;
 713                 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
 714                 clock-names = "sclk_fimd", "fimd";
 715                 power-domains = <&pd_lcd0>;
 716                 iommus = <&sysmmu_fimd0>;
 717                 samsung,sysreg = <&sys_reg>;
 718                 status = "disabled";
 719         };
 720
 721         tmu: tmu@100C0000 {
 722                 #include "exynos4412-tmu-sensor-conf.dtsi"
 723         };
 724
 725         jpeg_codec: jpeg-codec@11840000 {
 726                 compatible = "samsung,exynos4210-jpeg";
 727                 reg = <0x11840000 0x1000>;
 728                 interrupts = <0 88 0>;
 729                 clocks = <&clock CLK_JPEG>;
 730                 clock-names = "jpeg";
 731                 power-domains = <&pd_cam>;
 732                 iommus = <&sysmmu_jpeg>;
 733         };
 734
 735         rotator: rotator@12810000 {
 736                 compatible = "samsung,exynos4210-rotator";
 737                 reg = <0x12810000 0x64>;
 738                 interrupts = <0 83 0>;
 739                 clocks = <&clock CLK_ROTATOR>;
 740                 clock-names = "rotator";
 741                 iommus = <&sysmmu_rotator>;
 742         };
 743
 744         hdmi: hdmi@12D00000 {
 745                 compatible = "samsung,exynos4210-hdmi";
 746                 reg = <0x12D00000 0x70000>;
 747                 interrupts = <0 92 0>;
 748                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
 749                         "mout_hdmi";
 750                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 751                         <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 752                         <&clock CLK_MOUT_HDMI>;
 753                 phy = <&hdmi_i2c_phy>;
 754                 power-domains = <&pd_tv>;
 755                 samsung,syscon-phandle = <&pmu_system_controller>;
 756                 status = "disabled";
 757         };
 758
 759         mixer: mixer@12C10000 {
 760                 compatible = "samsung,exynos4210-mixer";
 761                 interrupts = <0 91 0>;
 762                 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
 763                 power-domains = <&pd_tv>;
 764                 iommus = <&sysmmu_tv>;
 765                 status = "disabled";
 766         };
 767
 768         ppmu_dmc0: ppmu_dmc0@106a0000 {
 769                 compatible = "samsung,exynos-ppmu";
 770                 reg = <0x106a0000 0x2000>;
 771                 clocks = <&clock CLK_PPMUDMC0>;
 772                 clock-names = "ppmu";
 773                 status = "disabled";
 774         };
 775
 776         ppmu_dmc1: ppmu_dmc1@106b0000 {
 777                 compatible = "samsung,exynos-ppmu";
 778                 reg = <0x106b0000 0x2000>;
 779                 clocks = <&clock CLK_PPMUDMC1>;
 780                 clock-names = "ppmu";
 781                 status = "disabled";
 782         };
 783
 784         ppmu_cpu: ppmu_cpu@106c0000 {
 785                 compatible = "samsung,exynos-ppmu";
 786                 reg = <0x106c0000 0x2000>;
 787                 clocks = <&clock CLK_PPMUCPU>;
 788                 clock-names = "ppmu";
 789                 status = "disabled";
 790         };
 791
 792         ppmu_acp: ppmu_acp@10ae0000 {
 793                 compatible = "samsung,exynos-ppmu";
 794                 reg = <0x106e0000 0x2000>;
 795                 status = "disabled";
 796         };
 797
 798         ppmu_rightbus: ppmu_rightbus@112a0000 {
 799                 compatible = "samsung,exynos-ppmu";
 800                 reg = <0x112a0000 0x2000>;
 801                 clocks = <&clock CLK_PPMURIGHT>;
 802                 clock-names = "ppmu";
 803                 status = "disabled";
 804         };
 805
 806         ppmu_leftbus: ppmu_leftbus0@116a0000 {
 807                 compatible = "samsung,exynos-ppmu";
 808                 reg = <0x116a0000 0x2000>;
 809                 clocks = <&clock CLK_PPMULEFT>;
 810                 clock-names = "ppmu";
 811                 status = "disabled";
 812         };
 813
 814         ppmu_camif: ppmu_camif@11ac0000 {
 815                 compatible = "samsung,exynos-ppmu";
 816                 reg = <0x11ac0000 0x2000>;
 817                 clocks = <&clock CLK_PPMUCAMIF>;
 818                 clock-names = "ppmu";
 819                 status = "disabled";
 820         };
 821
 822         ppmu_lcd0: ppmu_lcd0@11e40000 {
 823                 compatible = "samsung,exynos-ppmu";
 824                 reg = <0x11e40000 0x2000>;
 825                 clocks = <&clock CLK_PPMULCD0>;
 826                 clock-names = "ppmu";
 827                 status = "disabled";
 828         };
 829
 830         ppmu_fsys: ppmu_g3d@12630000 {
 831                 compatible = "samsung,exynos-ppmu";
 832                 reg = <0x12630000 0x2000>;
 833                 status = "disabled";
 834         };
 835
 836         ppmu_image: ppmu_image@12aa0000 {
 837                 compatible = "samsung,exynos-ppmu";
 838                 reg = <0x12aa0000 0x2000>;
 839                 clocks = <&clock CLK_PPMUIMAGE>;
 840                 clock-names = "ppmu";
 841                 status = "disabled";
 842         };
 843
 844         ppmu_tv: ppmu_tv@12e40000 {
 845                 compatible = "samsung,exynos-ppmu";
 846                 reg = <0x12e40000 0x2000>;
 847                 clocks = <&clock CLK_PPMUTV>;
 848                 clock-names = "ppmu";
 849                 status = "disabled";
 850         };
 851
 852         ppmu_g3d: ppmu_g3d@13220000 {
 853                 compatible = "samsung,exynos-ppmu";
 854                 reg = <0x13220000 0x2000>;
 855                 clocks = <&clock CLK_PPMUG3D>;
 856                 clock-names = "ppmu";
 857                 status = "disabled";
 858         };
 859
 860         ppmu_mfc_left: ppmu_mfc_left@13660000 {
 861                 compatible = "samsung,exynos-ppmu";
 862                 reg = <0x13660000 0x2000>;
 863                 clocks = <&clock CLK_PPMUMFC_L>;
 864                 clock-names = "ppmu";
 865                 status = "disabled";
 866         };
 867
 868         ppmu_mfc_right: ppmu_mfc_right@13670000 {
 869                 compatible = "samsung,exynos-ppmu";
 870                 reg = <0x13670000 0x2000>;
 871                 clocks = <&clock CLK_PPMUMFC_R>;
 872                 clock-names = "ppmu";
 873                 status = "disabled";
 874         };
 875
 876         sysmmu_mfc_l: sysmmu@13620000 {
 877                 compatible = "samsung,exynos-sysmmu";
 878                 reg = <0x13620000 0x1000>;
 879                 interrupt-parent = <&combiner>;
 880                 interrupts = <5 5>;
 881                 clock-names = "sysmmu", "master";
 882                 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 883                 power-domains = <&pd_mfc>;
 884                 #iommu-cells = <0>;
 885         };
 886
 887         sysmmu_mfc_r: sysmmu@13630000 {
 888                 compatible = "samsung,exynos-sysmmu";
 889                 reg = <0x13630000 0x1000>;
 890                 interrupt-parent = <&combiner>;
 891                 interrupts = <5 6>;
 892                 clock-names = "sysmmu", "master";
 893                 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 894                 power-domains = <&pd_mfc>;
 895                 #iommu-cells = <0>;
 896         };
 897
 898         sysmmu_tv: sysmmu@12E20000 {
 899                 compatible = "samsung,exynos-sysmmu";
 900                 reg = <0x12E20000 0x1000>;
 901                 interrupt-parent = <&combiner>;
 902                 interrupts = <5 4>;
 903                 clock-names = "sysmmu", "master";
 904                 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
 905                 power-domains = <&pd_tv>;
 906                 #iommu-cells = <0>;
 907         };
 908
 909         sysmmu_fimc0: sysmmu@11A20000 {
 910                 compatible = "samsung,exynos-sysmmu";
 911                 reg = <0x11A20000 0x1000>;
 912                 interrupt-parent = <&combiner>;
 913                 interrupts = <4 2>;
 914                 clock-names = "sysmmu", "master";
 915                 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
 916                 power-domains = <&pd_cam>;
 917                 #iommu-cells = <0>;
 918         };
 919
 920         sysmmu_fimc1: sysmmu@11A30000 {
 921                 compatible = "samsung,exynos-sysmmu";
 922                 reg = <0x11A30000 0x1000>;
 923                 interrupt-parent = <&combiner>;
 924                 interrupts = <4 3>;
 925                 clock-names = "sysmmu", "master";
 926                 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
 927                 power-domains = <&pd_cam>;
 928                 #iommu-cells = <0>;
 929         };
 930
 931         sysmmu_fimc2: sysmmu@11A40000 {
 932                 compatible = "samsung,exynos-sysmmu";
 933                 reg = <0x11A40000 0x1000>;
 934                 interrupt-parent = <&combiner>;
 935                 interrupts = <4 4>;
 936                 clock-names = "sysmmu", "master";
 937                 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
 938                 power-domains = <&pd_cam>;
 939                 #iommu-cells = <0>;
 940         };
 941
 942         sysmmu_fimc3: sysmmu@11A50000 {
 943                 compatible = "samsung,exynos-sysmmu";
 944                 reg = <0x11A50000 0x1000>;
 945                 interrupt-parent = <&combiner>;
 946                 interrupts = <4 5>;
 947                 clock-names = "sysmmu", "master";
 948                 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
 949                 power-domains = <&pd_cam>;
 950                 #iommu-cells = <0>;
 951         };
 952
 953         sysmmu_jpeg: sysmmu@11A60000 {
 954                 compatible = "samsung,exynos-sysmmu";
 955                 reg = <0x11A60000 0x1000>;
 956                 interrupt-parent = <&combiner>;
 957                 interrupts = <4 6>;
 958                 clock-names = "sysmmu", "master";
 959                 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 960                 power-domains = <&pd_cam>;
 961                 #iommu-cells = <0>;
 962         };
 963
 964         sysmmu_rotator: sysmmu@12A30000 {
 965                 compatible = "samsung,exynos-sysmmu";
 966                 reg = <0x12A30000 0x1000>;
 967                 interrupt-parent = <&combiner>;
 968                 interrupts = <5 0>;
 969                 clock-names = "sysmmu", "master";
 970                 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 971                 #iommu-cells = <0>;
 972         };
 973
 974         sysmmu_fimd0: sysmmu@11E20000 {
 975                 compatible = "samsung,exynos-sysmmu";
 976                 reg = <0x11E20000 0x1000>;
 977                 interrupt-parent = <&combiner>;
 978                 interrupts = <5 2>;
 979                 clock-names = "sysmmu", "master";
 980                 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
 981                 power-domains = <&pd_lcd0>;
 982                 #iommu-cells = <0>;
 983         };
 984
 985         prng: rng@10830400 {
 986                 compatible = "samsung,exynos4-rng";
 987                 reg = <0x10830400 0x200>;
 988                 clocks = <&clock CLK_SSS>;
 989                 clock-names = "secss";
 990                 status = "disabled";
 991         };
 992 };