2 * Samsung's Exynos4 SoC series common device tree source
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
9 * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
10 * SoCs from Exynos4 series can include this file and provide values for SoCs
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
15 * nodes can be added to this file.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #include <dt-bindings/clock/exynos4.h>
23 #include <dt-bindings/clock/exynos-audss-clk.h>
24 #include "skeleton.dtsi"
27 interrupt-parent = <&gic>;
53 clock_audss: clock-controller@03810000 {
54 compatible = "samsung,exynos4210-audss-clock";
55 reg = <0x03810000 0x0C>;
60 compatible = "samsung,s5pv210-i2s";
61 reg = <0x03830000 0x100>;
62 clocks = <&clock_audss EXYNOS_I2S_BUS>;
64 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
65 dma-names = "tx", "rx", "tx-sec";
66 samsung,idma-addr = <0x03000000>;
71 compatible = "samsung,exynos4210-chipid";
72 reg = <0x10000000 0x100>;
75 mipi_phy: video-phy@10020710 {
76 compatible = "samsung,s5pv210-mipi-video-phy";
81 pd_mfc: mfc-power-domain@10023C40 {
82 compatible = "samsung,exynos4210-pd";
83 reg = <0x10023C40 0x20>;
86 pd_g3d: g3d-power-domain@10023C60 {
87 compatible = "samsung,exynos4210-pd";
88 reg = <0x10023C60 0x20>;
91 pd_lcd0: lcd0-power-domain@10023C80 {
92 compatible = "samsung,exynos4210-pd";
93 reg = <0x10023C80 0x20>;
96 pd_tv: tv-power-domain@10023C20 {
97 compatible = "samsung,exynos4210-pd";
98 reg = <0x10023C20 0x20>;
101 pd_cam: cam-power-domain@10023C00 {
102 compatible = "samsung,exynos4210-pd";
103 reg = <0x10023C00 0x20>;
106 pd_gps: gps-power-domain@10023CE0 {
107 compatible = "samsung,exynos4210-pd";
108 reg = <0x10023CE0 0x20>;
111 pd_gps_alive: gps-alive-power-domain@10023D00 {
112 compatible = "samsung,exynos4210-pd";
113 reg = <0x10023D00 0x20>;
116 gic: interrupt-controller@10490000 {
117 compatible = "arm,cortex-a9-gic";
118 #interrupt-cells = <3>;
119 interrupt-controller;
120 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
123 combiner: interrupt-controller@10440000 {
124 compatible = "samsung,exynos4210-combiner";
125 #interrupt-cells = <2>;
126 interrupt-controller;
127 reg = <0x10440000 0x1000>;
131 compatible = "arm,cortex-a9-pmu";
132 interrupt-parent = <&combiner>;
133 interrupts = <2 2>, <3 2>;
136 sys_reg: syscon@10010000 {
137 compatible = "samsung,exynos4-sysreg", "syscon";
138 reg = <0x10010000 0x400>;
141 pmu_system_controller: system-controller@10020000 {
142 compatible = "samsung,exynos4210-pmu", "syscon";
143 reg = <0x10020000 0x4000>;
146 dsi_0: dsi@11C80000 {
147 compatible = "samsung,exynos4210-mipi-dsi";
148 reg = <0x11C80000 0x10000>;
149 interrupts = <0 79 0>;
150 samsung,power-domain = <&pd_lcd0>;
151 phys = <&mipi_phy 1>;
153 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
154 clock-names = "bus_clk", "pll_clk";
156 #address-cells = <1>;
161 compatible = "samsung,fimc", "simple-bus";
163 #address-cells = <1>;
166 clock-output-names = "cam_a_clkout", "cam_b_clkout";
169 fimc_0: fimc@11800000 {
170 compatible = "samsung,exynos4210-fimc";
171 reg = <0x11800000 0x1000>;
172 interrupts = <0 84 0>;
173 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
174 clock-names = "fimc", "sclk_fimc";
175 samsung,power-domain = <&pd_cam>;
176 samsung,sysreg = <&sys_reg>;
180 fimc_1: fimc@11810000 {
181 compatible = "samsung,exynos4210-fimc";
182 reg = <0x11810000 0x1000>;
183 interrupts = <0 85 0>;
184 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
185 clock-names = "fimc", "sclk_fimc";
186 samsung,power-domain = <&pd_cam>;
187 samsung,sysreg = <&sys_reg>;
191 fimc_2: fimc@11820000 {
192 compatible = "samsung,exynos4210-fimc";
193 reg = <0x11820000 0x1000>;
194 interrupts = <0 86 0>;
195 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
196 clock-names = "fimc", "sclk_fimc";
197 samsung,power-domain = <&pd_cam>;
198 samsung,sysreg = <&sys_reg>;
202 fimc_3: fimc@11830000 {
203 compatible = "samsung,exynos4210-fimc";
204 reg = <0x11830000 0x1000>;
205 interrupts = <0 87 0>;
206 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
207 clock-names = "fimc", "sclk_fimc";
208 samsung,power-domain = <&pd_cam>;
209 samsung,sysreg = <&sys_reg>;
213 csis_0: csis@11880000 {
214 compatible = "samsung,exynos4210-csis";
215 reg = <0x11880000 0x4000>;
216 interrupts = <0 78 0>;
217 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
218 clock-names = "csis", "sclk_csis";
220 samsung,power-domain = <&pd_cam>;
221 phys = <&mipi_phy 0>;
224 #address-cells = <1>;
228 csis_1: csis@11890000 {
229 compatible = "samsung,exynos4210-csis";
230 reg = <0x11890000 0x4000>;
231 interrupts = <0 80 0>;
232 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
233 clock-names = "csis", "sclk_csis";
235 samsung,power-domain = <&pd_cam>;
236 phys = <&mipi_phy 2>;
239 #address-cells = <1>;
245 compatible = "samsung,s3c2410-wdt";
246 reg = <0x10060000 0x100>;
247 interrupts = <0 43 0>;
248 clocks = <&clock CLK_WDT>;
249 clock-names = "watchdog";
254 compatible = "samsung,s3c6410-rtc";
255 reg = <0x10070000 0x100>;
256 interrupts = <0 44 0>, <0 45 0>;
257 clocks = <&clock CLK_RTC>;
263 compatible = "samsung,s5pv210-keypad";
264 reg = <0x100A0000 0x100>;
265 interrupts = <0 109 0>;
266 clocks = <&clock CLK_KEYIF>;
267 clock-names = "keypad";
272 compatible = "samsung,exynos4210-sdhci";
273 reg = <0x12510000 0x100>;
274 interrupts = <0 73 0>;
275 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
276 clock-names = "hsmmc", "mmc_busclk.2";
281 compatible = "samsung,exynos4210-sdhci";
282 reg = <0x12520000 0x100>;
283 interrupts = <0 74 0>;
284 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
285 clock-names = "hsmmc", "mmc_busclk.2";
290 compatible = "samsung,exynos4210-sdhci";
291 reg = <0x12530000 0x100>;
292 interrupts = <0 75 0>;
293 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
294 clock-names = "hsmmc", "mmc_busclk.2";
299 compatible = "samsung,exynos4210-sdhci";
300 reg = <0x12540000 0x100>;
301 interrupts = <0 76 0>;
302 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
303 clock-names = "hsmmc", "mmc_busclk.2";
307 exynos_usbphy: exynos-usbphy@125B0000 {
308 compatible = "samsung,exynos4210-usb2-phy";
309 reg = <0x125B0000 0x100>;
310 samsung,pmureg-phandle = <&pmu_system_controller>;
311 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
312 clock-names = "phy", "ref";
318 compatible = "samsung,s3c6400-hsotg";
319 reg = <0x12480000 0x20000>;
320 interrupts = <0 71 0>;
321 clocks = <&clock CLK_USB_DEVICE>;
323 phys = <&exynos_usbphy 0>;
324 phy-names = "usb2-phy";
329 compatible = "samsung,exynos4210-ehci";
330 reg = <0x12580000 0x100>;
331 interrupts = <0 70 0>;
332 clocks = <&clock CLK_USB_HOST>;
333 clock-names = "usbhost";
335 #address-cells = <1>;
339 phys = <&exynos_usbphy 1>;
344 phys = <&exynos_usbphy 2>;
349 phys = <&exynos_usbphy 3>;
355 compatible = "samsung,exynos4210-ohci";
356 reg = <0x12590000 0x100>;
357 interrupts = <0 70 0>;
358 clocks = <&clock CLK_USB_HOST>;
359 clock-names = "usbhost";
361 #address-cells = <1>;
365 phys = <&exynos_usbphy 1>;
371 compatible = "samsung,s5pv210-i2s";
372 reg = <0x13960000 0x100>;
373 clocks = <&clock CLK_I2S1>;
375 dmas = <&pdma1 12>, <&pdma1 11>;
376 dma-names = "tx", "rx";
381 compatible = "samsung,s5pv210-i2s";
382 reg = <0x13970000 0x100>;
383 clocks = <&clock CLK_I2S2>;
385 dmas = <&pdma0 14>, <&pdma0 13>;
386 dma-names = "tx", "rx";
390 mfc: codec@13400000 {
391 compatible = "samsung,mfc-v5";
392 reg = <0x13400000 0x10000>;
393 interrupts = <0 94 0>;
394 samsung,power-domain = <&pd_mfc>;
395 clocks = <&clock CLK_MFC>;
400 serial_0: serial@13800000 {
401 compatible = "samsung,exynos4210-uart";
402 reg = <0x13800000 0x100>;
403 interrupts = <0 52 0>;
404 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
405 clock-names = "uart", "clk_uart_baud0";
409 serial_1: serial@13810000 {
410 compatible = "samsung,exynos4210-uart";
411 reg = <0x13810000 0x100>;
412 interrupts = <0 53 0>;
413 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
414 clock-names = "uart", "clk_uart_baud0";
418 serial_2: serial@13820000 {
419 compatible = "samsung,exynos4210-uart";
420 reg = <0x13820000 0x100>;
421 interrupts = <0 54 0>;
422 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
423 clock-names = "uart", "clk_uart_baud0";
427 serial_3: serial@13830000 {
428 compatible = "samsung,exynos4210-uart";
429 reg = <0x13830000 0x100>;
430 interrupts = <0 55 0>;
431 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
432 clock-names = "uart", "clk_uart_baud0";
436 i2c_0: i2c@13860000 {
437 #address-cells = <1>;
439 compatible = "samsung,s3c2440-i2c";
440 reg = <0x13860000 0x100>;
441 interrupts = <0 58 0>;
442 clocks = <&clock CLK_I2C0>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&i2c0_bus>;
449 i2c_1: i2c@13870000 {
450 #address-cells = <1>;
452 compatible = "samsung,s3c2440-i2c";
453 reg = <0x13870000 0x100>;
454 interrupts = <0 59 0>;
455 clocks = <&clock CLK_I2C1>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&i2c1_bus>;
462 i2c_2: i2c@13880000 {
463 #address-cells = <1>;
465 compatible = "samsung,s3c2440-i2c";
466 reg = <0x13880000 0x100>;
467 interrupts = <0 60 0>;
468 clocks = <&clock CLK_I2C2>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&i2c2_bus>;
475 i2c_3: i2c@13890000 {
476 #address-cells = <1>;
478 compatible = "samsung,s3c2440-i2c";
479 reg = <0x13890000 0x100>;
480 interrupts = <0 61 0>;
481 clocks = <&clock CLK_I2C3>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&i2c3_bus>;
488 i2c_4: i2c@138A0000 {
489 #address-cells = <1>;
491 compatible = "samsung,s3c2440-i2c";
492 reg = <0x138A0000 0x100>;
493 interrupts = <0 62 0>;
494 clocks = <&clock CLK_I2C4>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&i2c4_bus>;
501 i2c_5: i2c@138B0000 {
502 #address-cells = <1>;
504 compatible = "samsung,s3c2440-i2c";
505 reg = <0x138B0000 0x100>;
506 interrupts = <0 63 0>;
507 clocks = <&clock CLK_I2C5>;
509 pinctrl-names = "default";
510 pinctrl-0 = <&i2c5_bus>;
514 i2c_6: i2c@138C0000 {
515 #address-cells = <1>;
517 compatible = "samsung,s3c2440-i2c";
518 reg = <0x138C0000 0x100>;
519 interrupts = <0 64 0>;
520 clocks = <&clock CLK_I2C6>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&i2c6_bus>;
527 i2c_7: i2c@138D0000 {
528 #address-cells = <1>;
530 compatible = "samsung,s3c2440-i2c";
531 reg = <0x138D0000 0x100>;
532 interrupts = <0 65 0>;
533 clocks = <&clock CLK_I2C7>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&i2c7_bus>;
540 spi_0: spi@13920000 {
541 compatible = "samsung,exynos4210-spi";
542 reg = <0x13920000 0x100>;
543 interrupts = <0 66 0>;
544 dmas = <&pdma0 7>, <&pdma0 6>;
545 dma-names = "tx", "rx";
546 #address-cells = <1>;
548 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
549 clock-names = "spi", "spi_busclk0";
550 pinctrl-names = "default";
551 pinctrl-0 = <&spi0_bus>;
555 spi_1: spi@13930000 {
556 compatible = "samsung,exynos4210-spi";
557 reg = <0x13930000 0x100>;
558 interrupts = <0 67 0>;
559 dmas = <&pdma1 7>, <&pdma1 6>;
560 dma-names = "tx", "rx";
561 #address-cells = <1>;
563 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
564 clock-names = "spi", "spi_busclk0";
565 pinctrl-names = "default";
566 pinctrl-0 = <&spi1_bus>;
570 spi_2: spi@13940000 {
571 compatible = "samsung,exynos4210-spi";
572 reg = <0x13940000 0x100>;
573 interrupts = <0 68 0>;
574 dmas = <&pdma0 9>, <&pdma0 8>;
575 dma-names = "tx", "rx";
576 #address-cells = <1>;
578 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
579 clock-names = "spi", "spi_busclk0";
580 pinctrl-names = "default";
581 pinctrl-0 = <&spi2_bus>;
586 compatible = "samsung,exynos4210-pwm";
587 reg = <0x139D0000 0x1000>;
588 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
589 clocks = <&clock CLK_PWM>;
590 clock-names = "timers";
596 #address-cells = <1>;
598 compatible = "arm,amba-bus";
599 interrupt-parent = <&gic>;
602 pdma0: pdma@12680000 {
603 compatible = "arm,pl330", "arm,primecell";
604 reg = <0x12680000 0x1000>;
605 interrupts = <0 35 0>;
606 clocks = <&clock CLK_PDMA0>;
607 clock-names = "apb_pclk";
610 #dma-requests = <32>;
613 pdma1: pdma@12690000 {
614 compatible = "arm,pl330", "arm,primecell";
615 reg = <0x12690000 0x1000>;
616 interrupts = <0 36 0>;
617 clocks = <&clock CLK_PDMA1>;
618 clock-names = "apb_pclk";
621 #dma-requests = <32>;
624 mdma1: mdma@12850000 {
625 compatible = "arm,pl330", "arm,primecell";
626 reg = <0x12850000 0x1000>;
627 interrupts = <0 34 0>;
628 clocks = <&clock CLK_MDMA>;
629 clock-names = "apb_pclk";
636 fimd: fimd@11c00000 {
637 compatible = "samsung,exynos4210-fimd";
638 interrupt-parent = <&combiner>;
639 reg = <0x11c00000 0x20000>;
640 interrupt-names = "fifo", "vsync", "lcd_sys";
641 interrupts = <11 0>, <11 1>, <11 2>;
642 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
643 clock-names = "sclk_fimd", "fimd";
644 samsung,power-domain = <&pd_lcd0>;
645 samsung,sysreg = <&sys_reg>;