2 * Samsung's Exynos4 SoC series common device tree source
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
9 * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
10 * SoCs from Exynos4 series can include this file and provide values for SoCs
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
15 * nodes can be added to this file.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #include <dt-bindings/clock/exynos4.h>
23 #include <dt-bindings/clock/exynos-audss-clk.h>
24 #include "skeleton.dtsi"
27 interrupt-parent = <&gic>;
54 clock_audss: clock-controller@03810000 {
55 compatible = "samsung,exynos4210-audss-clock";
56 reg = <0x03810000 0x0C>;
61 compatible = "samsung,s5pv210-i2s";
62 reg = <0x03830000 0x100>;
63 clocks = <&clock_audss EXYNOS_I2S_BUS>;
66 clock-output-names = "i2s_cdclk0";
67 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
68 dma-names = "tx", "rx", "tx-sec";
69 samsung,idma-addr = <0x03000000>;
70 #sound-dai-cells = <1>;
75 compatible = "samsung,exynos4210-chipid";
76 reg = <0x10000000 0x100>;
79 mipi_phy: video-phy@10020710 {
80 compatible = "samsung,s5pv210-mipi-video-phy";
83 syscon = <&pmu_system_controller>;
86 pd_mfc: mfc-power-domain@10023C40 {
87 compatible = "samsung,exynos4210-pd";
88 reg = <0x10023C40 0x20>;
89 #power-domain-cells = <0>;
92 pd_g3d: g3d-power-domain@10023C60 {
93 compatible = "samsung,exynos4210-pd";
94 reg = <0x10023C60 0x20>;
95 #power-domain-cells = <0>;
98 pd_lcd0: lcd0-power-domain@10023C80 {
99 compatible = "samsung,exynos4210-pd";
100 reg = <0x10023C80 0x20>;
101 #power-domain-cells = <0>;
104 pd_tv: tv-power-domain@10023C20 {
105 compatible = "samsung,exynos4210-pd";
106 reg = <0x10023C20 0x20>;
107 #power-domain-cells = <0>;
108 power-domains = <&pd_lcd0>;
111 pd_cam: cam-power-domain@10023C00 {
112 compatible = "samsung,exynos4210-pd";
113 reg = <0x10023C00 0x20>;
114 #power-domain-cells = <0>;
117 pd_gps: gps-power-domain@10023CE0 {
118 compatible = "samsung,exynos4210-pd";
119 reg = <0x10023CE0 0x20>;
120 #power-domain-cells = <0>;
123 pd_gps_alive: gps-alive-power-domain@10023D00 {
124 compatible = "samsung,exynos4210-pd";
125 reg = <0x10023D00 0x20>;
126 #power-domain-cells = <0>;
129 gic: interrupt-controller@10490000 {
130 compatible = "arm,cortex-a9-gic";
131 #interrupt-cells = <3>;
132 interrupt-controller;
133 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
136 combiner: interrupt-controller@10440000 {
137 compatible = "samsung,exynos4210-combiner";
138 #interrupt-cells = <2>;
139 interrupt-controller;
140 reg = <0x10440000 0x1000>;
144 compatible = "arm,cortex-a9-pmu";
145 interrupt-parent = <&combiner>;
146 interrupts = <2 2>, <3 2>;
149 sys_reg: syscon@10010000 {
150 compatible = "samsung,exynos4-sysreg", "syscon";
151 reg = <0x10010000 0x400>;
154 pmu_system_controller: system-controller@10020000 {
155 compatible = "samsung,exynos4210-pmu", "syscon";
156 reg = <0x10020000 0x4000>;
157 interrupt-controller;
158 #interrupt-cells = <3>;
159 interrupt-parent = <&gic>;
162 dsi_0: dsi@11C80000 {
163 compatible = "samsung,exynos4210-mipi-dsi";
164 reg = <0x11C80000 0x10000>;
165 interrupts = <0 79 0>;
166 power-domains = <&pd_lcd0>;
167 phys = <&mipi_phy 1>;
169 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
170 clock-names = "bus_clk", "pll_clk";
172 #address-cells = <1>;
177 compatible = "samsung,fimc", "simple-bus";
179 #address-cells = <1>;
182 clock-output-names = "cam_a_clkout", "cam_b_clkout";
185 fimc_0: fimc@11800000 {
186 compatible = "samsung,exynos4210-fimc";
187 reg = <0x11800000 0x1000>;
188 interrupts = <0 84 0>;
189 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
190 clock-names = "fimc", "sclk_fimc";
191 power-domains = <&pd_cam>;
192 samsung,sysreg = <&sys_reg>;
196 fimc_1: fimc@11810000 {
197 compatible = "samsung,exynos4210-fimc";
198 reg = <0x11810000 0x1000>;
199 interrupts = <0 85 0>;
200 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
201 clock-names = "fimc", "sclk_fimc";
202 power-domains = <&pd_cam>;
203 samsung,sysreg = <&sys_reg>;
207 fimc_2: fimc@11820000 {
208 compatible = "samsung,exynos4210-fimc";
209 reg = <0x11820000 0x1000>;
210 interrupts = <0 86 0>;
211 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
212 clock-names = "fimc", "sclk_fimc";
213 power-domains = <&pd_cam>;
214 samsung,sysreg = <&sys_reg>;
218 fimc_3: fimc@11830000 {
219 compatible = "samsung,exynos4210-fimc";
220 reg = <0x11830000 0x1000>;
221 interrupts = <0 87 0>;
222 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
223 clock-names = "fimc", "sclk_fimc";
224 power-domains = <&pd_cam>;
225 samsung,sysreg = <&sys_reg>;
229 csis_0: csis@11880000 {
230 compatible = "samsung,exynos4210-csis";
231 reg = <0x11880000 0x4000>;
232 interrupts = <0 78 0>;
233 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
234 clock-names = "csis", "sclk_csis";
236 power-domains = <&pd_cam>;
237 phys = <&mipi_phy 0>;
240 #address-cells = <1>;
244 csis_1: csis@11890000 {
245 compatible = "samsung,exynos4210-csis";
246 reg = <0x11890000 0x4000>;
247 interrupts = <0 80 0>;
248 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
249 clock-names = "csis", "sclk_csis";
251 power-domains = <&pd_cam>;
252 phys = <&mipi_phy 2>;
255 #address-cells = <1>;
261 compatible = "samsung,s3c2410-wdt";
262 reg = <0x10060000 0x100>;
263 interrupts = <0 43 0>;
264 clocks = <&clock CLK_WDT>;
265 clock-names = "watchdog";
270 compatible = "samsung,s3c6410-rtc";
271 reg = <0x10070000 0x100>;
272 interrupt-parent = <&pmu_system_controller>;
273 interrupts = <0 44 0>, <0 45 0>;
274 clocks = <&clock CLK_RTC>;
280 compatible = "samsung,s5pv210-keypad";
281 reg = <0x100A0000 0x100>;
282 interrupts = <0 109 0>;
283 clocks = <&clock CLK_KEYIF>;
284 clock-names = "keypad";
289 compatible = "samsung,exynos4210-sdhci";
290 reg = <0x12510000 0x100>;
291 interrupts = <0 73 0>;
292 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
293 clock-names = "hsmmc", "mmc_busclk.2";
298 compatible = "samsung,exynos4210-sdhci";
299 reg = <0x12520000 0x100>;
300 interrupts = <0 74 0>;
301 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
302 clock-names = "hsmmc", "mmc_busclk.2";
307 compatible = "samsung,exynos4210-sdhci";
308 reg = <0x12530000 0x100>;
309 interrupts = <0 75 0>;
310 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
311 clock-names = "hsmmc", "mmc_busclk.2";
316 compatible = "samsung,exynos4210-sdhci";
317 reg = <0x12540000 0x100>;
318 interrupts = <0 76 0>;
319 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
320 clock-names = "hsmmc", "mmc_busclk.2";
324 exynos_usbphy: exynos-usbphy@125B0000 {
325 compatible = "samsung,exynos4210-usb2-phy";
326 reg = <0x125B0000 0x100>;
327 samsung,pmureg-phandle = <&pmu_system_controller>;
328 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
329 clock-names = "phy", "ref";
335 compatible = "samsung,s3c6400-hsotg";
336 reg = <0x12480000 0x20000>;
337 interrupts = <0 71 0>;
338 clocks = <&clock CLK_USB_DEVICE>;
340 phys = <&exynos_usbphy 0>;
341 phy-names = "usb2-phy";
346 compatible = "samsung,exynos4210-ehci";
347 reg = <0x12580000 0x100>;
348 interrupts = <0 70 0>;
349 clocks = <&clock CLK_USB_HOST>;
350 clock-names = "usbhost";
352 #address-cells = <1>;
356 phys = <&exynos_usbphy 1>;
361 phys = <&exynos_usbphy 2>;
366 phys = <&exynos_usbphy 3>;
372 compatible = "samsung,exynos4210-ohci";
373 reg = <0x12590000 0x100>;
374 interrupts = <0 70 0>;
375 clocks = <&clock CLK_USB_HOST>;
376 clock-names = "usbhost";
378 #address-cells = <1>;
382 phys = <&exynos_usbphy 1>;
388 compatible = "samsung,s3c6410-i2s";
389 reg = <0x13960000 0x100>;
390 clocks = <&clock CLK_I2S1>;
393 clock-output-names = "i2s_cdclk1";
394 dmas = <&pdma1 12>, <&pdma1 11>;
395 dma-names = "tx", "rx";
396 #sound-dai-cells = <1>;
401 compatible = "samsung,s3c6410-i2s";
402 reg = <0x13970000 0x100>;
403 clocks = <&clock CLK_I2S2>;
406 clock-output-names = "i2s_cdclk2";
407 dmas = <&pdma0 14>, <&pdma0 13>;
408 dma-names = "tx", "rx";
409 #sound-dai-cells = <1>;
413 mfc: codec@13400000 {
414 compatible = "samsung,mfc-v5";
415 reg = <0x13400000 0x10000>;
416 interrupts = <0 94 0>;
417 power-domains = <&pd_mfc>;
418 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
419 clock-names = "mfc", "sclk_mfc";
423 serial_0: serial@13800000 {
424 compatible = "samsung,exynos4210-uart";
425 reg = <0x13800000 0x100>;
426 interrupts = <0 52 0>;
427 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
428 clock-names = "uart", "clk_uart_baud0";
432 serial_1: serial@13810000 {
433 compatible = "samsung,exynos4210-uart";
434 reg = <0x13810000 0x100>;
435 interrupts = <0 53 0>;
436 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
437 clock-names = "uart", "clk_uart_baud0";
441 serial_2: serial@13820000 {
442 compatible = "samsung,exynos4210-uart";
443 reg = <0x13820000 0x100>;
444 interrupts = <0 54 0>;
445 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
446 clock-names = "uart", "clk_uart_baud0";
450 serial_3: serial@13830000 {
451 compatible = "samsung,exynos4210-uart";
452 reg = <0x13830000 0x100>;
453 interrupts = <0 55 0>;
454 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
455 clock-names = "uart", "clk_uart_baud0";
459 i2c_0: i2c@13860000 {
460 #address-cells = <1>;
462 compatible = "samsung,s3c2440-i2c";
463 reg = <0x13860000 0x100>;
464 interrupts = <0 58 0>;
465 clocks = <&clock CLK_I2C0>;
467 pinctrl-names = "default";
468 pinctrl-0 = <&i2c0_bus>;
472 i2c_1: i2c@13870000 {
473 #address-cells = <1>;
475 compatible = "samsung,s3c2440-i2c";
476 reg = <0x13870000 0x100>;
477 interrupts = <0 59 0>;
478 clocks = <&clock CLK_I2C1>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&i2c1_bus>;
485 i2c_2: i2c@13880000 {
486 #address-cells = <1>;
488 compatible = "samsung,s3c2440-i2c";
489 reg = <0x13880000 0x100>;
490 interrupts = <0 60 0>;
491 clocks = <&clock CLK_I2C2>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&i2c2_bus>;
498 i2c_3: i2c@13890000 {
499 #address-cells = <1>;
501 compatible = "samsung,s3c2440-i2c";
502 reg = <0x13890000 0x100>;
503 interrupts = <0 61 0>;
504 clocks = <&clock CLK_I2C3>;
506 pinctrl-names = "default";
507 pinctrl-0 = <&i2c3_bus>;
511 i2c_4: i2c@138A0000 {
512 #address-cells = <1>;
514 compatible = "samsung,s3c2440-i2c";
515 reg = <0x138A0000 0x100>;
516 interrupts = <0 62 0>;
517 clocks = <&clock CLK_I2C4>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&i2c4_bus>;
524 i2c_5: i2c@138B0000 {
525 #address-cells = <1>;
527 compatible = "samsung,s3c2440-i2c";
528 reg = <0x138B0000 0x100>;
529 interrupts = <0 63 0>;
530 clocks = <&clock CLK_I2C5>;
532 pinctrl-names = "default";
533 pinctrl-0 = <&i2c5_bus>;
537 i2c_6: i2c@138C0000 {
538 #address-cells = <1>;
540 compatible = "samsung,s3c2440-i2c";
541 reg = <0x138C0000 0x100>;
542 interrupts = <0 64 0>;
543 clocks = <&clock CLK_I2C6>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&i2c6_bus>;
550 i2c_7: i2c@138D0000 {
551 #address-cells = <1>;
553 compatible = "samsung,s3c2440-i2c";
554 reg = <0x138D0000 0x100>;
555 interrupts = <0 65 0>;
556 clocks = <&clock CLK_I2C7>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&i2c7_bus>;
563 i2c_8: i2c@138E0000 {
564 #address-cells = <1>;
566 compatible = "samsung,s3c2440-hdmiphy-i2c";
567 reg = <0x138E0000 0x100>;
568 interrupts = <0 93 0>;
569 clocks = <&clock CLK_I2C_HDMI>;
573 hdmi_i2c_phy: hdmiphy@38 {
574 compatible = "exynos4210-hdmiphy";
579 spi_0: spi@13920000 {
580 compatible = "samsung,exynos4210-spi";
581 reg = <0x13920000 0x100>;
582 interrupts = <0 66 0>;
583 dmas = <&pdma0 7>, <&pdma0 6>;
584 dma-names = "tx", "rx";
585 #address-cells = <1>;
587 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
588 clock-names = "spi", "spi_busclk0";
589 pinctrl-names = "default";
590 pinctrl-0 = <&spi0_bus>;
594 spi_1: spi@13930000 {
595 compatible = "samsung,exynos4210-spi";
596 reg = <0x13930000 0x100>;
597 interrupts = <0 67 0>;
598 dmas = <&pdma1 7>, <&pdma1 6>;
599 dma-names = "tx", "rx";
600 #address-cells = <1>;
602 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
603 clock-names = "spi", "spi_busclk0";
604 pinctrl-names = "default";
605 pinctrl-0 = <&spi1_bus>;
609 spi_2: spi@13940000 {
610 compatible = "samsung,exynos4210-spi";
611 reg = <0x13940000 0x100>;
612 interrupts = <0 68 0>;
613 dmas = <&pdma0 9>, <&pdma0 8>;
614 dma-names = "tx", "rx";
615 #address-cells = <1>;
617 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
618 clock-names = "spi", "spi_busclk0";
619 pinctrl-names = "default";
620 pinctrl-0 = <&spi2_bus>;
625 compatible = "samsung,exynos4210-pwm";
626 reg = <0x139D0000 0x1000>;
627 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
628 clocks = <&clock CLK_PWM>;
629 clock-names = "timers";
635 #address-cells = <1>;
637 compatible = "arm,amba-bus";
638 interrupt-parent = <&gic>;
641 pdma0: pdma@12680000 {
642 compatible = "arm,pl330", "arm,primecell";
643 reg = <0x12680000 0x1000>;
644 interrupts = <0 35 0>;
645 clocks = <&clock CLK_PDMA0>;
646 clock-names = "apb_pclk";
649 #dma-requests = <32>;
652 pdma1: pdma@12690000 {
653 compatible = "arm,pl330", "arm,primecell";
654 reg = <0x12690000 0x1000>;
655 interrupts = <0 36 0>;
656 clocks = <&clock CLK_PDMA1>;
657 clock-names = "apb_pclk";
660 #dma-requests = <32>;
663 mdma1: mdma@12850000 {
664 compatible = "arm,pl330", "arm,primecell";
665 reg = <0x12850000 0x1000>;
666 interrupts = <0 34 0>;
667 clocks = <&clock CLK_MDMA>;
668 clock-names = "apb_pclk";
675 fimd: fimd@11c00000 {
676 compatible = "samsung,exynos4210-fimd";
677 interrupt-parent = <&combiner>;
678 reg = <0x11c00000 0x20000>;
679 interrupt-names = "fifo", "vsync", "lcd_sys";
680 interrupts = <11 0>, <11 1>, <11 2>;
681 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
682 clock-names = "sclk_fimd", "fimd";
683 power-domains = <&pd_lcd0>;
684 samsung,sysreg = <&sys_reg>;
689 #include "exynos4412-tmu-sensor-conf.dtsi"
692 hdmi: hdmi@12D00000 {
693 compatible = "samsung,exynos4210-hdmi";
694 reg = <0x12D00000 0x70000>;
695 interrupts = <0 92 0>;
696 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
698 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
699 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
700 <&clock CLK_MOUT_HDMI>;
701 phy = <&hdmi_i2c_phy>;
702 power-domains = <&pd_tv>;
703 samsung,syscon-phandle = <&pmu_system_controller>;
707 mixer: mixer@12C10000 {
708 compatible = "samsung,exynos4210-mixer";
709 interrupts = <0 91 0>;
710 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
711 power-domains = <&pd_tv>;
715 ppmu_dmc0: ppmu_dmc0@106a0000 {
716 compatible = "samsung,exynos-ppmu";
717 reg = <0x106a0000 0x2000>;
718 clocks = <&clock CLK_PPMUDMC0>;
719 clock-names = "ppmu";
723 ppmu_dmc1: ppmu_dmc1@106b0000 {
724 compatible = "samsung,exynos-ppmu";
725 reg = <0x106b0000 0x2000>;
726 clocks = <&clock CLK_PPMUDMC1>;
727 clock-names = "ppmu";
731 ppmu_cpu: ppmu_cpu@106c0000 {
732 compatible = "samsung,exynos-ppmu";
733 reg = <0x106c0000 0x2000>;
734 clocks = <&clock CLK_PPMUCPU>;
735 clock-names = "ppmu";
739 ppmu_acp: ppmu_acp@10ae0000 {
740 compatible = "samsung,exynos-ppmu";
741 reg = <0x106e0000 0x2000>;
745 ppmu_rightbus: ppmu_rightbus@112a0000 {
746 compatible = "samsung,exynos-ppmu";
747 reg = <0x112a0000 0x2000>;
748 clocks = <&clock CLK_PPMURIGHT>;
749 clock-names = "ppmu";
753 ppmu_leftbus: ppmu_leftbus0@116a0000 {
754 compatible = "samsung,exynos-ppmu";
755 reg = <0x116a0000 0x2000>;
756 clocks = <&clock CLK_PPMULEFT>;
757 clock-names = "ppmu";
761 ppmu_camif: ppmu_camif@11ac0000 {
762 compatible = "samsung,exynos-ppmu";
763 reg = <0x11ac0000 0x2000>;
764 clocks = <&clock CLK_PPMUCAMIF>;
765 clock-names = "ppmu";
769 ppmu_lcd0: ppmu_lcd0@11e40000 {
770 compatible = "samsung,exynos-ppmu";
771 reg = <0x11e40000 0x2000>;
772 clocks = <&clock CLK_PPMULCD0>;
773 clock-names = "ppmu";
777 ppmu_fsys: ppmu_g3d@12630000 {
778 compatible = "samsung,exynos-ppmu";
779 reg = <0x12630000 0x2000>;
783 ppmu_image: ppmu_image@12aa0000 {
784 compatible = "samsung,exynos-ppmu";
785 reg = <0x12aa0000 0x2000>;
786 clocks = <&clock CLK_PPMUIMAGE>;
787 clock-names = "ppmu";
791 ppmu_tv: ppmu_tv@12e40000 {
792 compatible = "samsung,exynos-ppmu";
793 reg = <0x12e40000 0x2000>;
794 clocks = <&clock CLK_PPMUTV>;
795 clock-names = "ppmu";
799 ppmu_g3d: ppmu_g3d@13220000 {
800 compatible = "samsung,exynos-ppmu";
801 reg = <0x13220000 0x2000>;
802 clocks = <&clock CLK_PPMUG3D>;
803 clock-names = "ppmu";
807 ppmu_mfc_left: ppmu_mfc_left@13660000 {
808 compatible = "samsung,exynos-ppmu";
809 reg = <0x13660000 0x2000>;
810 clocks = <&clock CLK_PPMUMFC_L>;
811 clock-names = "ppmu";
815 ppmu_mfc_right: ppmu_mfc_right@13670000 {
816 compatible = "samsung,exynos-ppmu";
817 reg = <0x13670000 0x2000>;
818 clocks = <&clock CLK_PPMUMFC_R>;
819 clock-names = "ppmu";