2 * SAMSUNG EXYNOS5250 SoC device tree source
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <dt-bindings/clock/exynos5250.h>
21 #include "exynos5.dtsi"
22 #include "exynos5250-pinctrl.dtsi"
23 #include "exynos4-cpu-thermal.dtsi"
24 #include <dt-bindings/clock/exynos-audss-clk.h>
27 compatible = "samsung,exynos5250", "samsung,exynos5";
51 pinctrl0 = &pinctrl_0;
52 pinctrl1 = &pinctrl_1;
53 pinctrl2 = &pinctrl_2;
54 pinctrl3 = &pinctrl_3;
63 compatible = "arm,cortex-a15";
65 clock-frequency = <1700000000>;
66 cooling-min-level = <15>;
67 cooling-max-level = <9>;
68 #cooling-cells = <2>; /* min followed by max */
72 compatible = "arm,cortex-a15";
74 clock-frequency = <1700000000>;
79 compatible = "mmio-sram";
80 reg = <0x02020000 0x30000>;
83 ranges = <0 0x02020000 0x30000>;
86 compatible = "samsung,exynos4210-sysram";
91 compatible = "samsung,exynos4210-sysram-ns";
92 reg = <0x2f000 0x1000>;
96 pd_gsc: gsc-power-domain@10044000 {
97 compatible = "samsung,exynos4210-pd";
98 reg = <0x10044000 0x20>;
99 #power-domain-cells = <0>;
102 pd_mfc: mfc-power-domain@10044040 {
103 compatible = "samsung,exynos4210-pd";
104 reg = <0x10044040 0x20>;
105 #power-domain-cells = <0>;
108 pd_disp1: disp1-power-domain@100440A0 {
109 compatible = "samsung,exynos4210-pd";
110 reg = <0x100440A0 0x20>;
111 #power-domain-cells = <0>;
114 clock: clock-controller@10010000 {
115 compatible = "samsung,exynos5250-clock";
116 reg = <0x10010000 0x30000>;
120 clock_audss: audss-clock-controller@3810000 {
121 compatible = "samsung,exynos5250-audss-clock";
122 reg = <0x03810000 0x0C>;
124 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
125 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
126 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
130 compatible = "arm,armv7-timer";
131 interrupts = <1 13 0xf08>,
135 /* Unfortunately we need this since some versions of U-Boot
136 * on Exynos don't set the CNTFRQ register, so we need the
139 clock-frequency = <24000000>;
143 compatible = "samsung,exynos4210-mct";
144 reg = <0x101C0000 0x800>;
145 interrupt-controller;
146 #interrupt-cells = <2>;
147 interrupt-parent = <&mct_map>;
148 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
150 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
151 clock-names = "fin_pll", "mct";
154 #interrupt-cells = <2>;
155 #address-cells = <0>;
157 interrupt-map = <0x0 0 &combiner 23 3>,
158 <0x1 0 &combiner 23 4>,
159 <0x2 0 &combiner 25 2>,
160 <0x3 0 &combiner 25 3>,
161 <0x4 0 &gic 0 120 0>,
162 <0x5 0 &gic 0 121 0>;
167 compatible = "arm,cortex-a15-pmu";
168 interrupt-parent = <&combiner>;
169 interrupts = <1 2>, <22 4>;
172 pinctrl_0: pinctrl@11400000 {
173 compatible = "samsung,exynos5250-pinctrl";
174 reg = <0x11400000 0x1000>;
175 interrupts = <0 46 0>;
177 wakup_eint: wakeup-interrupt-controller {
178 compatible = "samsung,exynos4210-wakeup-eint";
179 interrupt-parent = <&gic>;
180 interrupts = <0 32 0>;
184 pinctrl_1: pinctrl@13400000 {
185 compatible = "samsung,exynos5250-pinctrl";
186 reg = <0x13400000 0x1000>;
187 interrupts = <0 45 0>;
190 pinctrl_2: pinctrl@10d10000 {
191 compatible = "samsung,exynos5250-pinctrl";
192 reg = <0x10d10000 0x1000>;
193 interrupts = <0 50 0>;
196 pinctrl_3: pinctrl@03860000 {
197 compatible = "samsung,exynos5250-pinctrl";
198 reg = <0x03860000 0x1000>;
199 interrupts = <0 47 0>;
202 pmu_system_controller: system-controller@10040000 {
203 compatible = "samsung,exynos5250-pmu", "syscon";
204 reg = <0x10040000 0x5000>;
205 clock-names = "clkout16";
206 clocks = <&clock CLK_FIN_PLL>;
208 interrupt-controller;
209 #interrupt-cells = <3>;
210 interrupt-parent = <&gic>;
213 sysreg_system_controller: syscon@10050000 {
214 compatible = "samsung,exynos5-sysreg", "syscon";
215 reg = <0x10050000 0x5000>;
219 compatible = "samsung,exynos5250-wdt";
220 reg = <0x101D0000 0x100>;
221 interrupts = <0 42 0>;
222 clocks = <&clock CLK_WDT>;
223 clock-names = "watchdog";
224 samsung,syscon-phandle = <&pmu_system_controller>;
228 compatible = "samsung,exynos5250-g2d";
229 reg = <0x10850000 0x1000>;
230 interrupts = <0 91 0>;
231 clocks = <&clock CLK_G2D>;
232 clock-names = "fimg2d";
233 iommus = <&sysmmu_g2d>;
236 mfc: codec@11000000 {
237 compatible = "samsung,mfc-v6";
238 reg = <0x11000000 0x10000>;
239 interrupts = <0 96 0>;
240 power-domains = <&pd_mfc>;
241 clocks = <&clock CLK_MFC>;
243 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
244 iommu-names = "left", "right";
248 compatible = "samsung,exynos5250-tmu";
249 reg = <0x10060000 0x100>;
250 interrupts = <0 65 0>;
251 clocks = <&clock CLK_TMU>;
252 clock-names = "tmu_apbif";
253 #include "exynos4412-tmu-sensor-conf.dtsi"
257 cpu_thermal: cpu-thermal {
258 polling-delay-passive = <0>;
260 thermal-sensors = <&tmu 0>;
264 /* Corresponds to 800MHz at freq_table */
265 cooling-device = <&cpu0 9 9>;
268 /* Corresponds to 200MHz at freq_table */
269 cooling-device = <&cpu0 15 15>;
275 sata: sata@122F0000 {
276 compatible = "snps,dwc-ahci";
277 samsung,sata-freq = <66>;
278 reg = <0x122F0000 0x1ff>;
279 interrupts = <0 115 0>;
280 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
281 clock-names = "sata", "sclk_sata";
283 phy-names = "sata-phy";
287 sata_phy: sata-phy@12170000 {
288 compatible = "samsung,exynos5250-sata-phy";
289 reg = <0x12170000 0x1ff>;
290 clocks = <&clock CLK_SATA_PHYCTRL>;
291 clock-names = "sata_phyctrl";
293 samsung,syscon-phandle = <&pmu_system_controller>;
297 i2c_0: i2c@12C60000 {
298 compatible = "samsung,s3c2440-i2c";
299 reg = <0x12C60000 0x100>;
300 interrupts = <0 56 0>;
301 #address-cells = <1>;
303 clocks = <&clock CLK_I2C0>;
305 pinctrl-names = "default";
306 pinctrl-0 = <&i2c0_bus>;
307 samsung,sysreg-phandle = <&sysreg_system_controller>;
311 i2c_1: i2c@12C70000 {
312 compatible = "samsung,s3c2440-i2c";
313 reg = <0x12C70000 0x100>;
314 interrupts = <0 57 0>;
315 #address-cells = <1>;
317 clocks = <&clock CLK_I2C1>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&i2c1_bus>;
321 samsung,sysreg-phandle = <&sysreg_system_controller>;
325 i2c_2: i2c@12C80000 {
326 compatible = "samsung,s3c2440-i2c";
327 reg = <0x12C80000 0x100>;
328 interrupts = <0 58 0>;
329 #address-cells = <1>;
331 clocks = <&clock CLK_I2C2>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&i2c2_bus>;
335 samsung,sysreg-phandle = <&sysreg_system_controller>;
339 i2c_3: i2c@12C90000 {
340 compatible = "samsung,s3c2440-i2c";
341 reg = <0x12C90000 0x100>;
342 interrupts = <0 59 0>;
343 #address-cells = <1>;
345 clocks = <&clock CLK_I2C3>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&i2c3_bus>;
349 samsung,sysreg-phandle = <&sysreg_system_controller>;
353 i2c_4: i2c@12CA0000 {
354 compatible = "samsung,s3c2440-i2c";
355 reg = <0x12CA0000 0x100>;
356 interrupts = <0 60 0>;
357 #address-cells = <1>;
359 clocks = <&clock CLK_I2C4>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&i2c4_bus>;
366 i2c_5: i2c@12CB0000 {
367 compatible = "samsung,s3c2440-i2c";
368 reg = <0x12CB0000 0x100>;
369 interrupts = <0 61 0>;
370 #address-cells = <1>;
372 clocks = <&clock CLK_I2C5>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&i2c5_bus>;
379 i2c_6: i2c@12CC0000 {
380 compatible = "samsung,s3c2440-i2c";
381 reg = <0x12CC0000 0x100>;
382 interrupts = <0 62 0>;
383 #address-cells = <1>;
385 clocks = <&clock CLK_I2C6>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&i2c6_bus>;
392 i2c_7: i2c@12CD0000 {
393 compatible = "samsung,s3c2440-i2c";
394 reg = <0x12CD0000 0x100>;
395 interrupts = <0 63 0>;
396 #address-cells = <1>;
398 clocks = <&clock CLK_I2C7>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&i2c7_bus>;
405 i2c_8: i2c@12CE0000 {
406 compatible = "samsung,s3c2440-hdmiphy-i2c";
407 reg = <0x12CE0000 0x1000>;
408 interrupts = <0 64 0>;
409 #address-cells = <1>;
411 clocks = <&clock CLK_I2C_HDMI>;
416 i2c_9: i2c@121D0000 {
417 compatible = "samsung,exynos5-sata-phy-i2c";
418 reg = <0x121D0000 0x100>;
419 #address-cells = <1>;
421 clocks = <&clock CLK_SATA_PHYI2C>;
426 spi_0: spi@12d20000 {
427 compatible = "samsung,exynos4210-spi";
429 reg = <0x12d20000 0x100>;
430 interrupts = <0 66 0>;
433 dma-names = "tx", "rx";
434 #address-cells = <1>;
436 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
437 clock-names = "spi", "spi_busclk0";
438 pinctrl-names = "default";
439 pinctrl-0 = <&spi0_bus>;
442 spi_1: spi@12d30000 {
443 compatible = "samsung,exynos4210-spi";
445 reg = <0x12d30000 0x100>;
446 interrupts = <0 67 0>;
449 dma-names = "tx", "rx";
450 #address-cells = <1>;
452 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
453 clock-names = "spi", "spi_busclk0";
454 pinctrl-names = "default";
455 pinctrl-0 = <&spi1_bus>;
458 spi_2: spi@12d40000 {
459 compatible = "samsung,exynos4210-spi";
461 reg = <0x12d40000 0x100>;
462 interrupts = <0 68 0>;
465 dma-names = "tx", "rx";
466 #address-cells = <1>;
468 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
469 clock-names = "spi", "spi_busclk0";
470 pinctrl-names = "default";
471 pinctrl-0 = <&spi2_bus>;
474 mmc_0: mmc@12200000 {
475 compatible = "samsung,exynos5250-dw-mshc";
476 interrupts = <0 75 0>;
477 #address-cells = <1>;
479 reg = <0x12200000 0x1000>;
480 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
481 clock-names = "biu", "ciu";
486 mmc_1: mmc@12210000 {
487 compatible = "samsung,exynos5250-dw-mshc";
488 interrupts = <0 76 0>;
489 #address-cells = <1>;
491 reg = <0x12210000 0x1000>;
492 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
493 clock-names = "biu", "ciu";
498 mmc_2: mmc@12220000 {
499 compatible = "samsung,exynos5250-dw-mshc";
500 interrupts = <0 77 0>;
501 #address-cells = <1>;
503 reg = <0x12220000 0x1000>;
504 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
505 clock-names = "biu", "ciu";
510 mmc_3: mmc@12230000 {
511 compatible = "samsung,exynos5250-dw-mshc";
512 reg = <0x12230000 0x1000>;
513 interrupts = <0 78 0>;
514 #address-cells = <1>;
516 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
517 clock-names = "biu", "ciu";
523 compatible = "samsung,s5pv210-i2s";
525 reg = <0x03830000 0x100>;
529 dma-names = "tx", "rx", "tx-sec";
530 clocks = <&clock_audss EXYNOS_I2S_BUS>,
531 <&clock_audss EXYNOS_I2S_BUS>,
532 <&clock_audss EXYNOS_SCLK_I2S>;
533 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
534 samsung,idma-addr = <0x03000000>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&i2s0_bus>;
540 compatible = "samsung,s3c6410-i2s";
542 reg = <0x12D60000 0x100>;
545 dma-names = "tx", "rx";
546 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
547 clock-names = "iis", "i2s_opclk0";
548 pinctrl-names = "default";
549 pinctrl-0 = <&i2s1_bus>;
553 compatible = "samsung,s3c6410-i2s";
555 reg = <0x12D70000 0x100>;
558 dma-names = "tx", "rx";
559 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
560 clock-names = "iis", "i2s_opclk0";
561 pinctrl-names = "default";
562 pinctrl-0 = <&i2s2_bus>;
566 compatible = "samsung,exynos5250-dwusb3";
567 clocks = <&clock CLK_USB3>;
568 clock-names = "usbdrd30";
569 #address-cells = <1>;
574 compatible = "synopsys,dwc3";
575 reg = <0x12000000 0x10000>;
576 interrupts = <0 72 0>;
577 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
578 phy-names = "usb2-phy", "usb3-phy";
582 usbdrd_phy: phy@12100000 {
583 compatible = "samsung,exynos5250-usbdrd-phy";
584 reg = <0x12100000 0x100>;
585 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
586 clock-names = "phy", "ref";
587 samsung,pmu-syscon = <&pmu_system_controller>;
592 compatible = "samsung,exynos4210-ehci";
593 reg = <0x12110000 0x100>;
594 interrupts = <0 71 0>;
596 clocks = <&clock CLK_USB2>;
597 clock-names = "usbhost";
598 #address-cells = <1>;
602 phys = <&usb2_phy_gen 1>;
607 compatible = "samsung,exynos4210-ohci";
608 reg = <0x12120000 0x100>;
609 interrupts = <0 71 0>;
611 clocks = <&clock CLK_USB2>;
612 clock-names = "usbhost";
613 #address-cells = <1>;
617 phys = <&usb2_phy_gen 1>;
621 usb2_phy_gen: phy@12130000 {
622 compatible = "samsung,exynos5250-usb2-phy";
623 reg = <0x12130000 0x100>;
624 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
625 clock-names = "phy", "ref";
627 samsung,sysreg-phandle = <&sysreg_system_controller>;
628 samsung,pmureg-phandle = <&pmu_system_controller>;
632 compatible = "samsung,exynos4210-pwm";
633 reg = <0x12dd0000 0x100>;
634 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
636 clocks = <&clock CLK_PWM>;
637 clock-names = "timers";
641 #address-cells = <1>;
643 compatible = "arm,amba-bus";
644 interrupt-parent = <&gic>;
647 pdma0: pdma@121A0000 {
648 compatible = "arm,pl330", "arm,primecell";
649 reg = <0x121A0000 0x1000>;
650 interrupts = <0 34 0>;
651 clocks = <&clock CLK_PDMA0>;
652 clock-names = "apb_pclk";
655 #dma-requests = <32>;
658 pdma1: pdma@121B0000 {
659 compatible = "arm,pl330", "arm,primecell";
660 reg = <0x121B0000 0x1000>;
661 interrupts = <0 35 0>;
662 clocks = <&clock CLK_PDMA1>;
663 clock-names = "apb_pclk";
666 #dma-requests = <32>;
669 mdma0: mdma@10800000 {
670 compatible = "arm,pl330", "arm,primecell";
671 reg = <0x10800000 0x1000>;
672 interrupts = <0 33 0>;
673 clocks = <&clock CLK_MDMA0>;
674 clock-names = "apb_pclk";
680 mdma1: mdma@11C10000 {
681 compatible = "arm,pl330", "arm,primecell";
682 reg = <0x11C10000 0x1000>;
683 interrupts = <0 124 0>;
684 clocks = <&clock CLK_MDMA1>;
685 clock-names = "apb_pclk";
692 gsc_0: gsc@13e00000 {
693 compatible = "samsung,exynos5-gsc";
694 reg = <0x13e00000 0x1000>;
695 interrupts = <0 85 0>;
696 power-domains = <&pd_gsc>;
697 clocks = <&clock CLK_GSCL0>;
698 clock-names = "gscl";
699 iommu = <&sysmmu_gsc0>;
702 gsc_1: gsc@13e10000 {
703 compatible = "samsung,exynos5-gsc";
704 reg = <0x13e10000 0x1000>;
705 interrupts = <0 86 0>;
706 power-domains = <&pd_gsc>;
707 clocks = <&clock CLK_GSCL1>;
708 clock-names = "gscl";
709 iommu = <&sysmmu_gsc1>;
712 gsc_2: gsc@13e20000 {
713 compatible = "samsung,exynos5-gsc";
714 reg = <0x13e20000 0x1000>;
715 interrupts = <0 87 0>;
716 power-domains = <&pd_gsc>;
717 clocks = <&clock CLK_GSCL2>;
718 clock-names = "gscl";
719 iommu = <&sysmmu_gsc2>;
722 gsc_3: gsc@13e30000 {
723 compatible = "samsung,exynos5-gsc";
724 reg = <0x13e30000 0x1000>;
725 interrupts = <0 88 0>;
726 power-domains = <&pd_gsc>;
727 clocks = <&clock CLK_GSCL3>;
728 clock-names = "gscl";
729 iommu = <&sysmmu_gsc3>;
733 compatible = "samsung,exynos4212-hdmi";
734 reg = <0x14530000 0x70000>;
735 power-domains = <&pd_disp1>;
736 interrupts = <0 95 0>;
737 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
738 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
739 <&clock CLK_MOUT_HDMI>;
740 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
741 "sclk_hdmiphy", "mout_hdmi";
742 samsung,syscon-phandle = <&pmu_system_controller>;
746 compatible = "samsung,exynos5250-mixer";
747 reg = <0x14450000 0x10000>;
748 power-domains = <&pd_disp1>;
749 interrupts = <0 94 0>;
750 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
751 <&clock CLK_SCLK_HDMI>;
752 clock-names = "mixer", "hdmi", "sclk_hdmi";
753 iommus = <&sysmmu_tv>;
756 dp_phy: video-phy@10040720 {
757 compatible = "samsung,exynos5250-dp-video-phy";
758 samsung,pmu-syscon = <&pmu_system_controller>;
763 compatible = "samsung,exynos-adc-v1";
764 reg = <0x12D10000 0x100>;
765 interrupts = <0 106 0>;
766 clocks = <&clock CLK_ADC>;
768 #io-channel-cells = <1>;
770 samsung,syscon-phandle = <&pmu_system_controller>;
775 compatible = "samsung,exynos4210-secss";
776 reg = <0x10830000 0x10000>;
777 interrupts = <0 112 0>;
778 clocks = <&clock CLK_SSS>;
779 clock-names = "secss";
782 sysmmu_g2d: sysmmu@10A60000 {
783 compatible = "samsung,exynos-sysmmu";
784 reg = <0x10A60000 0x1000>;
785 interrupt-parent = <&combiner>;
787 clock-names = "sysmmu", "master";
788 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
792 sysmmu_mfc_r: sysmmu@11200000 {
793 compatible = "samsung,exynos-sysmmu";
794 reg = <0x11200000 0x1000>;
795 interrupt-parent = <&combiner>;
797 power-domains = <&pd_mfc>;
798 clock-names = "sysmmu", "master";
799 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
803 sysmmu_mfc_l: sysmmu@11210000 {
804 compatible = "samsung,exynos-sysmmu";
805 reg = <0x11210000 0x1000>;
806 interrupt-parent = <&combiner>;
808 power-domains = <&pd_mfc>;
809 clock-names = "sysmmu", "master";
810 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
814 sysmmu_rotator: sysmmu@11D40000 {
815 compatible = "samsung,exynos-sysmmu";
816 reg = <0x11D40000 0x1000>;
817 interrupt-parent = <&combiner>;
819 clock-names = "sysmmu", "master";
820 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
824 sysmmu_jpeg: sysmmu@11F20000 {
825 compatible = "samsung,exynos-sysmmu";
826 reg = <0x11F20000 0x1000>;
827 interrupt-parent = <&combiner>;
829 power-domains = <&pd_gsc>;
830 clock-names = "sysmmu", "master";
831 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
835 sysmmu_fimc_isp: sysmmu@13260000 {
836 compatible = "samsung,exynos-sysmmu";
837 reg = <0x13260000 0x1000>;
838 interrupt-parent = <&combiner>;
840 clock-names = "sysmmu";
841 clocks = <&clock CLK_SMMU_FIMC_ISP>;
845 sysmmu_fimc_drc: sysmmu@13270000 {
846 compatible = "samsung,exynos-sysmmu";
847 reg = <0x13270000 0x1000>;
848 interrupt-parent = <&combiner>;
850 clock-names = "sysmmu";
851 clocks = <&clock CLK_SMMU_FIMC_DRC>;
855 sysmmu_fimc_fd: sysmmu@132A0000 {
856 compatible = "samsung,exynos-sysmmu";
857 reg = <0x132A0000 0x1000>;
858 interrupt-parent = <&combiner>;
860 clock-names = "sysmmu";
861 clocks = <&clock CLK_SMMU_FIMC_FD>;
865 sysmmu_fimc_scc: sysmmu@13280000 {
866 compatible = "samsung,exynos-sysmmu";
867 reg = <0x13280000 0x1000>;
868 interrupt-parent = <&combiner>;
870 clock-names = "sysmmu";
871 clocks = <&clock CLK_SMMU_FIMC_SCC>;
875 sysmmu_fimc_scp: sysmmu@13290000 {
876 compatible = "samsung,exynos-sysmmu";
877 reg = <0x13290000 0x1000>;
878 interrupt-parent = <&combiner>;
880 clock-names = "sysmmu";
881 clocks = <&clock CLK_SMMU_FIMC_SCP>;
885 sysmmu_fimc_mcuctl: sysmmu@132B0000 {
886 compatible = "samsung,exynos-sysmmu";
887 reg = <0x132B0000 0x1000>;
888 interrupt-parent = <&combiner>;
890 clock-names = "sysmmu";
891 clocks = <&clock CLK_SMMU_FIMC_MCU>;
895 sysmmu_fimc_odc: sysmmu@132C0000 {
896 compatible = "samsung,exynos-sysmmu";
897 reg = <0x132C0000 0x1000>;
898 interrupt-parent = <&combiner>;
900 clock-names = "sysmmu";
901 clocks = <&clock CLK_SMMU_FIMC_ODC>;
905 sysmmu_fimc_dis0: sysmmu@132D0000 {
906 compatible = "samsung,exynos-sysmmu";
907 reg = <0x132D0000 0x1000>;
908 interrupt-parent = <&combiner>;
910 clock-names = "sysmmu";
911 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
915 sysmmu_fimc_dis1: sysmmu@132E0000{
916 compatible = "samsung,exynos-sysmmu";
917 reg = <0x132E0000 0x1000>;
918 interrupt-parent = <&combiner>;
920 clock-names = "sysmmu";
921 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
925 sysmmu_fimc_3dnr: sysmmu@132F0000 {
926 compatible = "samsung,exynos-sysmmu";
927 reg = <0x132F0000 0x1000>;
928 interrupt-parent = <&combiner>;
930 clock-names = "sysmmu";
931 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
935 sysmmu_fimc_lite0: sysmmu@13C40000 {
936 compatible = "samsung,exynos-sysmmu";
937 reg = <0x13C40000 0x1000>;
938 interrupt-parent = <&combiner>;
940 power-domains = <&pd_gsc>;
941 clock-names = "sysmmu", "master";
942 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
946 sysmmu_fimc_lite1: sysmmu@13C50000 {
947 compatible = "samsung,exynos-sysmmu";
948 reg = <0x13C50000 0x1000>;
949 interrupt-parent = <&combiner>;
951 power-domains = <&pd_gsc>;
952 clock-names = "sysmmu", "master";
953 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
957 sysmmu_gsc0: sysmmu@13E80000 {
958 compatible = "samsung,exynos-sysmmu";
959 reg = <0x13E80000 0x1000>;
960 interrupt-parent = <&combiner>;
962 power-domains = <&pd_gsc>;
963 clock-names = "sysmmu", "master";
964 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
968 sysmmu_gsc1: sysmmu@13E90000 {
969 compatible = "samsung,exynos-sysmmu";
970 reg = <0x13E90000 0x1000>;
971 interrupt-parent = <&combiner>;
973 power-domains = <&pd_gsc>;
974 clock-names = "sysmmu", "master";
975 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
979 sysmmu_gsc2: sysmmu@13EA0000 {
980 compatible = "samsung,exynos-sysmmu";
981 reg = <0x13EA0000 0x1000>;
982 interrupt-parent = <&combiner>;
984 power-domains = <&pd_gsc>;
985 clock-names = "sysmmu", "master";
986 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
990 sysmmu_gsc3: sysmmu@13EB0000 {
991 compatible = "samsung,exynos-sysmmu";
992 reg = <0x13EB0000 0x1000>;
993 interrupt-parent = <&combiner>;
995 power-domains = <&pd_gsc>;
996 clock-names = "sysmmu", "master";
997 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1001 sysmmu_fimd1: sysmmu@14640000 {
1002 compatible = "samsung,exynos-sysmmu";
1003 reg = <0x14640000 0x1000>;
1004 interrupt-parent = <&combiner>;
1006 power-domains = <&pd_disp1>;
1007 clock-names = "sysmmu", "master";
1008 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1012 sysmmu_tv: sysmmu@14650000 {
1013 compatible = "samsung,exynos-sysmmu";
1014 reg = <0x14650000 0x1000>;
1015 interrupt-parent = <&combiner>;
1017 power-domains = <&pd_disp1>;
1018 clock-names = "sysmmu", "master";
1019 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1025 power-domains = <&pd_disp1>;
1026 clocks = <&clock CLK_DP>;
1033 power-domains = <&pd_disp1>;
1034 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1035 clock-names = "sclk_fimd", "fimd";
1036 iommus = <&sysmmu_fimd1>;
1040 clocks = <&clock CLK_RTC>;
1041 clock-names = "rtc";
1042 interrupt-parent = <&pmu_system_controller>;
1043 status = "disabled";
1047 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1048 clock-names = "uart", "clk_uart_baud0";
1052 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1053 clock-names = "uart", "clk_uart_baud0";
1057 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1058 clock-names = "uart", "clk_uart_baud0";
1062 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1063 clock-names = "uart", "clk_uart_baud0";