2 * SAMSUNG EXYNOS5250 SoC device tree source
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <dt-bindings/clock/exynos5250.h>
21 #include "exynos5.dtsi"
22 #include "exynos4-cpu-thermal.dtsi"
23 #include <dt-bindings/clock/exynos-audss-clk.h>
26 compatible = "samsung,exynos5250", "samsung,exynos5";
50 pinctrl0 = &pinctrl_0;
51 pinctrl1 = &pinctrl_1;
52 pinctrl2 = &pinctrl_2;
53 pinctrl3 = &pinctrl_3;
62 compatible = "arm,cortex-a15";
64 clock-frequency = <1700000000>;
65 clocks = <&clock CLK_ARM_CLK>;
67 clock-latency = <140000>;
87 cooling-min-level = <15>;
88 cooling-max-level = <9>;
89 #cooling-cells = <2>; /* min followed by max */
93 compatible = "arm,cortex-a15";
95 clock-frequency = <1700000000>;
100 compatible = "mmio-sram";
101 reg = <0x02020000 0x30000>;
102 #address-cells = <1>;
104 ranges = <0 0x02020000 0x30000>;
107 compatible = "samsung,exynos4210-sysram";
112 compatible = "samsung,exynos4210-sysram-ns";
113 reg = <0x2f000 0x1000>;
117 pd_gsc: gsc-power-domain@10044000 {
118 compatible = "samsung,exynos4210-pd";
119 reg = <0x10044000 0x20>;
120 #power-domain-cells = <0>;
123 pd_mfc: mfc-power-domain@10044040 {
124 compatible = "samsung,exynos4210-pd";
125 reg = <0x10044040 0x20>;
126 #power-domain-cells = <0>;
129 pd_disp1: disp1-power-domain@100440A0 {
130 compatible = "samsung,exynos4210-pd";
131 reg = <0x100440A0 0x20>;
132 #power-domain-cells = <0>;
133 clocks = <&clock CLK_FIN_PLL>,
134 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
135 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
136 clock-names = "oscclk", "clk0", "clk1";
139 clock: clock-controller@10010000 {
140 compatible = "samsung,exynos5250-clock";
141 reg = <0x10010000 0x30000>;
145 clock_audss: audss-clock-controller@3810000 {
146 compatible = "samsung,exynos5250-audss-clock";
147 reg = <0x03810000 0x0C>;
149 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
150 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
151 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
155 compatible = "arm,armv7-timer";
156 interrupts = <1 13 0xf08>,
160 /* Unfortunately we need this since some versions of U-Boot
161 * on Exynos don't set the CNTFRQ register, so we need the
164 clock-frequency = <24000000>;
168 compatible = "samsung,exynos4210-mct";
169 reg = <0x101C0000 0x800>;
170 interrupt-controller;
171 #interrupt-cells = <2>;
172 interrupt-parent = <&mct_map>;
173 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
175 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
176 clock-names = "fin_pll", "mct";
179 #interrupt-cells = <2>;
180 #address-cells = <0>;
182 interrupt-map = <0x0 0 &combiner 23 3>,
183 <0x1 0 &combiner 23 4>,
184 <0x2 0 &combiner 25 2>,
185 <0x3 0 &combiner 25 3>,
186 <0x4 0 &gic 0 120 0>,
187 <0x5 0 &gic 0 121 0>;
192 compatible = "arm,cortex-a15-pmu";
193 interrupt-parent = <&combiner>;
194 interrupts = <1 2>, <22 4>;
197 pinctrl_0: pinctrl@11400000 {
198 compatible = "samsung,exynos5250-pinctrl";
199 reg = <0x11400000 0x1000>;
200 interrupts = <0 46 0>;
202 wakup_eint: wakeup-interrupt-controller {
203 compatible = "samsung,exynos4210-wakeup-eint";
204 interrupt-parent = <&gic>;
205 interrupts = <0 32 0>;
209 pinctrl_1: pinctrl@13400000 {
210 compatible = "samsung,exynos5250-pinctrl";
211 reg = <0x13400000 0x1000>;
212 interrupts = <0 45 0>;
215 pinctrl_2: pinctrl@10d10000 {
216 compatible = "samsung,exynos5250-pinctrl";
217 reg = <0x10d10000 0x1000>;
218 interrupts = <0 50 0>;
221 pinctrl_3: pinctrl@03860000 {
222 compatible = "samsung,exynos5250-pinctrl";
223 reg = <0x03860000 0x1000>;
224 interrupts = <0 47 0>;
227 pmu_system_controller: system-controller@10040000 {
228 compatible = "samsung,exynos5250-pmu", "syscon";
229 reg = <0x10040000 0x5000>;
230 clock-names = "clkout16";
231 clocks = <&clock CLK_FIN_PLL>;
233 interrupt-controller;
234 #interrupt-cells = <3>;
235 interrupt-parent = <&gic>;
238 sysreg_system_controller: syscon@10050000 {
239 compatible = "samsung,exynos5-sysreg", "syscon";
240 reg = <0x10050000 0x5000>;
244 compatible = "samsung,exynos5250-wdt";
245 reg = <0x101D0000 0x100>;
246 interrupts = <0 42 0>;
247 clocks = <&clock CLK_WDT>;
248 clock-names = "watchdog";
249 samsung,syscon-phandle = <&pmu_system_controller>;
253 compatible = "samsung,exynos5250-g2d";
254 reg = <0x10850000 0x1000>;
255 interrupts = <0 91 0>;
256 clocks = <&clock CLK_G2D>;
257 clock-names = "fimg2d";
258 iommus = <&sysmmu_g2d>;
261 mfc: codec@11000000 {
262 compatible = "samsung,mfc-v6";
263 reg = <0x11000000 0x10000>;
264 interrupts = <0 96 0>;
265 power-domains = <&pd_mfc>;
266 clocks = <&clock CLK_MFC>;
268 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
269 iommu-names = "left", "right";
272 rotator: rotator@11C00000 {
273 compatible = "samsung,exynos5250-rotator";
274 reg = <0x11C00000 0x64>;
275 interrupts = <0 84 0>;
276 clocks = <&clock CLK_ROTATOR>;
277 clock-names = "rotator";
278 iommus = <&sysmmu_rotator>;
282 compatible = "samsung,exynos5250-tmu";
283 reg = <0x10060000 0x100>;
284 interrupts = <0 65 0>;
285 clocks = <&clock CLK_TMU>;
286 clock-names = "tmu_apbif";
287 #include "exynos4412-tmu-sensor-conf.dtsi"
291 cpu_thermal: cpu-thermal {
292 polling-delay-passive = <0>;
294 thermal-sensors = <&tmu 0>;
298 /* Corresponds to 800MHz at freq_table */
299 cooling-device = <&cpu0 9 9>;
302 /* Corresponds to 200MHz at freq_table */
303 cooling-device = <&cpu0 15 15>;
309 sata: sata@122F0000 {
310 compatible = "snps,dwc-ahci";
311 samsung,sata-freq = <66>;
312 reg = <0x122F0000 0x1ff>;
313 interrupts = <0 115 0>;
314 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
315 clock-names = "sata", "sclk_sata";
317 phy-names = "sata-phy";
321 sata_phy: sata-phy@12170000 {
322 compatible = "samsung,exynos5250-sata-phy";
323 reg = <0x12170000 0x1ff>;
324 clocks = <&clock CLK_SATA_PHYCTRL>;
325 clock-names = "sata_phyctrl";
327 samsung,syscon-phandle = <&pmu_system_controller>;
331 i2c_0: i2c@12C60000 {
332 compatible = "samsung,s3c2440-i2c";
333 reg = <0x12C60000 0x100>;
334 interrupts = <0 56 0>;
335 #address-cells = <1>;
337 clocks = <&clock CLK_I2C0>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&i2c0_bus>;
341 samsung,sysreg-phandle = <&sysreg_system_controller>;
345 i2c_1: i2c@12C70000 {
346 compatible = "samsung,s3c2440-i2c";
347 reg = <0x12C70000 0x100>;
348 interrupts = <0 57 0>;
349 #address-cells = <1>;
351 clocks = <&clock CLK_I2C1>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&i2c1_bus>;
355 samsung,sysreg-phandle = <&sysreg_system_controller>;
359 i2c_2: i2c@12C80000 {
360 compatible = "samsung,s3c2440-i2c";
361 reg = <0x12C80000 0x100>;
362 interrupts = <0 58 0>;
363 #address-cells = <1>;
365 clocks = <&clock CLK_I2C2>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c2_bus>;
369 samsung,sysreg-phandle = <&sysreg_system_controller>;
373 i2c_3: i2c@12C90000 {
374 compatible = "samsung,s3c2440-i2c";
375 reg = <0x12C90000 0x100>;
376 interrupts = <0 59 0>;
377 #address-cells = <1>;
379 clocks = <&clock CLK_I2C3>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&i2c3_bus>;
383 samsung,sysreg-phandle = <&sysreg_system_controller>;
387 i2c_4: i2c@12CA0000 {
388 compatible = "samsung,s3c2440-i2c";
389 reg = <0x12CA0000 0x100>;
390 interrupts = <0 60 0>;
391 #address-cells = <1>;
393 clocks = <&clock CLK_I2C4>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&i2c4_bus>;
400 i2c_5: i2c@12CB0000 {
401 compatible = "samsung,s3c2440-i2c";
402 reg = <0x12CB0000 0x100>;
403 interrupts = <0 61 0>;
404 #address-cells = <1>;
406 clocks = <&clock CLK_I2C5>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&i2c5_bus>;
413 i2c_6: i2c@12CC0000 {
414 compatible = "samsung,s3c2440-i2c";
415 reg = <0x12CC0000 0x100>;
416 interrupts = <0 62 0>;
417 #address-cells = <1>;
419 clocks = <&clock CLK_I2C6>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c6_bus>;
426 i2c_7: i2c@12CD0000 {
427 compatible = "samsung,s3c2440-i2c";
428 reg = <0x12CD0000 0x100>;
429 interrupts = <0 63 0>;
430 #address-cells = <1>;
432 clocks = <&clock CLK_I2C7>;
434 pinctrl-names = "default";
435 pinctrl-0 = <&i2c7_bus>;
439 i2c_8: i2c@12CE0000 {
440 compatible = "samsung,s3c2440-hdmiphy-i2c";
441 reg = <0x12CE0000 0x1000>;
442 interrupts = <0 64 0>;
443 #address-cells = <1>;
445 clocks = <&clock CLK_I2C_HDMI>;
450 i2c_9: i2c@121D0000 {
451 compatible = "samsung,exynos5-sata-phy-i2c";
452 reg = <0x121D0000 0x100>;
453 #address-cells = <1>;
455 clocks = <&clock CLK_SATA_PHYI2C>;
460 spi_0: spi@12d20000 {
461 compatible = "samsung,exynos4210-spi";
463 reg = <0x12d20000 0x100>;
464 interrupts = <0 66 0>;
467 dma-names = "tx", "rx";
468 #address-cells = <1>;
470 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
471 clock-names = "spi", "spi_busclk0";
472 pinctrl-names = "default";
473 pinctrl-0 = <&spi0_bus>;
476 spi_1: spi@12d30000 {
477 compatible = "samsung,exynos4210-spi";
479 reg = <0x12d30000 0x100>;
480 interrupts = <0 67 0>;
483 dma-names = "tx", "rx";
484 #address-cells = <1>;
486 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
487 clock-names = "spi", "spi_busclk0";
488 pinctrl-names = "default";
489 pinctrl-0 = <&spi1_bus>;
492 spi_2: spi@12d40000 {
493 compatible = "samsung,exynos4210-spi";
495 reg = <0x12d40000 0x100>;
496 interrupts = <0 68 0>;
499 dma-names = "tx", "rx";
500 #address-cells = <1>;
502 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
503 clock-names = "spi", "spi_busclk0";
504 pinctrl-names = "default";
505 pinctrl-0 = <&spi2_bus>;
508 mmc_0: mmc@12200000 {
509 compatible = "samsung,exynos5250-dw-mshc";
510 interrupts = <0 75 0>;
511 #address-cells = <1>;
513 reg = <0x12200000 0x1000>;
514 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
515 clock-names = "biu", "ciu";
520 mmc_1: mmc@12210000 {
521 compatible = "samsung,exynos5250-dw-mshc";
522 interrupts = <0 76 0>;
523 #address-cells = <1>;
525 reg = <0x12210000 0x1000>;
526 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
527 clock-names = "biu", "ciu";
532 mmc_2: mmc@12220000 {
533 compatible = "samsung,exynos5250-dw-mshc";
534 interrupts = <0 77 0>;
535 #address-cells = <1>;
537 reg = <0x12220000 0x1000>;
538 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
539 clock-names = "biu", "ciu";
544 mmc_3: mmc@12230000 {
545 compatible = "samsung,exynos5250-dw-mshc";
546 reg = <0x12230000 0x1000>;
547 interrupts = <0 78 0>;
548 #address-cells = <1>;
550 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
551 clock-names = "biu", "ciu";
557 compatible = "samsung,s5pv210-i2s";
559 reg = <0x03830000 0x100>;
563 dma-names = "tx", "rx", "tx-sec";
564 clocks = <&clock_audss EXYNOS_I2S_BUS>,
565 <&clock_audss EXYNOS_I2S_BUS>,
566 <&clock_audss EXYNOS_SCLK_I2S>;
567 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
568 samsung,idma-addr = <0x03000000>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&i2s0_bus>;
574 compatible = "samsung,s3c6410-i2s";
576 reg = <0x12D60000 0x100>;
579 dma-names = "tx", "rx";
580 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
581 clock-names = "iis", "i2s_opclk0";
582 pinctrl-names = "default";
583 pinctrl-0 = <&i2s1_bus>;
587 compatible = "samsung,s3c6410-i2s";
589 reg = <0x12D70000 0x100>;
592 dma-names = "tx", "rx";
593 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
594 clock-names = "iis", "i2s_opclk0";
595 pinctrl-names = "default";
596 pinctrl-0 = <&i2s2_bus>;
600 compatible = "samsung,exynos5250-dwusb3";
601 clocks = <&clock CLK_USB3>;
602 clock-names = "usbdrd30";
603 #address-cells = <1>;
608 compatible = "synopsys,dwc3";
609 reg = <0x12000000 0x10000>;
610 interrupts = <0 72 0>;
611 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
612 phy-names = "usb2-phy", "usb3-phy";
616 usbdrd_phy: phy@12100000 {
617 compatible = "samsung,exynos5250-usbdrd-phy";
618 reg = <0x12100000 0x100>;
619 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
620 clock-names = "phy", "ref";
621 samsung,pmu-syscon = <&pmu_system_controller>;
626 compatible = "samsung,exynos4210-ehci";
627 reg = <0x12110000 0x100>;
628 interrupts = <0 71 0>;
630 clocks = <&clock CLK_USB2>;
631 clock-names = "usbhost";
632 #address-cells = <1>;
636 phys = <&usb2_phy_gen 1>;
641 compatible = "samsung,exynos4210-ohci";
642 reg = <0x12120000 0x100>;
643 interrupts = <0 71 0>;
645 clocks = <&clock CLK_USB2>;
646 clock-names = "usbhost";
647 #address-cells = <1>;
651 phys = <&usb2_phy_gen 1>;
655 usb2_phy_gen: phy@12130000 {
656 compatible = "samsung,exynos5250-usb2-phy";
657 reg = <0x12130000 0x100>;
658 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
659 clock-names = "phy", "ref";
661 samsung,sysreg-phandle = <&sysreg_system_controller>;
662 samsung,pmureg-phandle = <&pmu_system_controller>;
666 compatible = "samsung,exynos4210-pwm";
667 reg = <0x12dd0000 0x100>;
668 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
670 clocks = <&clock CLK_PWM>;
671 clock-names = "timers";
675 #address-cells = <1>;
677 compatible = "simple-bus";
678 interrupt-parent = <&gic>;
681 pdma0: pdma@121A0000 {
682 compatible = "arm,pl330", "arm,primecell";
683 reg = <0x121A0000 0x1000>;
684 interrupts = <0 34 0>;
685 clocks = <&clock CLK_PDMA0>;
686 clock-names = "apb_pclk";
689 #dma-requests = <32>;
692 pdma1: pdma@121B0000 {
693 compatible = "arm,pl330", "arm,primecell";
694 reg = <0x121B0000 0x1000>;
695 interrupts = <0 35 0>;
696 clocks = <&clock CLK_PDMA1>;
697 clock-names = "apb_pclk";
700 #dma-requests = <32>;
703 mdma0: mdma@10800000 {
704 compatible = "arm,pl330", "arm,primecell";
705 reg = <0x10800000 0x1000>;
706 interrupts = <0 33 0>;
707 clocks = <&clock CLK_MDMA0>;
708 clock-names = "apb_pclk";
714 mdma1: mdma@11C10000 {
715 compatible = "arm,pl330", "arm,primecell";
716 reg = <0x11C10000 0x1000>;
717 interrupts = <0 124 0>;
718 clocks = <&clock CLK_MDMA1>;
719 clock-names = "apb_pclk";
726 gsc_0: gsc@13e00000 {
727 compatible = "samsung,exynos5-gsc";
728 reg = <0x13e00000 0x1000>;
729 interrupts = <0 85 0>;
730 power-domains = <&pd_gsc>;
731 clocks = <&clock CLK_GSCL0>;
732 clock-names = "gscl";
733 iommu = <&sysmmu_gsc0>;
736 gsc_1: gsc@13e10000 {
737 compatible = "samsung,exynos5-gsc";
738 reg = <0x13e10000 0x1000>;
739 interrupts = <0 86 0>;
740 power-domains = <&pd_gsc>;
741 clocks = <&clock CLK_GSCL1>;
742 clock-names = "gscl";
743 iommu = <&sysmmu_gsc1>;
746 gsc_2: gsc@13e20000 {
747 compatible = "samsung,exynos5-gsc";
748 reg = <0x13e20000 0x1000>;
749 interrupts = <0 87 0>;
750 power-domains = <&pd_gsc>;
751 clocks = <&clock CLK_GSCL2>;
752 clock-names = "gscl";
753 iommu = <&sysmmu_gsc2>;
756 gsc_3: gsc@13e30000 {
757 compatible = "samsung,exynos5-gsc";
758 reg = <0x13e30000 0x1000>;
759 interrupts = <0 88 0>;
760 power-domains = <&pd_gsc>;
761 clocks = <&clock CLK_GSCL3>;
762 clock-names = "gscl";
763 iommu = <&sysmmu_gsc3>;
767 compatible = "samsung,exynos4212-hdmi";
768 reg = <0x14530000 0x70000>;
769 power-domains = <&pd_disp1>;
770 interrupts = <0 95 0>;
771 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
772 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
773 <&clock CLK_MOUT_HDMI>;
774 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
775 "sclk_hdmiphy", "mout_hdmi";
776 samsung,syscon-phandle = <&pmu_system_controller>;
780 compatible = "samsung,exynos5250-mixer";
781 reg = <0x14450000 0x10000>;
782 power-domains = <&pd_disp1>;
783 interrupts = <0 94 0>;
784 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
785 <&clock CLK_SCLK_HDMI>;
786 clock-names = "mixer", "hdmi", "sclk_hdmi";
787 iommus = <&sysmmu_tv>;
790 dp_phy: video-phy@10040720 {
791 compatible = "samsung,exynos5250-dp-video-phy";
792 samsung,pmu-syscon = <&pmu_system_controller>;
797 compatible = "samsung,exynos-adc-v1";
798 reg = <0x12D10000 0x100>;
799 interrupts = <0 106 0>;
800 clocks = <&clock CLK_ADC>;
802 #io-channel-cells = <1>;
804 samsung,syscon-phandle = <&pmu_system_controller>;
809 compatible = "samsung,exynos4210-secss";
810 reg = <0x10830000 0x300>;
811 interrupts = <0 112 0>;
812 clocks = <&clock CLK_SSS>;
813 clock-names = "secss";
816 sysmmu_g2d: sysmmu@10A60000 {
817 compatible = "samsung,exynos-sysmmu";
818 reg = <0x10A60000 0x1000>;
819 interrupt-parent = <&combiner>;
821 clock-names = "sysmmu", "master";
822 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
826 sysmmu_mfc_r: sysmmu@11200000 {
827 compatible = "samsung,exynos-sysmmu";
828 reg = <0x11200000 0x1000>;
829 interrupt-parent = <&combiner>;
831 power-domains = <&pd_mfc>;
832 clock-names = "sysmmu", "master";
833 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
837 sysmmu_mfc_l: sysmmu@11210000 {
838 compatible = "samsung,exynos-sysmmu";
839 reg = <0x11210000 0x1000>;
840 interrupt-parent = <&combiner>;
842 power-domains = <&pd_mfc>;
843 clock-names = "sysmmu", "master";
844 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
848 sysmmu_rotator: sysmmu@11D40000 {
849 compatible = "samsung,exynos-sysmmu";
850 reg = <0x11D40000 0x1000>;
851 interrupt-parent = <&combiner>;
853 clock-names = "sysmmu", "master";
854 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
858 sysmmu_jpeg: sysmmu@11F20000 {
859 compatible = "samsung,exynos-sysmmu";
860 reg = <0x11F20000 0x1000>;
861 interrupt-parent = <&combiner>;
863 power-domains = <&pd_gsc>;
864 clock-names = "sysmmu", "master";
865 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
869 sysmmu_fimc_isp: sysmmu@13260000 {
870 compatible = "samsung,exynos-sysmmu";
871 reg = <0x13260000 0x1000>;
872 interrupt-parent = <&combiner>;
874 clock-names = "sysmmu";
875 clocks = <&clock CLK_SMMU_FIMC_ISP>;
879 sysmmu_fimc_drc: sysmmu@13270000 {
880 compatible = "samsung,exynos-sysmmu";
881 reg = <0x13270000 0x1000>;
882 interrupt-parent = <&combiner>;
884 clock-names = "sysmmu";
885 clocks = <&clock CLK_SMMU_FIMC_DRC>;
889 sysmmu_fimc_fd: sysmmu@132A0000 {
890 compatible = "samsung,exynos-sysmmu";
891 reg = <0x132A0000 0x1000>;
892 interrupt-parent = <&combiner>;
894 clock-names = "sysmmu";
895 clocks = <&clock CLK_SMMU_FIMC_FD>;
899 sysmmu_fimc_scc: sysmmu@13280000 {
900 compatible = "samsung,exynos-sysmmu";
901 reg = <0x13280000 0x1000>;
902 interrupt-parent = <&combiner>;
904 clock-names = "sysmmu";
905 clocks = <&clock CLK_SMMU_FIMC_SCC>;
909 sysmmu_fimc_scp: sysmmu@13290000 {
910 compatible = "samsung,exynos-sysmmu";
911 reg = <0x13290000 0x1000>;
912 interrupt-parent = <&combiner>;
914 clock-names = "sysmmu";
915 clocks = <&clock CLK_SMMU_FIMC_SCP>;
919 sysmmu_fimc_mcuctl: sysmmu@132B0000 {
920 compatible = "samsung,exynos-sysmmu";
921 reg = <0x132B0000 0x1000>;
922 interrupt-parent = <&combiner>;
924 clock-names = "sysmmu";
925 clocks = <&clock CLK_SMMU_FIMC_MCU>;
929 sysmmu_fimc_odc: sysmmu@132C0000 {
930 compatible = "samsung,exynos-sysmmu";
931 reg = <0x132C0000 0x1000>;
932 interrupt-parent = <&combiner>;
934 clock-names = "sysmmu";
935 clocks = <&clock CLK_SMMU_FIMC_ODC>;
939 sysmmu_fimc_dis0: sysmmu@132D0000 {
940 compatible = "samsung,exynos-sysmmu";
941 reg = <0x132D0000 0x1000>;
942 interrupt-parent = <&combiner>;
944 clock-names = "sysmmu";
945 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
949 sysmmu_fimc_dis1: sysmmu@132E0000{
950 compatible = "samsung,exynos-sysmmu";
951 reg = <0x132E0000 0x1000>;
952 interrupt-parent = <&combiner>;
954 clock-names = "sysmmu";
955 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
959 sysmmu_fimc_3dnr: sysmmu@132F0000 {
960 compatible = "samsung,exynos-sysmmu";
961 reg = <0x132F0000 0x1000>;
962 interrupt-parent = <&combiner>;
964 clock-names = "sysmmu";
965 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
969 sysmmu_fimc_lite0: sysmmu@13C40000 {
970 compatible = "samsung,exynos-sysmmu";
971 reg = <0x13C40000 0x1000>;
972 interrupt-parent = <&combiner>;
974 power-domains = <&pd_gsc>;
975 clock-names = "sysmmu", "master";
976 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
980 sysmmu_fimc_lite1: sysmmu@13C50000 {
981 compatible = "samsung,exynos-sysmmu";
982 reg = <0x13C50000 0x1000>;
983 interrupt-parent = <&combiner>;
985 power-domains = <&pd_gsc>;
986 clock-names = "sysmmu", "master";
987 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
991 sysmmu_gsc0: sysmmu@13E80000 {
992 compatible = "samsung,exynos-sysmmu";
993 reg = <0x13E80000 0x1000>;
994 interrupt-parent = <&combiner>;
996 power-domains = <&pd_gsc>;
997 clock-names = "sysmmu", "master";
998 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1002 sysmmu_gsc1: sysmmu@13E90000 {
1003 compatible = "samsung,exynos-sysmmu";
1004 reg = <0x13E90000 0x1000>;
1005 interrupt-parent = <&combiner>;
1007 power-domains = <&pd_gsc>;
1008 clock-names = "sysmmu", "master";
1009 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1013 sysmmu_gsc2: sysmmu@13EA0000 {
1014 compatible = "samsung,exynos-sysmmu";
1015 reg = <0x13EA0000 0x1000>;
1016 interrupt-parent = <&combiner>;
1018 power-domains = <&pd_gsc>;
1019 clock-names = "sysmmu", "master";
1020 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1024 sysmmu_gsc3: sysmmu@13EB0000 {
1025 compatible = "samsung,exynos-sysmmu";
1026 reg = <0x13EB0000 0x1000>;
1027 interrupt-parent = <&combiner>;
1029 power-domains = <&pd_gsc>;
1030 clock-names = "sysmmu", "master";
1031 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1035 sysmmu_fimd1: sysmmu@14640000 {
1036 compatible = "samsung,exynos-sysmmu";
1037 reg = <0x14640000 0x1000>;
1038 interrupt-parent = <&combiner>;
1040 power-domains = <&pd_disp1>;
1041 clock-names = "sysmmu", "master";
1042 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1046 sysmmu_tv: sysmmu@14650000 {
1047 compatible = "samsung,exynos-sysmmu";
1048 reg = <0x14650000 0x1000>;
1049 interrupt-parent = <&combiner>;
1051 power-domains = <&pd_disp1>;
1052 clock-names = "sysmmu", "master";
1053 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1059 power-domains = <&pd_disp1>;
1060 clocks = <&clock CLK_DP>;
1067 power-domains = <&pd_disp1>;
1068 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1069 clock-names = "sclk_fimd", "fimd";
1070 iommus = <&sysmmu_fimd1>;
1074 clocks = <&clock CLK_RTC>;
1075 clock-names = "rtc";
1076 interrupt-parent = <&pmu_system_controller>;
1077 status = "disabled";
1081 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1082 clock-names = "uart", "clk_uart_baud0";
1086 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1087 clock-names = "uart", "clk_uart_baud0";
1091 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1092 clock-names = "uart", "clk_uart_baud0";
1096 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1097 clock-names = "uart", "clk_uart_baud0";
1100 #include "exynos5250-pinctrl.dtsi"