arch/arm/boot/dts/exynos5410.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5410 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
   8  * EXYNOS5410 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include "skeleton.dtsi"
  17 #include <dt-bindings/clock/exynos5410.h>
  18
  19 / {
  20         compatible = "samsung,exynos5410", "samsung,exynos5";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 serial0 = &uart0;
  25                 serial1 = &uart1;
  26                 serial2 = &uart2;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 CPU0: cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a15";
  36                         reg = <0x0>;
  37                         clock-frequency = <1600000000>;
  38                 };
  39
  40                 CPU1: cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x1>;
  44                         clock-frequency = <1600000000>;
  45                 };
  46
  47                 CPU2: cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a15";
  50                         reg = <0x2>;
  51                         clock-frequency = <1600000000>;
  52                 };
  53
  54                 CPU3: cpu@3 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a15";
  57                         reg = <0x3>;
  58                         clock-frequency = <1600000000>;
  59                 };
  60         };
  61
  62         soc: soc {
  63                 compatible = "simple-bus";
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 ranges;
  67
  68                 combiner: interrupt-controller@10440000 {
  69                         compatible = "samsung,exynos4210-combiner";
  70                         #interrupt-cells = <2>;
  71                         interrupt-controller;
  72                         samsung,combiner-nr = <32>;
  73                         reg = <0x10440000 0x1000>;
  74                         interrupts =    <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  75                                         <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
  76                                         <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
  77                                         <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
  78                                         <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
  79                                         <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
  80                                         <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
  81                                         <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
  82                 };
  83
  84                 gic: interrupt-controller@10481000 {
  85                         compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  86                         #interrupt-cells = <3>;
  87                         interrupt-controller;
  88                         reg =   <0x10481000 0x1000>,
  89                                 <0x10482000 0x1000>,
  90                                 <0x10484000 0x2000>,
  91                                 <0x10486000 0x2000>;
  92                         interrupts = <1 9 0xf04>;
  93                 };
  94
  95                 chipid@10000000 {
  96                         compatible = "samsung,exynos4210-chipid";
  97                         reg = <0x10000000 0x100>;
  98                 };
  99
 100                 pmu_system_controller: system-controller@10040000 {
 101                         compatible = "samsung,exynos5410-pmu", "syscon";
 102                         reg = <0x10040000 0x5000>;
 103                 };
 104
 105                 poweroff: syscon-poweroff {
 106                         compatible = "syscon-poweroff";
 107                         regmap = <&pmu_system_controller>;
 108                         offset = <0x330C>; /* PS_HOLD_CONTROL */
 109                         mask = <0x5200>; /* reset value */
 110                 };
 111
 112                 reboot: syscon-reboot {
 113                         compatible = "syscon-reboot";
 114                         regmap = <&pmu_system_controller>;
 115                         offset = <0x0400>; /* SWRESET */
 116                         mask = <0x1>;
 117                 };
 118
 119                 mct: mct@101C0000 {
 120                         compatible = "samsung,exynos4210-mct";
 121                         reg = <0x101C0000 0xB00>;
 122                         interrupt-parent = <&interrupt_map>;
 123                         interrupts = <0>, <1>, <2>, <3>,
 124                                 <4>, <5>, <6>, <7>,
 125                                 <8>, <9>, <10>, <11>;
 126                         clocks = <&fin_pll>, <&clock CLK_MCT>;
 127                         clock-names = "fin_pll", "mct";
 128
 129                         interrupt_map: interrupt-map {
 130                                 #interrupt-cells = <1>;
 131                                 #address-cells = <0>;
 132                                 #size-cells = <0>;
 133                                 interrupt-map = <0 &combiner 23 3>,
 134                                                 <1 &combiner 23 4>,
 135                                                 <2 &combiner 25 2>,
 136                                                 <3 &combiner 25 3>,
 137                                                 <4 &gic 0 120 0>,
 138                                                 <5 &gic 0 121 0>,
 139                                                 <6 &gic 0 122 0>,
 140                                                 <7 &gic 0 123 0>,
 141                                                 <8 &gic 0 128 0>,
 142                                                 <9 &gic 0 129 0>,
 143                                                 <10 &gic 0 130 0>,
 144                                                 <11 &gic 0 131 0>;
 145                         };
 146                 };
 147
 148                 sysram@02020000 {
 149                         compatible = "mmio-sram";
 150                         reg = <0x02020000 0x54000>;
 151                         #address-cells = <1>;
 152                         #size-cells = <1>;
 153                         ranges = <0 0x02020000 0x54000>;
 154
 155                         smp-sysram@0 {
 156                                 compatible = "samsung,exynos4210-sysram";
 157                                 reg = <0x0 0x1000>;
 158                         };
 159
 160                         smp-sysram@53000 {
 161                                 compatible = "samsung,exynos4210-sysram-ns";
 162                                 reg = <0x53000 0x1000>;
 163                         };
 164                 };
 165
 166                 clock: clock-controller@10010000 {
 167                         compatible = "samsung,exynos5410-clock";
 168                         reg = <0x10010000 0x30000>;
 169                         #clock-cells = <1>;
 170                 };
 171
 172                 mmc_0: mmc@12200000 {
 173                         compatible = "samsung,exynos5250-dw-mshc";
 174                         reg = <0x12200000 0x1000>;
 175                         interrupts = <0 75 0>;
 176                         #address-cells = <1>;
 177                         #size-cells = <0>;
 178                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 179                         clock-names = "biu", "ciu";
 180                         fifo-depth = <0x80>;
 181                         status = "disabled";
 182                 };
 183
 184                 mmc_1: mmc@12210000 {
 185                         compatible = "samsung,exynos5250-dw-mshc";
 186                         reg = <0x12210000 0x1000>;
 187                         interrupts = <0 76 0>;
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 191                         clock-names = "biu", "ciu";
 192                         fifo-depth = <0x80>;
 193                         status = "disabled";
 194                 };
 195
 196                 mmc_2: mmc@12220000 {
 197                         compatible = "samsung,exynos5250-dw-mshc";
 198                         reg = <0x12220000 0x1000>;
 199                         interrupts = <0 77 0>;
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 203                         clock-names = "biu", "ciu";
 204                         fifo-depth = <0x80>;
 205                         status = "disabled";
 206                 };
 207
 208                 uart0: serial@12C00000 {
 209                         compatible = "samsung,exynos4210-uart";
 210                         reg = <0x12C00000 0x100>;
 211                         interrupts = <0 51 0>;
 212                         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 213                         clock-names = "uart", "clk_uart_baud0";
 214                         status = "disabled";
 215                 };
 216
 217                 uart1: serial@12C10000 {
 218                         compatible = "samsung,exynos4210-uart";
 219                         reg = <0x12C10000 0x100>;
 220                         interrupts = <0 52 0>;
 221                         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 222                         clock-names = "uart", "clk_uart_baud0";
 223                         status = "disabled";
 224                 };
 225
 226                 uart2: serial@12C20000 {
 227                         compatible = "samsung,exynos4210-uart";
 228                         reg = <0x12C20000 0x100>;
 229                         interrupts = <0 53 0>;
 230                         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 231                         clock-names = "uart", "clk_uart_baud0";
 232                         status = "disabled";
 233                 };
 234         };
 235 };