2 * SAMSUNG EXYNOS5410 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
8 * EXYNOS5410 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include "skeleton.dtsi"
17 #include <dt-bindings/clock/exynos5410.h>
20 compatible = "samsung,exynos5410", "samsung,exynos5";
21 interrupt-parent = <&gic>;
35 compatible = "arm,cortex-a15";
37 clock-frequency = <1600000000>;
42 compatible = "arm,cortex-a15";
44 clock-frequency = <1600000000>;
49 compatible = "arm,cortex-a15";
51 clock-frequency = <1600000000>;
56 compatible = "arm,cortex-a15";
58 clock-frequency = <1600000000>;
63 compatible = "simple-bus";
68 combiner: interrupt-controller@10440000 {
69 compatible = "samsung,exynos4210-combiner";
70 #interrupt-cells = <2>;
72 samsung,combiner-nr = <32>;
73 reg = <0x10440000 0x1000>;
74 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
75 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
76 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
77 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
78 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
79 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
80 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
81 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
84 gic: interrupt-controller@10481000 {
85 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
86 #interrupt-cells = <3>;
88 reg = <0x10481000 0x1000>,
92 interrupts = <1 9 0xf04>;
96 compatible = "samsung,exynos4210-chipid";
97 reg = <0x10000000 0x100>;
100 pmu_system_controller: system-controller@10040000 {
101 compatible = "samsung,exynos5410-pmu", "syscon";
102 reg = <0x10040000 0x5000>;
105 poweroff: syscon-poweroff {
106 compatible = "syscon-poweroff";
107 regmap = <&pmu_system_controller>;
108 offset = <0x330C>; /* PS_HOLD_CONTROL */
109 mask = <0x5200>; /* reset value */
112 reboot: syscon-reboot {
113 compatible = "syscon-reboot";
114 regmap = <&pmu_system_controller>;
115 offset = <0x0400>; /* SWRESET */
120 compatible = "samsung,exynos4210-mct";
121 reg = <0x101C0000 0xB00>;
122 interrupt-parent = <&interrupt_map>;
123 interrupts = <0>, <1>, <2>, <3>,
125 <8>, <9>, <10>, <11>;
126 clocks = <&fin_pll>, <&clock CLK_MCT>;
127 clock-names = "fin_pll", "mct";
129 interrupt_map: interrupt-map {
130 #interrupt-cells = <1>;
131 #address-cells = <0>;
133 interrupt-map = <0 &combiner 23 3>,
149 compatible = "mmio-sram";
150 reg = <0x02020000 0x54000>;
151 #address-cells = <1>;
153 ranges = <0 0x02020000 0x54000>;
156 compatible = "samsung,exynos4210-sysram";
161 compatible = "samsung,exynos4210-sysram-ns";
162 reg = <0x53000 0x1000>;
166 clock: clock-controller@10010000 {
167 compatible = "samsung,exynos5410-clock";
168 reg = <0x10010000 0x30000>;
172 mmc_0: mmc@12200000 {
173 compatible = "samsung,exynos5250-dw-mshc";
174 reg = <0x12200000 0x1000>;
175 interrupts = <0 75 0>;
176 #address-cells = <1>;
178 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
179 clock-names = "biu", "ciu";
184 mmc_1: mmc@12210000 {
185 compatible = "samsung,exynos5250-dw-mshc";
186 reg = <0x12210000 0x1000>;
187 interrupts = <0 76 0>;
188 #address-cells = <1>;
190 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
191 clock-names = "biu", "ciu";
196 mmc_2: mmc@12220000 {
197 compatible = "samsung,exynos5250-dw-mshc";
198 reg = <0x12220000 0x1000>;
199 interrupts = <0 77 0>;
200 #address-cells = <1>;
202 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
203 clock-names = "biu", "ciu";
208 uart0: serial@12C00000 {
209 compatible = "samsung,exynos4210-uart";
210 reg = <0x12C00000 0x100>;
211 interrupts = <0 51 0>;
212 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
213 clock-names = "uart", "clk_uart_baud0";
217 uart1: serial@12C10000 {
218 compatible = "samsung,exynos4210-uart";
219 reg = <0x12C10000 0x100>;
220 interrupts = <0 52 0>;
221 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
222 clock-names = "uart", "clk_uart_baud0";
226 uart2: serial@12C20000 {
227 compatible = "samsung,exynos4210-uart";
228 reg = <0x12C20000 0x100>;
229 interrupts = <0 53 0>;
230 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
231 clock-names = "uart", "clk_uart_baud0";