arch/arm/boot/dts/exynos5420-cpus.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC cpu device tree source
   3  *
   4  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This file provides desired ordering for Exynos5420 and Exynos5800
   8  * boards: CPU[0123] being the A15.
   9  *
  10  * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
  11  * but particular boards choose different booting order.
  12  *
  13  * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
  14  * booting cluster (big or LITTLE) is chosen by IROM code by reading
  15  * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
  16  * from the LITTLE: Cortex-A7.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  */
  22
  23 / {
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu0: cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a15";
  31                         reg = <0x0>;
  32                         clocks = <&clock CLK_ARM_CLK>;
  33                         clock-frequency = <1800000000>;
  34                         cci-control-port = <&cci_control1>;
  35                         operating-points-v2 = <&cluster_a15_opp_table>;
  36                 };
  37
  38                 cpu1: cpu@1 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a15";
  41                         reg = <0x1>;
  42                         clock-frequency = <1800000000>;
  43                         cci-control-port = <&cci_control1>;
  44                         operating-points-v2 = <&cluster_a15_opp_table>;
  45                 };
  46
  47                 cpu2: cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a15";
  50                         reg = <0x2>;
  51                         clock-frequency = <1800000000>;
  52                         cci-control-port = <&cci_control1>;
  53                         operating-points-v2 = <&cluster_a15_opp_table>;
  54                 };
  55
  56                 cpu3: cpu@3 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a15";
  59                         reg = <0x3>;
  60                         clock-frequency = <1800000000>;
  61                         cci-control-port = <&cci_control1>;
  62                         operating-points-v2 = <&cluster_a15_opp_table>;
  63                 };
  64
  65                 cpu4: cpu@100 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a7";
  68                         reg = <0x100>;
  69                         clocks = <&clock CLK_KFC_CLK>;
  70                         clock-frequency = <1000000000>;
  71                         cci-control-port = <&cci_control0>;
  72                         operating-points-v2 = <&cluster_a7_opp_table>;
  73                 };
  74
  75                 cpu5: cpu@101 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a7";
  78                         reg = <0x101>;
  79                         clock-frequency = <1000000000>;
  80                         cci-control-port = <&cci_control0>;
  81                         operating-points-v2 = <&cluster_a7_opp_table>;
  82                 };
  83
  84                 cpu6: cpu@102 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a7";
  87                         reg = <0x102>;
  88                         clock-frequency = <1000000000>;
  89                         cci-control-port = <&cci_control0>;
  90                         operating-points-v2 = <&cluster_a7_opp_table>;
  91                 };
  92
  93                 cpu7: cpu@103 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a7";
  96                         reg = <0x103>;
  97                         clock-frequency = <1000000000>;
  98                         cci-control-port = <&cci_control0>;
  99                         operating-points-v2 = <&cluster_a7_opp_table>;
 100                 };
 101         };
 102 };