arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include "exynos54xx.dtsi"
  17 #include <dt-bindings/clock/exynos5420.h>
  18 #include <dt-bindings/clock/exynos-audss-clk.h>
  19
  20 / {
  21         compatible = "samsung,exynos5420", "samsung,exynos5";
  22
  23         aliases {
  24                 mshc0 = &mmc_0;
  25                 mshc1 = &mmc_1;
  26                 mshc2 = &mmc_2;
  27                 pinctrl0 = &pinctrl_0;
  28                 pinctrl1 = &pinctrl_1;
  29                 pinctrl2 = &pinctrl_2;
  30                 pinctrl3 = &pinctrl_3;
  31                 pinctrl4 = &pinctrl_4;
  32                 i2c4 = &hsi2c_4;
  33                 i2c5 = &hsi2c_5;
  34                 i2c6 = &hsi2c_6;
  35                 i2c7 = &hsi2c_7;
  36                 i2c8 = &hsi2c_8;
  37                 i2c9 = &hsi2c_9;
  38                 i2c10 = &hsi2c_10;
  39                 gsc0 = &gsc_0;
  40                 gsc1 = &gsc_1;
  41                 spi0 = &spi_0;
  42                 spi1 = &spi_1;
  43                 spi2 = &spi_2;
  44                 usbdrdphy0 = &usbdrd_phy0;
  45                 usbdrdphy1 = &usbdrd_phy1;
  46         };
  47
  48         /*
  49          * The 'cpus' node is not present here but instead it is provided
  50          * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
  51          */
  52
  53         soc: soc {
  54                 cluster_a15_opp_table: opp_table0 {
  55                         compatible = "operating-points-v2";
  56                         opp-shared;
  57                         opp@1800000000 {
  58                                 opp-hz = /bits/ 64 <1800000000>;
  59                                 opp-microvolt = <1250000>;
  60                                 clock-latency-ns = <140000>;
  61                         };
  62                         opp@1700000000 {
  63                                 opp-hz = /bits/ 64 <1700000000>;
  64                                 opp-microvolt = <1212500>;
  65                                 clock-latency-ns = <140000>;
  66                         };
  67                         opp@1600000000 {
  68                                 opp-hz = /bits/ 64 <1600000000>;
  69                                 opp-microvolt = <1175000>;
  70                                 clock-latency-ns = <140000>;
  71                         };
  72                         opp@1500000000 {
  73                                 opp-hz = /bits/ 64 <1500000000>;
  74                                 opp-microvolt = <1137500>;
  75                                 clock-latency-ns = <140000>;
  76                         };
  77                         opp@1400000000 {
  78                                 opp-hz = /bits/ 64 <1400000000>;
  79                                 opp-microvolt = <1112500>;
  80                                 clock-latency-ns = <140000>;
  81                         };
  82                         opp@1300000000 {
  83                                 opp-hz = /bits/ 64 <1300000000>;
  84                                 opp-microvolt = <1062500>;
  85                                 clock-latency-ns = <140000>;
  86                         };
  87                         opp@1200000000 {
  88                                 opp-hz = /bits/ 64 <1200000000>;
  89                                 opp-microvolt = <1037500>;
  90                                 clock-latency-ns = <140000>;
  91                         };
  92                         opp@1100000000 {
  93                                 opp-hz = /bits/ 64 <1100000000>;
  94                                 opp-microvolt = <1012500>;
  95                                 clock-latency-ns = <140000>;
  96                         };
  97                         opp@1000000000 {
  98                                 opp-hz = /bits/ 64 <1000000000>;
  99                                 opp-microvolt = < 987500>;
 100                                 clock-latency-ns = <140000>;
 101                         };
 102                         opp@900000000 {
 103                                 opp-hz = /bits/ 64 <900000000>;
 104                                 opp-microvolt = < 962500>;
 105                                 clock-latency-ns = <140000>;
 106                         };
 107                         opp@800000000 {
 108                                 opp-hz = /bits/ 64 <800000000>;
 109                                 opp-microvolt = < 937500>;
 110                                 clock-latency-ns = <140000>;
 111                         };
 112                         opp@700000000 {
 113                                 opp-hz = /bits/ 64 <700000000>;
 114                                 opp-microvolt = < 912500>;
 115                                 clock-latency-ns = <140000>;
 116                         };
 117                 };
 118
 119                 cluster_a7_opp_table: opp_table1 {
 120                         compatible = "operating-points-v2";
 121                         opp-shared;
 122                         opp@1300000000 {
 123                                 opp-hz = /bits/ 64 <1300000000>;
 124                                 opp-microvolt = <1275000>;
 125                                 clock-latency-ns = <140000>;
 126                         };
 127                         opp@1200000000 {
 128                                 opp-hz = /bits/ 64 <1200000000>;
 129                                 opp-microvolt = <1212500>;
 130                                 clock-latency-ns = <140000>;
 131                         };
 132                         opp@1100000000 {
 133                                 opp-hz = /bits/ 64 <1100000000>;
 134                                 opp-microvolt = <1162500>;
 135                                 clock-latency-ns = <140000>;
 136                         };
 137                         opp@1000000000 {
 138                                 opp-hz = /bits/ 64 <1000000000>;
 139                                 opp-microvolt = <1112500>;
 140                                 clock-latency-ns = <140000>;
 141                         };
 142                         opp@900000000 {
 143                                 opp-hz = /bits/ 64 <900000000>;
 144                                 opp-microvolt = <1062500>;
 145                                 clock-latency-ns = <140000>;
 146                         };
 147                         opp@800000000 {
 148                                 opp-hz = /bits/ 64 <800000000>;
 149                                 opp-microvolt = <1025000>;
 150                                 clock-latency-ns = <140000>;
 151                         };
 152                         opp@700000000 {
 153                                 opp-hz = /bits/ 64 <700000000>;
 154                                 opp-microvolt = <975000>;
 155                                 clock-latency-ns = <140000>;
 156                         };
 157                         opp@600000000 {
 158                                 opp-hz = /bits/ 64 <600000000>;
 159                                 opp-microvolt = <937500>;
 160                                 clock-latency-ns = <140000>;
 161                         };
 162                 };
 163
 164                 cci: cci@10d20000 {
 165                         compatible = "arm,cci-400";
 166                         #address-cells = <1>;
 167                         #size-cells = <1>;
 168                         reg = <0x10d20000 0x1000>;
 169                         ranges = <0x0 0x10d20000 0x6000>;
 170
 171                         cci_control0: slave-if@4000 {
 172                                 compatible = "arm,cci-400-ctrl-if";
 173                                 interface-type = "ace";
 174                                 reg = <0x4000 0x1000>;
 175                         };
 176                         cci_control1: slave-if@5000 {
 177                                 compatible = "arm,cci-400-ctrl-if";
 178                                 interface-type = "ace";
 179                                 reg = <0x5000 0x1000>;
 180                         };
 181                 };
 182
 183                 clock: clock-controller@10010000 {
 184                         compatible = "samsung,exynos5420-clock";
 185                         reg = <0x10010000 0x30000>;
 186                         #clock-cells = <1>;
 187                 };
 188
 189                 clock_audss: audss-clock-controller@3810000 {
 190                         compatible = "samsung,exynos5420-audss-clock";
 191                         reg = <0x03810000 0x0C>;
 192                         #clock-cells = <1>;
 193                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
 194                                  <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 195                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 196                 };
 197
 198                 mfc: codec@11000000 {
 199                         compatible = "samsung,mfc-v7";
 200                         reg = <0x11000000 0x10000>;
 201                         interrupts = <0 96 0>;
 202                         clocks = <&clock CLK_MFC>;
 203                         clock-names = "mfc";
 204                         power-domains = <&mfc_pd>;
 205                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 206                         iommu-names = "left", "right";
 207                 };
 208
 209                 mmc_0: mmc@12200000 {
 210                         compatible = "samsung,exynos5420-dw-mshc-smu";
 211                         interrupts = <0 75 0>;
 212                         #address-cells = <1>;
 213                         #size-cells = <0>;
 214                         reg = <0x12200000 0x2000>;
 215                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 216                         clock-names = "biu", "ciu";
 217                         fifo-depth = <0x40>;
 218                         status = "disabled";
 219                 };
 220
 221                 mmc_1: mmc@12210000 {
 222                         compatible = "samsung,exynos5420-dw-mshc-smu";
 223                         interrupts = <0 76 0>;
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226                         reg = <0x12210000 0x2000>;
 227                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 228                         clock-names = "biu", "ciu";
 229                         fifo-depth = <0x40>;
 230                         status = "disabled";
 231                 };
 232
 233                 mmc_2: mmc@12220000 {
 234                         compatible = "samsung,exynos5420-dw-mshc";
 235                         interrupts = <0 77 0>;
 236                         #address-cells = <1>;
 237                         #size-cells = <0>;
 238                         reg = <0x12220000 0x1000>;
 239                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 240                         clock-names = "biu", "ciu";
 241                         fifo-depth = <0x40>;
 242                         status = "disabled";
 243                 };
 244
 245                 nocp_mem0_0: nocp@10CA1000 {
 246                         compatible = "samsung,exynos5420-nocp";
 247                         reg = <0x10CA1000 0x200>;
 248                         status = "disabled";
 249                 };
 250
 251                 nocp_mem0_1: nocp@10CA1400 {
 252                         compatible = "samsung,exynos5420-nocp";
 253                         reg = <0x10CA1400 0x200>;
 254                         status = "disabled";
 255                 };
 256
 257                 nocp_mem1_0: nocp@10CA1800 {
 258                         compatible = "samsung,exynos5420-nocp";
 259                         reg = <0x10CA1800 0x200>;
 260                         status = "disabled";
 261                 };
 262
 263                 nocp_mem1_1: nocp@10CA1C00 {
 264                         compatible = "samsung,exynos5420-nocp";
 265                         reg = <0x10CA1C00 0x200>;
 266                         status = "disabled";
 267                 };
 268
 269                 nocp_g3d_0: nocp@11A51000 {
 270                         compatible = "samsung,exynos5420-nocp";
 271                         reg = <0x11A51000 0x200>;
 272                         status = "disabled";
 273                 };
 274
 275                 nocp_g3d_1: nocp@11A51400 {
 276                         compatible = "samsung,exynos5420-nocp";
 277                         reg = <0x11A51400 0x200>;
 278                         status = "disabled";
 279                 };
 280
 281                 gsc_pd: power-domain@10044000 {
 282                         compatible = "samsung,exynos4210-pd";
 283                         reg = <0x10044000 0x20>;
 284                         #power-domain-cells = <0>;
 285                         clocks = <&clock CLK_FIN_PLL>,
 286                                  <&clock CLK_MOUT_USER_ACLK300_GSCL>,
 287                                  <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
 288                         clock-names = "oscclk", "clk0", "asb0", "asb1";
 289                 };
 290
 291                 isp_pd: power-domain@10044020 {
 292                         compatible = "samsung,exynos4210-pd";
 293                         reg = <0x10044020 0x20>;
 294                         #power-domain-cells = <0>;
 295                 };
 296
 297                 mfc_pd: power-domain@10044060 {
 298                         compatible = "samsung,exynos4210-pd";
 299                         reg = <0x10044060 0x20>;
 300                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
 301                         clock-names = "oscclk", "clk0";
 302                         #power-domain-cells = <0>;
 303                 };
 304
 305                 msc_pd: power-domain@10044120 {
 306                         compatible = "samsung,exynos4210-pd";
 307                         reg = <0x10044120 0x20>;
 308                         #power-domain-cells = <0>;
 309                 };
 310
 311                 disp_pd: power-domain@100440C0 {
 312                         compatible = "samsung,exynos4210-pd";
 313                         reg = <0x100440C0 0x20>;
 314                         #power-domain-cells = <0>;
 315                         clocks = <&clock CLK_FIN_PLL>,
 316                                  <&clock CLK_MOUT_USER_ACLK200_DISP1>,
 317                                  <&clock CLK_MOUT_USER_ACLK300_DISP1>,
 318                                  <&clock CLK_MOUT_USER_ACLK400_DISP1>,
 319                                  <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
 320                         clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
 321                 };
 322
 323                 pinctrl_0: pinctrl@13400000 {
 324                         compatible = "samsung,exynos5420-pinctrl";
 325                         reg = <0x13400000 0x1000>;
 326                         interrupts = <0 45 0>;
 327
 328                         wakeup-interrupt-controller {
 329                                 compatible = "samsung,exynos4210-wakeup-eint";
 330                                 interrupt-parent = <&gic>;
 331                                 interrupts = <0 32 0>;
 332                         };
 333                 };
 334
 335                 pinctrl_1: pinctrl@13410000 {
 336                         compatible = "samsung,exynos5420-pinctrl";
 337                         reg = <0x13410000 0x1000>;
 338                         interrupts = <0 78 0>;
 339                 };
 340
 341                 pinctrl_2: pinctrl@14000000 {
 342                         compatible = "samsung,exynos5420-pinctrl";
 343                         reg = <0x14000000 0x1000>;
 344                         interrupts = <0 46 0>;
 345                 };
 346
 347                 pinctrl_3: pinctrl@14010000 {
 348                         compatible = "samsung,exynos5420-pinctrl";
 349                         reg = <0x14010000 0x1000>;
 350                         interrupts = <0 50 0>;
 351                 };
 352
 353                 pinctrl_4: pinctrl@03860000 {
 354                         compatible = "samsung,exynos5420-pinctrl";
 355                         reg = <0x03860000 0x1000>;
 356                         interrupts = <0 47 0>;
 357                 };
 358
 359                 amba {
 360                         #address-cells = <1>;
 361                         #size-cells = <1>;
 362                         compatible = "simple-bus";
 363                         interrupt-parent = <&gic>;
 364                         ranges;
 365
 366                         adma: adma@03880000 {
 367                                 compatible = "arm,pl330", "arm,primecell";
 368                                 reg = <0x03880000 0x1000>;
 369                                 interrupts = <0 110 0>;
 370                                 clocks = <&clock_audss EXYNOS_ADMA>;
 371                                 clock-names = "apb_pclk";
 372                                 #dma-cells = <1>;
 373                                 #dma-channels = <6>;
 374                                 #dma-requests = <16>;
 375                         };
 376
 377                         pdma0: pdma@121A0000 {
 378                                 compatible = "arm,pl330", "arm,primecell";
 379                                 reg = <0x121A0000 0x1000>;
 380                                 interrupts = <0 34 0>;
 381                                 clocks = <&clock CLK_PDMA0>;
 382                                 clock-names = "apb_pclk";
 383                                 #dma-cells = <1>;
 384                                 #dma-channels = <8>;
 385                                 #dma-requests = <32>;
 386                         };
 387
 388                         pdma1: pdma@121B0000 {
 389                                 compatible = "arm,pl330", "arm,primecell";
 390                                 reg = <0x121B0000 0x1000>;
 391                                 interrupts = <0 35 0>;
 392                                 clocks = <&clock CLK_PDMA1>;
 393                                 clock-names = "apb_pclk";
 394                                 #dma-cells = <1>;
 395                                 #dma-channels = <8>;
 396                                 #dma-requests = <32>;
 397                         };
 398
 399                         mdma0: mdma@10800000 {
 400                                 compatible = "arm,pl330", "arm,primecell";
 401                                 reg = <0x10800000 0x1000>;
 402                                 interrupts = <0 33 0>;
 403                                 clocks = <&clock CLK_MDMA0>;
 404                                 clock-names = "apb_pclk";
 405                                 #dma-cells = <1>;
 406                                 #dma-channels = <8>;
 407                                 #dma-requests = <1>;
 408                         };
 409
 410                         mdma1: mdma@11C10000 {
 411                                 compatible = "arm,pl330", "arm,primecell";
 412                                 reg = <0x11C10000 0x1000>;
 413                                 interrupts = <0 124 0>;
 414                                 clocks = <&clock CLK_MDMA1>;
 415                                 clock-names = "apb_pclk";
 416                                 #dma-cells = <1>;
 417                                 #dma-channels = <8>;
 418                                 #dma-requests = <1>;
 419                                 /*
 420                                  * MDMA1 can support both secure and non-secure
 421                                  * AXI transactions. When this is enabled in
 422                                  * the kernel for boards that run in secure
 423                                  * mode, we are getting imprecise external
 424                                  * aborts causing the kernel to oops.
 425                                  */
 426                                 status = "disabled";
 427                         };
 428                 };
 429
 430                 i2s0: i2s@03830000 {
 431                         compatible = "samsung,exynos5420-i2s";
 432                         reg = <0x03830000 0x100>;
 433                         dmas = <&adma 0
 434                                 &adma 2
 435                                 &adma 1>;
 436                         dma-names = "tx", "rx", "tx-sec";
 437                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 438                                 <&clock_audss EXYNOS_I2S_BUS>,
 439                                 <&clock_audss EXYNOS_SCLK_I2S>;
 440                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 441                         #clock-cells = <1>;
 442                         clock-output-names = "i2s_cdclk0";
 443                         #sound-dai-cells = <1>;
 444                         samsung,idma-addr = <0x03000000>;
 445                         pinctrl-names = "default";
 446                         pinctrl-0 = <&i2s0_bus>;
 447                         status = "disabled";
 448                 };
 449
 450                 i2s1: i2s@12D60000 {
 451                         compatible = "samsung,exynos5420-i2s";
 452                         reg = <0x12D60000 0x100>;
 453                         dmas = <&pdma1 12
 454                                 &pdma1 11>;
 455                         dma-names = "tx", "rx";
 456                         clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 457                         clock-names = "iis", "i2s_opclk0";
 458                         #clock-cells = <1>;
 459                         clock-output-names = "i2s_cdclk1";
 460                         #sound-dai-cells = <1>;
 461                         pinctrl-names = "default";
 462                         pinctrl-0 = <&i2s1_bus>;
 463                         status = "disabled";
 464                 };
 465
 466                 i2s2: i2s@12D70000 {
 467                         compatible = "samsung,exynos5420-i2s";
 468                         reg = <0x12D70000 0x100>;
 469                         dmas = <&pdma0 12
 470                                 &pdma0 11>;
 471                         dma-names = "tx", "rx";
 472                         clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 473                         clock-names = "iis", "i2s_opclk0";
 474                         #clock-cells = <1>;
 475                         clock-output-names = "i2s_cdclk2";
 476                         #sound-dai-cells = <1>;
 477                         pinctrl-names = "default";
 478                         pinctrl-0 = <&i2s2_bus>;
 479                         status = "disabled";
 480                 };
 481
 482                 spi_0: spi@12d20000 {
 483                         compatible = "samsung,exynos4210-spi";
 484                         reg = <0x12d20000 0x100>;
 485                         interrupts = <0 68 0>;
 486                         dmas = <&pdma0 5
 487                                 &pdma0 4>;
 488                         dma-names = "tx", "rx";
 489                         #address-cells = <1>;
 490                         #size-cells = <0>;
 491                         pinctrl-names = "default";
 492                         pinctrl-0 = <&spi0_bus>;
 493                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 494                         clock-names = "spi", "spi_busclk0";
 495                         status = "disabled";
 496                 };
 497
 498                 spi_1: spi@12d30000 {
 499                         compatible = "samsung,exynos4210-spi";
 500                         reg = <0x12d30000 0x100>;
 501                         interrupts = <0 69 0>;
 502                         dmas = <&pdma1 5
 503                                 &pdma1 4>;
 504                         dma-names = "tx", "rx";
 505                         #address-cells = <1>;
 506                         #size-cells = <0>;
 507                         pinctrl-names = "default";
 508                         pinctrl-0 = <&spi1_bus>;
 509                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 510                         clock-names = "spi", "spi_busclk0";
 511                         status = "disabled";
 512                 };
 513
 514                 spi_2: spi@12d40000 {
 515                         compatible = "samsung,exynos4210-spi";
 516                         reg = <0x12d40000 0x100>;
 517                         interrupts = <0 70 0>;
 518                         dmas = <&pdma0 7
 519                                 &pdma0 6>;
 520                         dma-names = "tx", "rx";
 521                         #address-cells = <1>;
 522                         #size-cells = <0>;
 523                         pinctrl-names = "default";
 524                         pinctrl-0 = <&spi2_bus>;
 525                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 526                         clock-names = "spi", "spi_busclk0";
 527                         status = "disabled";
 528                 };
 529
 530                 dp_phy: dp-video-phy {
 531                         compatible = "samsung,exynos5420-dp-video-phy";
 532                         samsung,pmu-syscon = <&pmu_system_controller>;
 533                         #phy-cells = <0>;
 534                 };
 535
 536                 mipi_phy: mipi-video-phy {
 537                         compatible = "samsung,s5pv210-mipi-video-phy";
 538                         syscon = <&pmu_system_controller>;
 539                         #phy-cells = <1>;
 540                 };
 541
 542                 dsi@14500000 {
 543                         compatible = "samsung,exynos5410-mipi-dsi";
 544                         reg = <0x14500000 0x10000>;
 545                         interrupts = <0 82 0>;
 546                         phys = <&mipi_phy 1>;
 547                         phy-names = "dsim";
 548                         clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
 549                         clock-names = "bus_clk", "pll_clk";
 550                         #address-cells = <1>;
 551                         #size-cells = <0>;
 552                         status = "disabled";
 553                 };
 554
 555                 adc: adc@12D10000 {
 556                         compatible = "samsung,exynos-adc-v2";
 557                         reg = <0x12D10000 0x100>;
 558                         interrupts = <0 106 0>;
 559                         clocks = <&clock CLK_TSADC>;
 560                         clock-names = "adc";
 561                         #io-channel-cells = <1>;
 562                         io-channel-ranges;
 563                         samsung,syscon-phandle = <&pmu_system_controller>;
 564                         status = "disabled";
 565                 };
 566
 567                 /* i2c_0-3 are defined in exynos5.dtsi */
 568                 hsi2c_4: i2c@12CA0000 {
 569                         compatible = "samsung,exynos5250-hsi2c";
 570                         reg = <0x12CA0000 0x1000>;
 571                         interrupts = <0 60 0>;
 572                         #address-cells = <1>;
 573                         #size-cells = <0>;
 574                         pinctrl-names = "default";
 575                         pinctrl-0 = <&i2c4_hs_bus>;
 576                         clocks = <&clock CLK_USI0>;
 577                         clock-names = "hsi2c";
 578                         status = "disabled";
 579                 };
 580
 581                 hsi2c_5: i2c@12CB0000 {
 582                         compatible = "samsung,exynos5250-hsi2c";
 583                         reg = <0x12CB0000 0x1000>;
 584                         interrupts = <0 61 0>;
 585                         #address-cells = <1>;
 586                         #size-cells = <0>;
 587                         pinctrl-names = "default";
 588                         pinctrl-0 = <&i2c5_hs_bus>;
 589                         clocks = <&clock CLK_USI1>;
 590                         clock-names = "hsi2c";
 591                         status = "disabled";
 592                 };
 593
 594                 hsi2c_6: i2c@12CC0000 {
 595                         compatible = "samsung,exynos5250-hsi2c";
 596                         reg = <0x12CC0000 0x1000>;
 597                         interrupts = <0 62 0>;
 598                         #address-cells = <1>;
 599                         #size-cells = <0>;
 600                         pinctrl-names = "default";
 601                         pinctrl-0 = <&i2c6_hs_bus>;
 602                         clocks = <&clock CLK_USI2>;
 603                         clock-names = "hsi2c";
 604                         status = "disabled";
 605                 };
 606
 607                 hsi2c_7: i2c@12CD0000 {
 608                         compatible = "samsung,exynos5250-hsi2c";
 609                         reg = <0x12CD0000 0x1000>;
 610                         interrupts = <0 63 0>;
 611                         #address-cells = <1>;
 612                         #size-cells = <0>;
 613                         pinctrl-names = "default";
 614                         pinctrl-0 = <&i2c7_hs_bus>;
 615                         clocks = <&clock CLK_USI3>;
 616                         clock-names = "hsi2c";
 617                         status = "disabled";
 618                 };
 619
 620                 hsi2c_8: i2c@12E00000 {
 621                         compatible = "samsung,exynos5250-hsi2c";
 622                         reg = <0x12E00000 0x1000>;
 623                         interrupts = <0 87 0>;
 624                         #address-cells = <1>;
 625                         #size-cells = <0>;
 626                         pinctrl-names = "default";
 627                         pinctrl-0 = <&i2c8_hs_bus>;
 628                         clocks = <&clock CLK_USI4>;
 629                         clock-names = "hsi2c";
 630                         status = "disabled";
 631                 };
 632
 633                 hsi2c_9: i2c@12E10000 {
 634                         compatible = "samsung,exynos5250-hsi2c";
 635                         reg = <0x12E10000 0x1000>;
 636                         interrupts = <0 88 0>;
 637                         #address-cells = <1>;
 638                         #size-cells = <0>;
 639                         pinctrl-names = "default";
 640                         pinctrl-0 = <&i2c9_hs_bus>;
 641                         clocks = <&clock CLK_USI5>;
 642                         clock-names = "hsi2c";
 643                         status = "disabled";
 644                 };
 645
 646                 hsi2c_10: i2c@12E20000 {
 647                         compatible = "samsung,exynos5250-hsi2c";
 648                         reg = <0x12E20000 0x1000>;
 649                         interrupts = <0 203 0>;
 650                         #address-cells = <1>;
 651                         #size-cells = <0>;
 652                         pinctrl-names = "default";
 653                         pinctrl-0 = <&i2c10_hs_bus>;
 654                         clocks = <&clock CLK_USI6>;
 655                         clock-names = "hsi2c";
 656                         status = "disabled";
 657                 };
 658
 659                 hdmi: hdmi@14530000 {
 660                         compatible = "samsung,exynos5420-hdmi";
 661                         reg = <0x14530000 0x70000>;
 662                         interrupts = <0 95 0>;
 663                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 664                                  <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 665                                  <&clock CLK_MOUT_HDMI>;
 666                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 667                                 "sclk_hdmiphy", "mout_hdmi";
 668                         phy = <&hdmiphy>;
 669                         samsung,syscon-phandle = <&pmu_system_controller>;
 670                         status = "disabled";
 671                         power-domains = <&disp_pd>;
 672                 };
 673
 674                 hdmiphy: hdmiphy@145D0000 {
 675                         reg = <0x145D0000 0x20>;
 676                 };
 677
 678                 mixer: mixer@14450000 {
 679                         compatible = "samsung,exynos5420-mixer";
 680                         reg = <0x14450000 0x10000>;
 681                         interrupts = <0 94 0>;
 682                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 683                                  <&clock CLK_SCLK_HDMI>;
 684                         clock-names = "mixer", "hdmi", "sclk_hdmi";
 685                         power-domains = <&disp_pd>;
 686                         iommus = <&sysmmu_tv>;
 687                 };
 688
 689                 rotator: rotator@11C00000 {
 690                         compatible = "samsung,exynos5250-rotator";
 691                         reg = <0x11C00000 0x64>;
 692                         interrupts = <0 84 0>;
 693                         clocks = <&clock CLK_ROTATOR>;
 694                         clock-names = "rotator";
 695                         iommus = <&sysmmu_rotator>;
 696                 };
 697
 698                 gsc_0: video-scaler@13e00000 {
 699                         compatible = "samsung,exynos5-gsc";
 700                         reg = <0x13e00000 0x1000>;
 701                         interrupts = <0 85 0>;
 702                         clocks = <&clock CLK_GSCL0>;
 703                         clock-names = "gscl";
 704                         power-domains = <&gsc_pd>;
 705                         iommus = <&sysmmu_gscl0>;
 706                 };
 707
 708                 gsc_1: video-scaler@13e10000 {
 709                         compatible = "samsung,exynos5-gsc";
 710                         reg = <0x13e10000 0x1000>;
 711                         interrupts = <0 86 0>;
 712                         clocks = <&clock CLK_GSCL1>;
 713                         clock-names = "gscl";
 714                         power-domains = <&gsc_pd>;
 715                         iommus = <&sysmmu_gscl1>;
 716                 };
 717
 718                 jpeg_0: jpeg@11F50000 {
 719                         compatible = "samsung,exynos5420-jpeg";
 720                         reg = <0x11F50000 0x1000>;
 721                         interrupts = <0 89 0>;
 722                         clock-names = "jpeg";
 723                         clocks = <&clock CLK_JPEG>;
 724                         iommus = <&sysmmu_jpeg0>;
 725                 };
 726
 727                 jpeg_1: jpeg@11F60000 {
 728                         compatible = "samsung,exynos5420-jpeg";
 729                         reg = <0x11F60000 0x1000>;
 730                         interrupts = <0 168 0>;
 731                         clock-names = "jpeg";
 732                         clocks = <&clock CLK_JPEG2>;
 733                         iommus = <&sysmmu_jpeg1>;
 734                 };
 735
 736                 pmu_system_controller: system-controller@10040000 {
 737                         compatible = "samsung,exynos5420-pmu", "syscon";
 738                         reg = <0x10040000 0x5000>;
 739                         clock-names = "clkout16";
 740                         clocks = <&clock CLK_FIN_PLL>;
 741                         #clock-cells = <1>;
 742                         interrupt-controller;
 743                         #interrupt-cells = <3>;
 744                         interrupt-parent = <&gic>;
 745                 };
 746
 747                 tmu_cpu0: tmu@10060000 {
 748                         compatible = "samsung,exynos5420-tmu";
 749                         reg = <0x10060000 0x100>;
 750                         interrupts = <0 65 0>;
 751                         clocks = <&clock CLK_TMU>;
 752                         clock-names = "tmu_apbif";
 753                         #include "exynos4412-tmu-sensor-conf.dtsi"
 754                 };
 755
 756                 tmu_cpu1: tmu@10064000 {
 757                         compatible = "samsung,exynos5420-tmu";
 758                         reg = <0x10064000 0x100>;
 759                         interrupts = <0 183 0>;
 760                         clocks = <&clock CLK_TMU>;
 761                         clock-names = "tmu_apbif";
 762                         #include "exynos4412-tmu-sensor-conf.dtsi"
 763                 };
 764
 765                 tmu_cpu2: tmu@10068000 {
 766                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 767                         reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 768                         interrupts = <0 184 0>;
 769                         clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 770                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 771                         #include "exynos4412-tmu-sensor-conf.dtsi"
 772                 };
 773
 774                 tmu_cpu3: tmu@1006c000 {
 775                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 776                         reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 777                         interrupts = <0 185 0>;
 778                         clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 779                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 780                         #include "exynos4412-tmu-sensor-conf.dtsi"
 781                 };
 782
 783                 tmu_gpu: tmu@100a0000 {
 784                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 785                         reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 786                         interrupts = <0 215 0>;
 787                         clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 788                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 789                         #include "exynos4412-tmu-sensor-conf.dtsi"
 790                 };
 791
 792                 watchdog: watchdog@101D0000 {
 793                         compatible = "samsung,exynos5420-wdt";
 794                         reg = <0x101D0000 0x100>;
 795                         interrupts = <0 42 0>;
 796                         clocks = <&clock CLK_WDT>;
 797                         clock-names = "watchdog";
 798                         samsung,syscon-phandle = <&pmu_system_controller>;
 799                 };
 800
 801                 sss: sss@10830000 {
 802                         compatible = "samsung,exynos4210-secss";
 803                         reg = <0x10830000 0x300>;
 804                         interrupts = <0 112 0>;
 805                         clocks = <&clock CLK_SSS>;
 806                         clock-names = "secss";
 807                 };
 808
 809                 usbdrd3_0: usb3-0 {
 810                         compatible = "samsung,exynos5250-dwusb3";
 811                         clocks = <&clock CLK_USBD300>;
 812                         clock-names = "usbdrd30";
 813                         #address-cells = <1>;
 814                         #size-cells = <1>;
 815                         ranges;
 816
 817                         usbdrd_dwc3_0: dwc3@12000000 {
 818                                 compatible = "snps,dwc3";
 819                                 reg = <0x12000000 0x10000>;
 820                                 interrupts = <0 72 0>;
 821                                 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
 822                                 phy-names = "usb2-phy", "usb3-phy";
 823                         };
 824                 };
 825
 826                 usbdrd_phy0: phy@12100000 {
 827                         compatible = "samsung,exynos5420-usbdrd-phy";
 828                         reg = <0x12100000 0x100>;
 829                         clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 830                         clock-names = "phy", "ref";
 831                         samsung,pmu-syscon = <&pmu_system_controller>;
 832                         #phy-cells = <1>;
 833                 };
 834
 835                 usbdrd3_1: usb3-1 {
 836                         compatible = "samsung,exynos5250-dwusb3";
 837                         clocks = <&clock CLK_USBD301>;
 838                         clock-names = "usbdrd30";
 839                         #address-cells = <1>;
 840                         #size-cells = <1>;
 841                         ranges;
 842
 843                         usbdrd_dwc3_1: dwc3@12400000 {
 844                                 compatible = "snps,dwc3";
 845                                 reg = <0x12400000 0x10000>;
 846                                 interrupts = <0 73 0>;
 847                                 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
 848                                 phy-names = "usb2-phy", "usb3-phy";
 849                         };
 850                 };
 851
 852                 usbdrd_phy1: phy@12500000 {
 853                         compatible = "samsung,exynos5420-usbdrd-phy";
 854                         reg = <0x12500000 0x100>;
 855                         clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 856                         clock-names = "phy", "ref";
 857                         samsung,pmu-syscon = <&pmu_system_controller>;
 858                         #phy-cells = <1>;
 859                 };
 860
 861                 usbhost2: usb@12110000 {
 862                         compatible = "samsung,exynos4210-ehci";
 863                         reg = <0x12110000 0x100>;
 864                         interrupts = <0 71 0>;
 865
 866                         clocks = <&clock CLK_USBH20>;
 867                         clock-names = "usbhost";
 868                         #address-cells = <1>;
 869                         #size-cells = <0>;
 870                         port@0 {
 871                                 reg = <0>;
 872                                 phys = <&usb2_phy 1>;
 873                         };
 874                 };
 875
 876                 usbhost1: usb@12120000 {
 877                         compatible = "samsung,exynos4210-ohci";
 878                         reg = <0x12120000 0x100>;
 879                         interrupts = <0 71 0>;
 880
 881                         clocks = <&clock CLK_USBH20>;
 882                         clock-names = "usbhost";
 883                         #address-cells = <1>;
 884                         #size-cells = <0>;
 885                         port@0 {
 886                                 reg = <0>;
 887                                 phys = <&usb2_phy 1>;
 888                         };
 889                 };
 890
 891                 usb2_phy: phy@12130000 {
 892                         compatible = "samsung,exynos5250-usb2-phy";
 893                         reg = <0x12130000 0x100>;
 894                         clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
 895                         clock-names = "phy", "ref";
 896                         #phy-cells = <1>;
 897                         samsung,sysreg-phandle = <&sysreg_system_controller>;
 898                         samsung,pmureg-phandle = <&pmu_system_controller>;
 899                 };
 900
 901                 sysmmu_g2dr: sysmmu@0x10A60000 {
 902                         compatible = "samsung,exynos-sysmmu";
 903                         reg = <0x10A60000 0x1000>;
 904                         interrupt-parent = <&combiner>;
 905                         interrupts = <24 5>;
 906                         clock-names = "sysmmu", "master";
 907                         clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 908                         #iommu-cells = <0>;
 909                 };
 910
 911                 sysmmu_g2dw: sysmmu@0x10A70000 {
 912                         compatible = "samsung,exynos-sysmmu";
 913                         reg = <0x10A70000 0x1000>;
 914                         interrupt-parent = <&combiner>;
 915                         interrupts = <22 2>;
 916                         clock-names = "sysmmu", "master";
 917                         clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 918                         #iommu-cells = <0>;
 919                 };
 920
 921                 sysmmu_tv: sysmmu@0x14650000 {
 922                         compatible = "samsung,exynos-sysmmu";
 923                         reg = <0x14650000 0x1000>;
 924                         interrupt-parent = <&combiner>;
 925                         interrupts = <7 4>;
 926                         clock-names = "sysmmu", "master";
 927                         clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
 928                         power-domains = <&disp_pd>;
 929                         #iommu-cells = <0>;
 930                 };
 931
 932                 sysmmu_gscl0: sysmmu@0x13E80000 {
 933                         compatible = "samsung,exynos-sysmmu";
 934                         reg = <0x13E80000 0x1000>;
 935                         interrupt-parent = <&combiner>;
 936                         interrupts = <2 0>;
 937                         clock-names = "sysmmu", "master";
 938                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
 939                         power-domains = <&gsc_pd>;
 940                         #iommu-cells = <0>;
 941                 };
 942
 943                 sysmmu_gscl1: sysmmu@0x13E90000 {
 944                         compatible = "samsung,exynos-sysmmu";
 945                         reg = <0x13E90000 0x1000>;
 946                         interrupt-parent = <&combiner>;
 947                         interrupts = <2 2>;
 948                         clock-names = "sysmmu", "master";
 949                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
 950                         power-domains = <&gsc_pd>;
 951                         #iommu-cells = <0>;
 952                 };
 953
 954                 sysmmu_scaler0r: sysmmu@0x12880000 {
 955                         compatible = "samsung,exynos-sysmmu";
 956                         reg = <0x12880000 0x1000>;
 957                         interrupt-parent = <&combiner>;
 958                         interrupts = <22 4>;
 959                         clock-names = "sysmmu", "master";
 960                         clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
 961                         #iommu-cells = <0>;
 962                 };
 963
 964                 sysmmu_scaler1r: sysmmu@0x12890000 {
 965                         compatible = "samsung,exynos-sysmmu";
 966                         reg = <0x12890000 0x1000>;
 967                         interrupts = <0 186 0>;
 968                         clock-names = "sysmmu", "master";
 969                         clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
 970                         #iommu-cells = <0>;
 971                 };
 972
 973                 sysmmu_scaler2r: sysmmu@0x128A0000 {
 974                         compatible = "samsung,exynos-sysmmu";
 975                         reg = <0x128A0000 0x1000>;
 976                         interrupts = <0 188 0>;
 977                         clock-names = "sysmmu", "master";
 978                         clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
 979                         #iommu-cells = <0>;
 980                 };
 981
 982                 sysmmu_scaler0w: sysmmu@0x128C0000 {
 983                         compatible = "samsung,exynos-sysmmu";
 984                         reg = <0x128C0000 0x1000>;
 985                         interrupt-parent = <&combiner>;
 986                         interrupts = <27 2>;
 987                         clock-names = "sysmmu", "master";
 988                         clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
 989                         #iommu-cells = <0>;
 990                 };
 991
 992                 sysmmu_scaler1w: sysmmu@0x128D0000 {
 993                         compatible = "samsung,exynos-sysmmu";
 994                         reg = <0x128D0000 0x1000>;
 995                         interrupt-parent = <&combiner>;
 996                         interrupts = <22 6>;
 997                         clock-names = "sysmmu", "master";
 998                         clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
 999                         #iommu-cells = <0>;
1000                 };
1001
1002                 sysmmu_scaler2w: sysmmu@0x128E0000 {
1003                         compatible = "samsung,exynos-sysmmu";
1004                         reg = <0x128E0000 0x1000>;
1005                         interrupt-parent = <&combiner>;
1006                         interrupts = <19 6>;
1007                         clock-names = "sysmmu", "master";
1008                         clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1009                         #iommu-cells = <0>;
1010                 };
1011
1012                 sysmmu_rotator: sysmmu@0x11D40000 {
1013                         compatible = "samsung,exynos-sysmmu";
1014                         reg = <0x11D40000 0x1000>;
1015                         interrupt-parent = <&combiner>;
1016                         interrupts = <4 0>;
1017                         clock-names = "sysmmu", "master";
1018                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1019                         #iommu-cells = <0>;
1020                 };
1021
1022                 sysmmu_jpeg0: sysmmu@0x11F10000 {
1023                         compatible = "samsung,exynos-sysmmu";
1024                         reg = <0x11F10000 0x1000>;
1025                         interrupt-parent = <&combiner>;
1026                         interrupts = <4 2>;
1027                         clock-names = "sysmmu", "master";
1028                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1029                         #iommu-cells = <0>;
1030                 };
1031
1032                 sysmmu_jpeg1: sysmmu@0x11F20000 {
1033                         compatible = "samsung,exynos-sysmmu";
1034                         reg = <0x11F20000 0x1000>;
1035                         interrupts = <0 169 0>;
1036                         clock-names = "sysmmu", "master";
1037                         clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1038                         #iommu-cells = <0>;
1039                 };
1040
1041                 sysmmu_mfc_l: sysmmu@0x11200000 {
1042                         compatible = "samsung,exynos-sysmmu";
1043                         reg = <0x11200000 0x1000>;
1044                         interrupt-parent = <&combiner>;
1045                         interrupts = <6 2>;
1046                         clock-names = "sysmmu", "master";
1047                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1048                         power-domains = <&mfc_pd>;
1049                         #iommu-cells = <0>;
1050                 };
1051
1052                 sysmmu_mfc_r: sysmmu@0x11210000 {
1053                         compatible = "samsung,exynos-sysmmu";
1054                         reg = <0x11210000 0x1000>;
1055                         interrupt-parent = <&combiner>;
1056                         interrupts = <8 5>;
1057                         clock-names = "sysmmu", "master";
1058                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1059                         power-domains = <&mfc_pd>;
1060                         #iommu-cells = <0>;
1061                 };
1062
1063                 sysmmu_fimd1_0: sysmmu@0x14640000 {
1064                         compatible = "samsung,exynos-sysmmu";
1065                         reg = <0x14640000 0x1000>;
1066                         interrupt-parent = <&combiner>;
1067                         interrupts = <3 2>;
1068                         clock-names = "sysmmu", "master";
1069                         clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1070                         power-domains = <&disp_pd>;
1071                         #iommu-cells = <0>;
1072                 };
1073
1074                 sysmmu_fimd1_1: sysmmu@0x14680000 {
1075                         compatible = "samsung,exynos-sysmmu";
1076                         reg = <0x14680000 0x1000>;
1077                         interrupt-parent = <&combiner>;
1078                         interrupts = <3 0>;
1079                         clock-names = "sysmmu", "master";
1080                         clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1081                         power-domains = <&disp_pd>;
1082                         #iommu-cells = <0>;
1083                 };
1084
1085                 bus_wcore: bus_wcore {
1086                         compatible = "samsung,exynos-bus";
1087                         clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
1088                         clock-names = "bus";
1089                         operating-points-v2 = <&bus_wcore_opp_table>;
1090                         status = "disabled";
1091                 };
1092
1093                 bus_noc: bus_noc {
1094                         compatible = "samsung,exynos-bus";
1095                         clocks = <&clock CLK_DOUT_ACLK100_NOC>;
1096                         clock-names = "bus";
1097                         operating-points-v2 = <&bus_noc_opp_table>;
1098                         status = "disabled";
1099                 };
1100
1101                 bus_fsys_apb: bus_fsys_apb {
1102                         compatible = "samsung,exynos-bus";
1103                         clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
1104                         clock-names = "bus";
1105                         operating-points-v2 = <&bus_fsys_apb_opp_table>;
1106                         status = "disabled";
1107                 };
1108
1109                 bus_fsys: bus_fsys {
1110                         compatible = "samsung,exynos-bus";
1111                         clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
1112                         clock-names = "bus";
1113                         operating-points-v2 = <&bus_fsys_apb_opp_table>;
1114                         status = "disabled";
1115                 };
1116
1117                 bus_fsys2: bus_fsys2 {
1118                         compatible = "samsung,exynos-bus";
1119                         clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
1120                         clock-names = "bus";
1121                         operating-points-v2 = <&bus_fsys2_opp_table>;
1122                         status = "disabled";
1123                 };
1124
1125                 bus_mfc: bus_mfc {
1126                         compatible = "samsung,exynos-bus";
1127                         clocks = <&clock CLK_DOUT_ACLK333>;
1128                         clock-names = "bus";
1129                         operating-points-v2 = <&bus_mfc_opp_table>;
1130                         status = "disabled";
1131                 };
1132
1133                 bus_gen: bus_gen {
1134                         compatible = "samsung,exynos-bus";
1135                         clocks = <&clock CLK_DOUT_ACLK266>;
1136                         clock-names = "bus";
1137                         operating-points-v2 = <&bus_gen_opp_table>;
1138                         status = "disabled";
1139                 };
1140
1141                 bus_peri: bus_peri {
1142                         compatible = "samsung,exynos-bus";
1143                         clocks = <&clock CLK_DOUT_ACLK66>;
1144                         clock-names = "bus";
1145                         operating-points-v2 = <&bus_peri_opp_table>;
1146                         status = "disabled";
1147                 };
1148
1149                 bus_g2d: bus_g2d {
1150                         compatible = "samsung,exynos-bus";
1151                         clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1152                         clock-names = "bus";
1153                         operating-points-v2 = <&bus_g2d_opp_table>;
1154                         status = "disabled";
1155                 };
1156
1157                 bus_g2d_acp: bus_g2d_acp {
1158                         compatible = "samsung,exynos-bus";
1159                         clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1160                         clock-names = "bus";
1161                         operating-points-v2 = <&bus_g2d_acp_opp_table>;
1162                         status = "disabled";
1163                 };
1164
1165                 bus_jpeg: bus_jpeg {
1166                         compatible = "samsung,exynos-bus";
1167                         clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1168                         clock-names = "bus";
1169                         operating-points-v2 = <&bus_jpeg_opp_table>;
1170                         status = "disabled";
1171                 };
1172
1173                 bus_jpeg_apb: bus_jpeg_apb {
1174                         compatible = "samsung,exynos-bus";
1175                         clocks = <&clock CLK_DOUT_ACLK166>;
1176                         clock-names = "bus";
1177                         operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1178                         status = "disabled";
1179                 };
1180
1181                 bus_disp1_fimd: bus_disp1_fimd {
1182                         compatible = "samsung,exynos-bus";
1183                         clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1184                         clock-names = "bus";
1185                         operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1186                         status = "disabled";
1187                 };
1188
1189                 bus_disp1: bus_disp1 {
1190                         compatible = "samsung,exynos-bus";
1191                         clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1192                         clock-names = "bus";
1193                         operating-points-v2 = <&bus_disp1_opp_table>;
1194                         status = "disabled";
1195                 };
1196
1197                 bus_gscl_scaler: bus_gscl_scaler {
1198                         compatible = "samsung,exynos-bus";
1199                         clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1200                         clock-names = "bus";
1201                         operating-points-v2 = <&bus_gscl_opp_table>;
1202                         status = "disabled";
1203                 };
1204
1205                 bus_mscl: bus_mscl {
1206                         compatible = "samsung,exynos-bus";
1207                         clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1208                         clock-names = "bus";
1209                         operating-points-v2 = <&bus_mscl_opp_table>;
1210                         status = "disabled";
1211                 };
1212
1213                 bus_wcore_opp_table: opp_table2 {
1214                         compatible = "operating-points-v2";
1215
1216                         opp00 {
1217                                 opp-hz = /bits/ 64 <84000000>;
1218                                 opp-microvolt = <925000>;
1219                         };
1220                         opp01 {
1221                                 opp-hz = /bits/ 64 <111000000>;
1222                                 opp-microvolt = <950000>;
1223                         };
1224                         opp02 {
1225                                 opp-hz = /bits/ 64 <222000000>;
1226                                 opp-microvolt = <950000>;
1227                         };
1228                         opp03 {
1229                                 opp-hz = /bits/ 64 <333000000>;
1230                                 opp-microvolt = <950000>;
1231                         };
1232                         opp04 {
1233                                 opp-hz = /bits/ 64 <400000000>;
1234                                 opp-microvolt = <987500>;
1235                         };
1236                 };
1237
1238                 bus_noc_opp_table: opp_table3 {
1239                         compatible = "operating-points-v2";
1240
1241                         opp00 {
1242                                 opp-hz = /bits/ 64 <67000000>;
1243                         };
1244                         opp01 {
1245                                 opp-hz = /bits/ 64 <75000000>;
1246                         };
1247                         opp02 {
1248                                 opp-hz = /bits/ 64 <86000000>;
1249                         };
1250                         opp03 {
1251                                 opp-hz = /bits/ 64 <100000000>;
1252                         };
1253                 };
1254
1255                 bus_fsys_apb_opp_table: opp_table4 {
1256                         compatible = "operating-points-v2";
1257                         opp-shared;
1258
1259                         opp00 {
1260                                 opp-hz = /bits/ 64 <100000000>;
1261                         };
1262                         opp01 {
1263                                 opp-hz = /bits/ 64 <200000000>;
1264                         };
1265                 };
1266
1267                 bus_fsys2_opp_table: opp_table5 {
1268                         compatible = "operating-points-v2";
1269
1270                         opp00 {
1271                                 opp-hz = /bits/ 64 <75000000>;
1272                         };
1273                         opp01 {
1274                                 opp-hz = /bits/ 64 <100000000>;
1275                         };
1276                         opp02 {
1277                                 opp-hz = /bits/ 64 <150000000>;
1278                         };
1279                 };
1280
1281                 bus_mfc_opp_table: opp_table6 {
1282                         compatible = "operating-points-v2";
1283
1284                         opp00 {
1285                                 opp-hz = /bits/ 64 <96000000>;
1286                         };
1287                         opp01 {
1288                                 opp-hz = /bits/ 64 <111000000>;
1289                         };
1290                         opp02 {
1291                                 opp-hz = /bits/ 64 <167000000>;
1292                         };
1293                         opp03 {
1294                                 opp-hz = /bits/ 64 <222000000>;
1295                         };
1296                         opp04 {
1297                                 opp-hz = /bits/ 64 <333000000>;
1298                         };
1299                 };
1300
1301                 bus_gen_opp_table: opp_table7 {
1302                         compatible = "operating-points-v2";
1303
1304                         opp00 {
1305                                 opp-hz = /bits/ 64 <89000000>;
1306                         };
1307                         opp01 {
1308                                 opp-hz = /bits/ 64 <133000000>;
1309                         };
1310                         opp02 {
1311                                 opp-hz = /bits/ 64 <178000000>;
1312                         };
1313                         opp03 {
1314                                 opp-hz = /bits/ 64 <267000000>;
1315                         };
1316                 };
1317
1318                 bus_peri_opp_table: opp_table8 {
1319                         compatible = "operating-points-v2";
1320
1321                         opp00 {
1322                                 opp-hz = /bits/ 64 <67000000>;
1323                         };
1324                 };
1325
1326                 bus_g2d_opp_table: opp_table9 {
1327                         compatible = "operating-points-v2";
1328
1329                         opp00 {
1330                                 opp-hz = /bits/ 64 <84000000>;
1331                         };
1332                         opp01 {
1333                                 opp-hz = /bits/ 64 <167000000>;
1334                         };
1335                         opp02 {
1336                                 opp-hz = /bits/ 64 <222000000>;
1337                         };
1338                         opp03 {
1339                                 opp-hz = /bits/ 64 <300000000>;
1340                         };
1341                         opp04 {
1342                                 opp-hz = /bits/ 64 <333000000>;
1343                         };
1344                 };
1345
1346                 bus_g2d_acp_opp_table: opp_table10 {
1347                         compatible = "operating-points-v2";
1348
1349                         opp00 {
1350                                 opp-hz = /bits/ 64 <67000000>;
1351                         };
1352                         opp01 {
1353                                 opp-hz = /bits/ 64 <133000000>;
1354                         };
1355                         opp02 {
1356                                 opp-hz = /bits/ 64 <178000000>;
1357                         };
1358                         opp03 {
1359                                 opp-hz = /bits/ 64 <267000000>;
1360                         };
1361                 };
1362
1363                 bus_jpeg_opp_table: opp_table11 {
1364                         compatible = "operating-points-v2";
1365
1366                         opp00 {
1367                                 opp-hz = /bits/ 64 <75000000>;
1368                         };
1369                         opp01 {
1370                                 opp-hz = /bits/ 64 <150000000>;
1371                         };
1372                         opp02 {
1373                                 opp-hz = /bits/ 64 <200000000>;
1374                         };
1375                         opp03 {
1376                                 opp-hz = /bits/ 64 <300000000>;
1377                         };
1378                 };
1379
1380                 bus_jpeg_apb_opp_table: opp_table12 {
1381                         compatible = "operating-points-v2";
1382
1383                         opp00 {
1384                                 opp-hz = /bits/ 64 <84000000>;
1385                         };
1386                         opp01 {
1387                                 opp-hz = /bits/ 64 <111000000>;
1388                         };
1389                         opp02 {
1390                                 opp-hz = /bits/ 64 <134000000>;
1391                         };
1392                         opp03 {
1393                                 opp-hz = /bits/ 64 <167000000>;
1394                         };
1395                 };
1396
1397                 bus_disp1_fimd_opp_table: opp_table13 {
1398                         compatible = "operating-points-v2";
1399
1400                         opp00 {
1401                                 opp-hz = /bits/ 64 <120000000>;
1402                         };
1403                         opp01 {
1404                                 opp-hz = /bits/ 64 <200000000>;
1405                         };
1406                 };
1407
1408                 bus_disp1_opp_table: opp_table14 {
1409                         compatible = "operating-points-v2";
1410
1411                         opp00 {
1412                                 opp-hz = /bits/ 64 <120000000>;
1413                         };
1414                         opp01 {
1415                                 opp-hz = /bits/ 64 <200000000>;
1416                         };
1417                         opp02 {
1418                                 opp-hz = /bits/ 64 <300000000>;
1419                         };
1420                 };
1421
1422                 bus_gscl_opp_table: opp_table15 {
1423                         compatible = "operating-points-v2";
1424
1425                         opp00 {
1426                                 opp-hz = /bits/ 64 <150000000>;
1427                         };
1428                         opp01 {
1429                                 opp-hz = /bits/ 64 <200000000>;
1430                         };
1431                         opp02 {
1432                                 opp-hz = /bits/ 64 <300000000>;
1433                         };
1434                 };
1435
1436                 bus_mscl_opp_table: opp_table16 {
1437                         compatible = "operating-points-v2";
1438
1439                         opp00 {
1440                                 opp-hz = /bits/ 64 <84000000>;
1441                         };
1442                         opp01 {
1443                                 opp-hz = /bits/ 64 <167000000>;
1444                         };
1445                         opp02 {
1446                                 opp-hz = /bits/ 64 <222000000>;
1447                         };
1448                         opp03 {
1449                                 opp-hz = /bits/ 64 <333000000>;
1450                         };
1451                         opp04 {
1452                                 opp-hz = /bits/ 64 <400000000>;
1453                         };
1454                 };
1455         };
1456
1457         thermal-zones {
1458                 cpu0_thermal: cpu0-thermal {
1459                         thermal-sensors = <&tmu_cpu0>;
1460                         #include "exynos5420-trip-points.dtsi"
1461                 };
1462                 cpu1_thermal: cpu1-thermal {
1463                        thermal-sensors = <&tmu_cpu1>;
1464                        #include "exynos5420-trip-points.dtsi"
1465                 };
1466                 cpu2_thermal: cpu2-thermal {
1467                        thermal-sensors = <&tmu_cpu2>;
1468                        #include "exynos5420-trip-points.dtsi"
1469                 };
1470                 cpu3_thermal: cpu3-thermal {
1471                        thermal-sensors = <&tmu_cpu3>;
1472                        #include "exynos5420-trip-points.dtsi"
1473                 };
1474                 gpu_thermal: gpu-thermal {
1475                        thermal-sensors = <&tmu_gpu>;
1476                        #include "exynos5420-trip-points.dtsi"
1477                 };
1478         };
1479 };
1480
1481 &dp {
1482         clocks = <&clock CLK_DP1>;
1483         clock-names = "dp";
1484         phys = <&dp_phy>;
1485         phy-names = "dp";
1486         power-domains = <&disp_pd>;
1487 };
1488
1489 &fimd {
1490         compatible = "samsung,exynos5420-fimd";
1491         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1492         clock-names = "sclk_fimd", "fimd";
1493         power-domains = <&disp_pd>;
1494         iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1495         iommu-names = "m0", "m1";
1496 };
1497
1498 &i2c_0 {
1499         clocks = <&clock CLK_I2C0>;
1500         clock-names = "i2c";
1501         pinctrl-names = "default";
1502         pinctrl-0 = <&i2c0_bus>;
1503 };
1504
1505 &i2c_1 {
1506         clocks = <&clock CLK_I2C1>;
1507         clock-names = "i2c";
1508         pinctrl-names = "default";
1509         pinctrl-0 = <&i2c1_bus>;
1510 };
1511
1512 &i2c_2 {
1513         clocks = <&clock CLK_I2C2>;
1514         clock-names = "i2c";
1515         pinctrl-names = "default";
1516         pinctrl-0 = <&i2c2_bus>;
1517 };
1518
1519 &i2c_3 {
1520         clocks = <&clock CLK_I2C3>;
1521         clock-names = "i2c";
1522         pinctrl-names = "default";
1523         pinctrl-0 = <&i2c3_bus>;
1524 };
1525
1526 &mct {
1527         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1528         clock-names = "fin_pll", "mct";
1529 };
1530
1531 &pwm {
1532         clocks = <&clock CLK_PWM>;
1533         clock-names = "timers";
1534 };
1535
1536 &rtc {
1537         clocks = <&clock CLK_RTC>;
1538         clock-names = "rtc";
1539         interrupt-parent = <&pmu_system_controller>;
1540         status = "disabled";
1541 };
1542
1543 &serial_0 {
1544         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1545         clock-names = "uart", "clk_uart_baud0";
1546 };
1547
1548 &serial_1 {
1549         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1550         clock-names = "uart", "clk_uart_baud0";
1551 };
1552
1553 &serial_2 {
1554         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1555         clock-names = "uart", "clk_uart_baud0";
1556 };
1557
1558 &serial_3 {
1559         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1560         clock-names = "uart", "clk_uart_baud0";
1561 };
1562
1563 #include "exynos5420-pinctrl.dtsi"