arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include "exynos5.dtsi"
  17 #include "exynos5420-pinctrl.dtsi"
  18
  19 #include <dt-bindings/clk/exynos-audss-clk.h>
  20
  21 / {
  22         compatible = "samsung,exynos5420";
  23
  24         aliases {
  25                 pinctrl0 = &pinctrl_0;
  26                 pinctrl1 = &pinctrl_1;
  27                 pinctrl2 = &pinctrl_2;
  28                 pinctrl3 = &pinctrl_3;
  29                 pinctrl4 = &pinctrl_4;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 cpu0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a15";
  39                         reg = <0x0>;
  40                         clock-frequency = <1800000000>;
  41                 };
  42
  43                 cpu1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a15";
  46                         reg = <0x1>;
  47                         clock-frequency = <1800000000>;
  48                 };
  49
  50                 cpu2: cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <0x2>;
  54                         clock-frequency = <1800000000>;
  55                 };
  56
  57                 cpu3: cpu@3 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a15";
  60                         reg = <0x3>;
  61                         clock-frequency = <1800000000>;
  62                 };
  63         };
  64
  65         clock: clock-controller@10010000 {
  66                 compatible = "samsung,exynos5420-clock";
  67                 reg = <0x10010000 0x30000>;
  68                 #clock-cells = <1>;
  69         };
  70
  71         clock_audss: audss-clock-controller@3810000 {
  72                 compatible = "samsung,exynos5420-audss-clock";
  73                 reg = <0x03810000 0x0C>;
  74                 #clock-cells = <1>;
  75                 clocks = <&clock 148>;
  76                 clock-names = "sclk_audio";
  77         };
  78
  79         codec@11000000 {
  80                 compatible = "samsung,mfc-v7";
  81                 reg = <0x11000000 0x10000>;
  82                 interrupts = <0 96 0>;
  83                 clocks = <&clock 401>;
  84                 clock-names = "mfc";
  85         };
  86
  87         mct@101C0000 {
  88                 compatible = "samsung,exynos4210-mct";
  89                 reg = <0x101C0000 0x800>;
  90                 interrupt-controller;
  91                 #interrups-cells = <1>;
  92                 interrupt-parent = <&mct_map>;
  93                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
  94                 clocks = <&clock 1>, <&clock 315>;
  95                 clock-names = "fin_pll", "mct";
  96
  97                 mct_map: mct-map {
  98                         #interrupt-cells = <1>;
  99                         #address-cells = <0>;
 100                         #size-cells = <0>;
 101                         interrupt-map = <0 &combiner 23 3>,
 102                                         <1 &combiner 23 4>,
 103                                         <2 &combiner 25 2>,
 104                                         <3 &combiner 25 3>,
 105                                         <4 &gic 0 120 0>,
 106                                         <5 &gic 0 121 0>,
 107                                         <6 &gic 0 122 0>,
 108                                         <7 &gic 0 123 0>;
 109                 };
 110         };
 111
 112         gsc_pd: power-domain@10044000 {
 113                 compatible = "samsung,exynos4210-pd";
 114                 reg = <0x10044000 0x20>;
 115         };
 116
 117         isp_pd: power-domain@10044020 {
 118                 compatible = "samsung,exynos4210-pd";
 119                 reg = <0x10044020 0x20>;
 120         };
 121
 122         mfc_pd: power-domain@10044060 {
 123                 compatible = "samsung,exynos4210-pd";
 124                 reg = <0x10044060 0x20>;
 125         };
 126
 127         disp_pd: power-domain@100440C0 {
 128                 compatible = "samsung,exynos4210-pd";
 129                 reg = <0x100440C0 0x20>;
 130         };
 131
 132         mau_pd: power-domain@100440E0 {
 133                 compatible = "samsung,exynos4210-pd";
 134                 reg = <0x100440E0 0x20>;
 135         };
 136
 137         g2d_pd: power-domain@10044100 {
 138                 compatible = "samsung,exynos4210-pd";
 139                 reg = <0x10044100 0x20>;
 140         };
 141
 142         msc_pd: power-domain@10044120 {
 143                 compatible = "samsung,exynos4210-pd";
 144                 reg = <0x10044120 0x20>;
 145         };
 146
 147         pinctrl_0: pinctrl@13400000 {
 148                 compatible = "samsung,exynos5420-pinctrl";
 149                 reg = <0x13400000 0x1000>;
 150                 interrupts = <0 45 0>;
 151
 152                 wakeup-interrupt-controller {
 153                         compatible = "samsung,exynos4210-wakeup-eint";
 154                         interrupt-parent = <&gic>;
 155                         interrupts = <0 32 0>;
 156                 };
 157         };
 158
 159         pinctrl_1: pinctrl@13410000 {
 160                 compatible = "samsung,exynos5420-pinctrl";
 161                 reg = <0x13410000 0x1000>;
 162                 interrupts = <0 78 0>;
 163         };
 164
 165         pinctrl_2: pinctrl@14000000 {
 166                 compatible = "samsung,exynos5420-pinctrl";
 167                 reg = <0x14000000 0x1000>;
 168                 interrupts = <0 46 0>;
 169         };
 170
 171         pinctrl_3: pinctrl@14010000 {
 172                 compatible = "samsung,exynos5420-pinctrl";
 173                 reg = <0x14010000 0x1000>;
 174                 interrupts = <0 50 0>;
 175         };
 176
 177         pinctrl_4: pinctrl@03860000 {
 178                 compatible = "samsung,exynos5420-pinctrl";
 179                 reg = <0x03860000 0x1000>;
 180                 interrupts = <0 47 0>;
 181         };
 182
 183         rtc@101E0000 {
 184                 clocks = <&clock 317>;
 185                 clock-names = "rtc";
 186                 status = "okay";
 187         };
 188
 189         serial@12C00000 {
 190                 clocks = <&clock 257>, <&clock 128>;
 191                 clock-names = "uart", "clk_uart_baud0";
 192         };
 193
 194         serial@12C10000 {
 195                 clocks = <&clock 258>, <&clock 129>;
 196                 clock-names = "uart", "clk_uart_baud0";
 197         };
 198
 199         serial@12C20000 {
 200                 clocks = <&clock 259>, <&clock 130>;
 201                 clock-names = "uart", "clk_uart_baud0";
 202         };
 203
 204         serial@12C30000 {
 205                 clocks = <&clock 260>, <&clock 131>;
 206                 clock-names = "uart", "clk_uart_baud0";
 207         };
 208
 209         dp_phy: video-phy@10040728 {
 210                 compatible = "samsung,exynos5250-dp-video-phy";
 211                 reg = <0x10040728 4>;
 212                 #phy-cells = <0>;
 213         };
 214
 215         dp-controller@145B0000 {
 216                 clocks = <&clock 412>;
 217                 clock-names = "dp";
 218                 phys = <&dp_phy>;
 219                 phy-names = "dp";
 220         };
 221
 222         fimd@14400000 {
 223                 samsung,power-domain = <&disp_pd>;
 224                 clocks = <&clock 147>, <&clock 421>;
 225                 clock-names = "sclk_fimd", "fimd";
 226         };
 227
 228         adc: adc@12D10000 {
 229                 compatible = "samsung,exynos-adc-v2";
 230                 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
 231                 interrupts = <0 106 0>;
 232                 clocks = <&clock 270>;
 233                 clock-names = "adc";
 234                 #io-channel-cells = <1>;
 235                 io-channel-ranges;
 236                 status = "disabled";
 237         };
 238 };