2 * SAMSUNG EXYNOS5420 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include "exynos5.dtsi"
17 #include "exynos5420-pinctrl.dtsi"
19 #include <dt-bindings/clk/exynos-audss-clk.h>
22 compatible = "samsung,exynos5420";
28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
30 pinctrl2 = &pinctrl_2;
31 pinctrl3 = &pinctrl_3;
32 pinctrl4 = &pinctrl_4;
57 compatible = "arm,cortex-a15";
59 clock-frequency = <1800000000>;
64 compatible = "arm,cortex-a15";
66 clock-frequency = <1800000000>;
71 compatible = "arm,cortex-a15";
73 clock-frequency = <1800000000>;
78 compatible = "arm,cortex-a15";
80 clock-frequency = <1800000000>;
85 compatible = "arm,cortex-a7";
87 clock-frequency = <1000000000>;
92 compatible = "arm,cortex-a7";
94 clock-frequency = <1000000000>;
99 compatible = "arm,cortex-a7";
101 clock-frequency = <1000000000>;
106 compatible = "arm,cortex-a7";
108 clock-frequency = <1000000000>;
112 clock: clock-controller@10010000 {
113 compatible = "samsung,exynos5420-clock";
114 reg = <0x10010000 0x30000>;
118 clock_audss: audss-clock-controller@3810000 {
119 compatible = "samsung,exynos5420-audss-clock";
120 reg = <0x03810000 0x0C>;
122 clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;
123 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
127 compatible = "samsung,mfc-v7";
128 reg = <0x11000000 0x10000>;
129 interrupts = <0 96 0>;
130 clocks = <&clock 401>;
134 mmc_0: mmc@12200000 {
135 compatible = "samsung,exynos5420-dw-mshc-smu";
136 interrupts = <0 75 0>;
137 #address-cells = <1>;
139 reg = <0x12200000 0x2000>;
140 clocks = <&clock 351>, <&clock 132>;
141 clock-names = "biu", "ciu";
146 mmc_1: mmc@12210000 {
147 compatible = "samsung,exynos5420-dw-mshc-smu";
148 interrupts = <0 76 0>;
149 #address-cells = <1>;
151 reg = <0x12210000 0x2000>;
152 clocks = <&clock 352>, <&clock 133>;
153 clock-names = "biu", "ciu";
158 mmc_2: mmc@12220000 {
159 compatible = "samsung,exynos5420-dw-mshc";
160 interrupts = <0 77 0>;
161 #address-cells = <1>;
163 reg = <0x12220000 0x1000>;
164 clocks = <&clock 353>, <&clock 134>;
165 clock-names = "biu", "ciu";
171 compatible = "samsung,exynos4210-mct";
172 reg = <0x101C0000 0x800>;
173 interrupt-controller;
174 #interrups-cells = <1>;
175 interrupt-parent = <&mct_map>;
176 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
177 <8>, <9>, <10>, <11>;
178 clocks = <&clock 1>, <&clock 315>;
179 clock-names = "fin_pll", "mct";
182 #interrupt-cells = <1>;
183 #address-cells = <0>;
185 interrupt-map = <0 &combiner 23 3>,
200 gsc_pd: power-domain@10044000 {
201 compatible = "samsung,exynos4210-pd";
202 reg = <0x10044000 0x20>;
205 isp_pd: power-domain@10044020 {
206 compatible = "samsung,exynos4210-pd";
207 reg = <0x10044020 0x20>;
210 mfc_pd: power-domain@10044060 {
211 compatible = "samsung,exynos4210-pd";
212 reg = <0x10044060 0x20>;
215 disp_pd: power-domain@100440C0 {
216 compatible = "samsung,exynos4210-pd";
217 reg = <0x100440C0 0x20>;
220 mau_pd: power-domain@100440E0 {
221 compatible = "samsung,exynos4210-pd";
222 reg = <0x100440E0 0x20>;
225 g2d_pd: power-domain@10044100 {
226 compatible = "samsung,exynos4210-pd";
227 reg = <0x10044100 0x20>;
230 msc_pd: power-domain@10044120 {
231 compatible = "samsung,exynos4210-pd";
232 reg = <0x10044120 0x20>;
235 pinctrl_0: pinctrl@13400000 {
236 compatible = "samsung,exynos5420-pinctrl";
237 reg = <0x13400000 0x1000>;
238 interrupts = <0 45 0>;
240 wakeup-interrupt-controller {
241 compatible = "samsung,exynos4210-wakeup-eint";
242 interrupt-parent = <&gic>;
243 interrupts = <0 32 0>;
247 pinctrl_1: pinctrl@13410000 {
248 compatible = "samsung,exynos5420-pinctrl";
249 reg = <0x13410000 0x1000>;
250 interrupts = <0 78 0>;
253 pinctrl_2: pinctrl@14000000 {
254 compatible = "samsung,exynos5420-pinctrl";
255 reg = <0x14000000 0x1000>;
256 interrupts = <0 46 0>;
259 pinctrl_3: pinctrl@14010000 {
260 compatible = "samsung,exynos5420-pinctrl";
261 reg = <0x14010000 0x1000>;
262 interrupts = <0 50 0>;
265 pinctrl_4: pinctrl@03860000 {
266 compatible = "samsung,exynos5420-pinctrl";
267 reg = <0x03860000 0x1000>;
268 interrupts = <0 47 0>;
272 clocks = <&clock 317>;
278 #address-cells = <1>;
280 compatible = "arm,amba-bus";
281 interrupt-parent = <&gic>;
284 pdma0: pdma@121A0000 {
285 compatible = "arm,pl330", "arm,primecell";
286 reg = <0x121A0000 0x1000>;
287 interrupts = <0 34 0>;
288 clocks = <&clock 362>;
289 clock-names = "apb_pclk";
292 #dma-requests = <32>;
295 pdma1: pdma@121B0000 {
296 compatible = "arm,pl330", "arm,primecell";
297 reg = <0x121B0000 0x1000>;
298 interrupts = <0 35 0>;
299 clocks = <&clock 363>;
300 clock-names = "apb_pclk";
303 #dma-requests = <32>;
306 mdma0: mdma@10800000 {
307 compatible = "arm,pl330", "arm,primecell";
308 reg = <0x10800000 0x1000>;
309 interrupts = <0 33 0>;
310 clocks = <&clock 473>;
311 clock-names = "apb_pclk";
317 mdma1: mdma@11C10000 {
318 compatible = "arm,pl330", "arm,primecell";
319 reg = <0x11C10000 0x1000>;
320 interrupts = <0 124 0>;
321 clocks = <&clock 442>;
322 clock-names = "apb_pclk";
329 spi_0: spi@12d20000 {
330 compatible = "samsung,exynos4210-spi";
331 reg = <0x12d20000 0x100>;
332 interrupts = <0 66 0>;
335 dma-names = "tx", "rx";
336 #address-cells = <1>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&spi0_bus>;
340 clocks = <&clock 271>, <&clock 135>;
341 clock-names = "spi", "spi_busclk0";
345 spi_1: spi@12d30000 {
346 compatible = "samsung,exynos4210-spi";
347 reg = <0x12d30000 0x100>;
348 interrupts = <0 67 0>;
351 dma-names = "tx", "rx";
352 #address-cells = <1>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&spi1_bus>;
356 clocks = <&clock 272>, <&clock 136>;
357 clock-names = "spi", "spi_busclk0";
361 spi_2: spi@12d40000 {
362 compatible = "samsung,exynos4210-spi";
363 reg = <0x12d40000 0x100>;
364 interrupts = <0 68 0>;
367 dma-names = "tx", "rx";
368 #address-cells = <1>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&spi2_bus>;
372 clocks = <&clock 273>, <&clock 137>;
373 clock-names = "spi", "spi_busclk0";
378 clocks = <&clock 257>, <&clock 128>;
379 clock-names = "uart", "clk_uart_baud0";
383 clocks = <&clock 258>, <&clock 129>;
384 clock-names = "uart", "clk_uart_baud0";
388 clocks = <&clock 259>, <&clock 130>;
389 clock-names = "uart", "clk_uart_baud0";
393 clocks = <&clock 260>, <&clock 131>;
394 clock-names = "uart", "clk_uart_baud0";
398 compatible = "samsung,exynos4210-pwm";
399 reg = <0x12dd0000 0x100>;
400 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
402 clocks = <&clock 279>;
403 clock-names = "timers";
406 dp_phy: video-phy@10040728 {
407 compatible = "samsung,exynos5250-dp-video-phy";
408 reg = <0x10040728 4>;
412 dp-controller@145B0000 {
413 clocks = <&clock 412>;
420 samsung,power-domain = <&disp_pd>;
421 clocks = <&clock 147>, <&clock 421>;
422 clock-names = "sclk_fimd", "fimd";
426 compatible = "samsung,exynos-adc-v2";
427 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
428 interrupts = <0 106 0>;
429 clocks = <&clock 270>;
431 #io-channel-cells = <1>;
436 i2c_0: i2c@12C60000 {
437 compatible = "samsung,s3c2440-i2c";
438 reg = <0x12C60000 0x100>;
439 interrupts = <0 56 0>;
440 #address-cells = <1>;
442 clocks = <&clock 261>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&i2c0_bus>;
449 i2c_1: i2c@12C70000 {
450 compatible = "samsung,s3c2440-i2c";
451 reg = <0x12C70000 0x100>;
452 interrupts = <0 57 0>;
453 #address-cells = <1>;
455 clocks = <&clock 262>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&i2c1_bus>;
462 i2c_2: i2c@12C80000 {
463 compatible = "samsung,s3c2440-i2c";
464 reg = <0x12C80000 0x100>;
465 interrupts = <0 58 0>;
466 #address-cells = <1>;
468 clocks = <&clock 263>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&i2c2_bus>;
475 i2c_3: i2c@12C90000 {
476 compatible = "samsung,s3c2440-i2c";
477 reg = <0x12C90000 0x100>;
478 interrupts = <0 59 0>;
479 #address-cells = <1>;
481 clocks = <&clock 264>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&i2c3_bus>;
488 hsi2c_4: i2c@12CA0000 {
489 compatible = "samsung,exynos5-hsi2c";
490 reg = <0x12CA0000 0x1000>;
491 interrupts = <0 60 0>;
492 #address-cells = <1>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&i2c4_hs_bus>;
496 clocks = <&clock 265>;
497 clock-names = "hsi2c";
501 hsi2c_5: i2c@12CB0000 {
502 compatible = "samsung,exynos5-hsi2c";
503 reg = <0x12CB0000 0x1000>;
504 interrupts = <0 61 0>;
505 #address-cells = <1>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2c5_hs_bus>;
509 clocks = <&clock 266>;
510 clock-names = "hsi2c";
514 hsi2c_6: i2c@12CC0000 {
515 compatible = "samsung,exynos5-hsi2c";
516 reg = <0x12CC0000 0x1000>;
517 interrupts = <0 62 0>;
518 #address-cells = <1>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c6_hs_bus>;
522 clocks = <&clock 267>;
523 clock-names = "hsi2c";
527 hsi2c_7: i2c@12CD0000 {
528 compatible = "samsung,exynos5-hsi2c";
529 reg = <0x12CD0000 0x1000>;
530 interrupts = <0 63 0>;
531 #address-cells = <1>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&i2c7_hs_bus>;
535 clocks = <&clock 268>;
536 clock-names = "hsi2c";
540 hsi2c_8: i2c@12E00000 {
541 compatible = "samsung,exynos5-hsi2c";
542 reg = <0x12E00000 0x1000>;
543 interrupts = <0 87 0>;
544 #address-cells = <1>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c8_hs_bus>;
548 clocks = <&clock 281>;
549 clock-names = "hsi2c";
553 hsi2c_9: i2c@12E10000 {
554 compatible = "samsung,exynos5-hsi2c";
555 reg = <0x12E10000 0x1000>;
556 interrupts = <0 88 0>;
557 #address-cells = <1>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c9_hs_bus>;
561 clocks = <&clock 282>;
562 clock-names = "hsi2c";
566 hsi2c_10: i2c@12E20000 {
567 compatible = "samsung,exynos5-hsi2c";
568 reg = <0x12E20000 0x1000>;
569 interrupts = <0 203 0>;
570 #address-cells = <1>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c10_hs_bus>;
574 clocks = <&clock 283>;
575 clock-names = "hsi2c";
580 compatible = "samsung,exynos4212-hdmi";
581 reg = <0x14530000 0x70000>;
582 interrupts = <0 95 0>;
583 clocks = <&clock 413>, <&clock 143>, <&clock 768>,
584 <&clock 158>, <&clock 640>;
585 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
586 "sclk_hdmiphy", "mout_hdmi";
591 compatible = "samsung,exynos5420-mixer";
592 reg = <0x14450000 0x10000>;
593 interrupts = <0 94 0>;
594 clocks = <&clock 431>, <&clock 143>;
595 clock-names = "mixer", "sclk_hdmi";
598 gsc_0: video-scaler@13e00000 {
599 compatible = "samsung,exynos5-gsc";
600 reg = <0x13e00000 0x1000>;
601 interrupts = <0 85 0>;
602 clocks = <&clock 465>;
603 clock-names = "gscl";
604 samsung,power-domain = <&gsc_pd>;
607 gsc_1: video-scaler@13e10000 {
608 compatible = "samsung,exynos5-gsc";
609 reg = <0x13e10000 0x1000>;
610 interrupts = <0 86 0>;
611 clocks = <&clock 466>;
612 clock-names = "gscl";
613 samsung,power-domain = <&gsc_pd>;
616 tmu_cpu0: tmu@10060000 {
617 compatible = "samsung,exynos5420-tmu";
618 reg = <0x10060000 0x100>;
619 interrupts = <0 65 0>;
620 clocks = <&clock 318>;
621 clock-names = "tmu_apbif";
624 tmu_cpu1: tmu@10064000 {
625 compatible = "samsung,exynos5420-tmu";
626 reg = <0x10064000 0x100>;
627 interrupts = <0 183 0>;
628 clocks = <&clock 318>;
629 clock-names = "tmu_apbif";
632 tmu_cpu2: tmu@10068000 {
633 compatible = "samsung,exynos5420-tmu-ext-triminfo";
634 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
635 interrupts = <0 184 0>;
636 clocks = <&clock 318>, <&clock 318>;
637 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
640 tmu_cpu3: tmu@1006c000 {
641 compatible = "samsung,exynos5420-tmu-ext-triminfo";
642 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
643 interrupts = <0 185 0>;
644 clocks = <&clock 318>, <&clock 319>;
645 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
648 tmu_gpu: tmu@100a0000 {
649 compatible = "samsung,exynos5420-tmu-ext-triminfo";
650 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
651 interrupts = <0 215 0>;
652 clocks = <&clock 319>, <&clock 318>;
653 clock-names = "tmu_apbif", "tmu_triminfo_apbif";