2 * SAMSUNG EXYNOS5420 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include "exynos5.dtsi"
17 #include "exynos5420-pinctrl.dtsi"
19 #include <dt-bindings/clk/exynos-audss-clk.h>
22 compatible = "samsung,exynos5420";
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 pinctrl4 = &pinctrl_4;
42 compatible = "arm,cortex-a15";
44 clock-frequency = <1800000000>;
49 compatible = "arm,cortex-a15";
51 clock-frequency = <1800000000>;
56 compatible = "arm,cortex-a15";
58 clock-frequency = <1800000000>;
63 compatible = "arm,cortex-a15";
65 clock-frequency = <1800000000>;
69 clock: clock-controller@10010000 {
70 compatible = "samsung,exynos5420-clock";
71 reg = <0x10010000 0x30000>;
75 clock_audss: audss-clock-controller@3810000 {
76 compatible = "samsung,exynos5420-audss-clock";
77 reg = <0x03810000 0x0C>;
79 clocks = <&clock 148>;
80 clock-names = "sclk_audio";
84 compatible = "samsung,mfc-v7";
85 reg = <0x11000000 0x10000>;
86 interrupts = <0 96 0>;
87 clocks = <&clock 401>;
92 compatible = "samsung,exynos4210-mct";
93 reg = <0x101C0000 0x800>;
95 #interrups-cells = <1>;
96 interrupt-parent = <&mct_map>;
97 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
98 clocks = <&clock 1>, <&clock 315>;
99 clock-names = "fin_pll", "mct";
102 #interrupt-cells = <1>;
103 #address-cells = <0>;
105 interrupt-map = <0 &combiner 23 3>,
116 gsc_pd: power-domain@10044000 {
117 compatible = "samsung,exynos4210-pd";
118 reg = <0x10044000 0x20>;
121 isp_pd: power-domain@10044020 {
122 compatible = "samsung,exynos4210-pd";
123 reg = <0x10044020 0x20>;
126 mfc_pd: power-domain@10044060 {
127 compatible = "samsung,exynos4210-pd";
128 reg = <0x10044060 0x20>;
131 disp_pd: power-domain@100440C0 {
132 compatible = "samsung,exynos4210-pd";
133 reg = <0x100440C0 0x20>;
136 mau_pd: power-domain@100440E0 {
137 compatible = "samsung,exynos4210-pd";
138 reg = <0x100440E0 0x20>;
141 g2d_pd: power-domain@10044100 {
142 compatible = "samsung,exynos4210-pd";
143 reg = <0x10044100 0x20>;
146 msc_pd: power-domain@10044120 {
147 compatible = "samsung,exynos4210-pd";
148 reg = <0x10044120 0x20>;
151 pinctrl_0: pinctrl@13400000 {
152 compatible = "samsung,exynos5420-pinctrl";
153 reg = <0x13400000 0x1000>;
154 interrupts = <0 45 0>;
156 wakeup-interrupt-controller {
157 compatible = "samsung,exynos4210-wakeup-eint";
158 interrupt-parent = <&gic>;
159 interrupts = <0 32 0>;
163 pinctrl_1: pinctrl@13410000 {
164 compatible = "samsung,exynos5420-pinctrl";
165 reg = <0x13410000 0x1000>;
166 interrupts = <0 78 0>;
169 pinctrl_2: pinctrl@14000000 {
170 compatible = "samsung,exynos5420-pinctrl";
171 reg = <0x14000000 0x1000>;
172 interrupts = <0 46 0>;
175 pinctrl_3: pinctrl@14010000 {
176 compatible = "samsung,exynos5420-pinctrl";
177 reg = <0x14010000 0x1000>;
178 interrupts = <0 50 0>;
181 pinctrl_4: pinctrl@03860000 {
182 compatible = "samsung,exynos5420-pinctrl";
183 reg = <0x03860000 0x1000>;
184 interrupts = <0 47 0>;
188 clocks = <&clock 317>;
194 clocks = <&clock 257>, <&clock 128>;
195 clock-names = "uart", "clk_uart_baud0";
199 clocks = <&clock 258>, <&clock 129>;
200 clock-names = "uart", "clk_uart_baud0";
204 clocks = <&clock 259>, <&clock 130>;
205 clock-names = "uart", "clk_uart_baud0";
209 clocks = <&clock 260>, <&clock 131>;
210 clock-names = "uart", "clk_uart_baud0";
213 dp_phy: video-phy@10040728 {
214 compatible = "samsung,exynos5250-dp-video-phy";
215 reg = <0x10040728 4>;
219 dp-controller@145B0000 {
220 clocks = <&clock 412>;
227 samsung,power-domain = <&disp_pd>;
228 clocks = <&clock 147>, <&clock 421>;
229 clock-names = "sclk_fimd", "fimd";
233 compatible = "samsung,exynos-adc-v2";
234 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
235 interrupts = <0 106 0>;
236 clocks = <&clock 270>;
238 #io-channel-cells = <1>;
243 i2c_0: i2c@12C60000 {
244 compatible = "samsung,s3c2440-i2c";
245 reg = <0x12C60000 0x100>;
246 interrupts = <0 56 0>;
247 #address-cells = <1>;
249 clocks = <&clock 261>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&i2c0_bus>;
256 i2c_1: i2c@12C70000 {
257 compatible = "samsung,s3c2440-i2c";
258 reg = <0x12C70000 0x100>;
259 interrupts = <0 57 0>;
260 #address-cells = <1>;
262 clocks = <&clock 262>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&i2c1_bus>;
269 i2c_2: i2c@12C80000 {
270 compatible = "samsung,s3c2440-i2c";
271 reg = <0x12C80000 0x100>;
272 interrupts = <0 58 0>;
273 #address-cells = <1>;
275 clocks = <&clock 263>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&i2c2_bus>;
282 i2c_3: i2c@12C90000 {
283 compatible = "samsung,s3c2440-i2c";
284 reg = <0x12C90000 0x100>;
285 interrupts = <0 59 0>;
286 #address-cells = <1>;
288 clocks = <&clock 264>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&i2c3_bus>;
296 compatible = "samsung,exynos4212-hdmi";
297 reg = <0x14530000 0x70000>;
298 interrupts = <0 95 0>;
299 clocks = <&clock 413>, <&clock 143>, <&clock 768>,
300 <&clock 158>, <&clock 640>;
301 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
302 "sclk_hdmiphy", "mout_hdmi";
307 compatible = "samsung,exynos5420-mixer";
308 reg = <0x14450000 0x10000>;
309 interrupts = <0 94 0>;
310 clocks = <&clock 431>, <&clock 143>;
311 clock-names = "mixer", "sclk_hdmi";