arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <dt-bindings/clock/exynos5420.h>
  17 #include "exynos5.dtsi"
  18
  19 #include <dt-bindings/clock/exynos-audss-clk.h>
  20
  21 / {
  22         compatible = "samsung,exynos5420", "samsung,exynos5";
  23
  24         aliases {
  25                 mshc0 = &mmc_0;
  26                 mshc1 = &mmc_1;
  27                 mshc2 = &mmc_2;
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 pinctrl2 = &pinctrl_2;
  31                 pinctrl3 = &pinctrl_3;
  32                 pinctrl4 = &pinctrl_4;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &hsi2c_4;
  38                 i2c5 = &hsi2c_5;
  39                 i2c6 = &hsi2c_6;
  40                 i2c7 = &hsi2c_7;
  41                 i2c8 = &hsi2c_8;
  42                 i2c9 = &hsi2c_9;
  43                 i2c10 = &hsi2c_10;
  44                 gsc0 = &gsc_0;
  45                 gsc1 = &gsc_1;
  46                 spi0 = &spi_0;
  47                 spi1 = &spi_1;
  48                 spi2 = &spi_2;
  49                 usbdrdphy0 = &usbdrd_phy0;
  50                 usbdrdphy1 = &usbdrd_phy1;
  51         };
  52
  53         cluster_a15_opp_table: opp_table0 {
  54                 compatible = "operating-points-v2";
  55                 opp-shared;
  56                 opp@1800000000 {
  57                         opp-hz = /bits/ 64 <1800000000>;
  58                         opp-microvolt = <1250000>;
  59                         clock-latency-ns = <140000>;
  60                 };
  61                 opp@1700000000 {
  62                         opp-hz = /bits/ 64 <1700000000>;
  63                         opp-microvolt = <1212500>;
  64                         clock-latency-ns = <140000>;
  65                 };
  66                 opp@1600000000 {
  67                         opp-hz = /bits/ 64 <1600000000>;
  68                         opp-microvolt = <1175000>;
  69                         clock-latency-ns = <140000>;
  70                 };
  71                 opp@1500000000 {
  72                         opp-hz = /bits/ 64 <1500000000>;
  73                         opp-microvolt = <1137500>;
  74                         clock-latency-ns = <140000>;
  75                 };
  76                 opp@1400000000 {
  77                         opp-hz = /bits/ 64 <1400000000>;
  78                         opp-microvolt = <1112500>;
  79                         clock-latency-ns = <140000>;
  80                 };
  81                 opp@1300000000 {
  82                         opp-hz = /bits/ 64 <1300000000>;
  83                         opp-microvolt = <1062500>;
  84                         clock-latency-ns = <140000>;
  85                 };
  86                 opp@1200000000 {
  87                         opp-hz = /bits/ 64 <1200000000>;
  88                         opp-microvolt = <1037500>;
  89                         clock-latency-ns = <140000>;
  90                 };
  91                 opp@1100000000 {
  92                         opp-hz = /bits/ 64 <1100000000>;
  93                         opp-microvolt = <1012500>;
  94                         clock-latency-ns = <140000>;
  95                 };
  96                 opp@1000000000 {
  97                         opp-hz = /bits/ 64 <1000000000>;
  98                         opp-microvolt = < 987500>;
  99                         clock-latency-ns = <140000>;
 100                 };
 101                 opp@900000000 {
 102                         opp-hz = /bits/ 64 <900000000>;
 103                         opp-microvolt = < 962500>;
 104                         clock-latency-ns = <140000>;
 105                 };
 106                 opp@800000000 {
 107                         opp-hz = /bits/ 64 <800000000>;
 108                         opp-microvolt = < 937500>;
 109                         clock-latency-ns = <140000>;
 110                 };
 111                 opp@700000000 {
 112                         opp-hz = /bits/ 64 <700000000>;
 113                         opp-microvolt = < 912500>;
 114                         clock-latency-ns = <140000>;
 115                 };
 116         };
 117
 118         cluster_a7_opp_table: opp_table1 {
 119                 compatible = "operating-points-v2";
 120                 opp-shared;
 121                 opp@1300000000 {
 122                         opp-hz = /bits/ 64 <1300000000>;
 123                         opp-microvolt = <1275000>;
 124                         clock-latency-ns = <140000>;
 125                 };
 126                 opp@1200000000 {
 127                         opp-hz = /bits/ 64 <1200000000>;
 128                         opp-microvolt = <1212500>;
 129                         clock-latency-ns = <140000>;
 130                 };
 131                 opp@1100000000 {
 132                         opp-hz = /bits/ 64 <1100000000>;
 133                         opp-microvolt = <1162500>;
 134                         clock-latency-ns = <140000>;
 135                 };
 136                 opp@1000000000 {
 137                         opp-hz = /bits/ 64 <1000000000>;
 138                         opp-microvolt = <1112500>;
 139                         clock-latency-ns = <140000>;
 140                 };
 141                 opp@900000000 {
 142                         opp-hz = /bits/ 64 <900000000>;
 143                         opp-microvolt = <1062500>;
 144                         clock-latency-ns = <140000>;
 145                 };
 146                 opp@800000000 {
 147                         opp-hz = /bits/ 64 <800000000>;
 148                         opp-microvolt = <1025000>;
 149                         clock-latency-ns = <140000>;
 150                 };
 151                 opp@700000000 {
 152                         opp-hz = /bits/ 64 <700000000>;
 153                         opp-microvolt = <975000>;
 154                         clock-latency-ns = <140000>;
 155                 };
 156                 opp@600000000 {
 157                         opp-hz = /bits/ 64 <600000000>;
 158                         opp-microvolt = <937500>;
 159                         clock-latency-ns = <140000>;
 160                 };
 161         };
 162
 163         /*
 164          * The 'cpus' node is not present here but instead it is provided
 165          * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
 166          */
 167
 168         cci: cci@10d20000 {
 169                 compatible = "arm,cci-400";
 170                 #address-cells = <1>;
 171                 #size-cells = <1>;
 172                 reg = <0x10d20000 0x1000>;
 173                 ranges = <0x0 0x10d20000 0x6000>;
 174
 175                 cci_control0: slave-if@4000 {
 176                         compatible = "arm,cci-400-ctrl-if";
 177                         interface-type = "ace";
 178                         reg = <0x4000 0x1000>;
 179                 };
 180                 cci_control1: slave-if@5000 {
 181                         compatible = "arm,cci-400-ctrl-if";
 182                         interface-type = "ace";
 183                         reg = <0x5000 0x1000>;
 184                 };
 185         };
 186
 187         sysram@02020000 {
 188                 compatible = "mmio-sram";
 189                 reg = <0x02020000 0x54000>;
 190                 #address-cells = <1>;
 191                 #size-cells = <1>;
 192                 ranges = <0 0x02020000 0x54000>;
 193
 194                 smp-sysram@0 {
 195                         compatible = "samsung,exynos4210-sysram";
 196                         reg = <0x0 0x1000>;
 197                 };
 198
 199                 smp-sysram@53000 {
 200                         compatible = "samsung,exynos4210-sysram-ns";
 201                         reg = <0x53000 0x1000>;
 202                 };
 203         };
 204
 205         clock: clock-controller@10010000 {
 206                 compatible = "samsung,exynos5420-clock";
 207                 reg = <0x10010000 0x30000>;
 208                 #clock-cells = <1>;
 209         };
 210
 211         clock_audss: audss-clock-controller@3810000 {
 212                 compatible = "samsung,exynos5420-audss-clock";
 213                 reg = <0x03810000 0x0C>;
 214                 #clock-cells = <1>;
 215                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
 216                          <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 217                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 218         };
 219
 220         mfc: codec@11000000 {
 221                 compatible = "samsung,mfc-v7";
 222                 reg = <0x11000000 0x10000>;
 223                 interrupts = <0 96 0>;
 224                 clocks = <&clock CLK_MFC>;
 225                 clock-names = "mfc";
 226                 power-domains = <&mfc_pd>;
 227                 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 228                 iommu-names = "left", "right";
 229         };
 230
 231         mmc_0: mmc@12200000 {
 232                 compatible = "samsung,exynos5420-dw-mshc-smu";
 233                 interrupts = <0 75 0>;
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236                 reg = <0x12200000 0x2000>;
 237                 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 238                 clock-names = "biu", "ciu";
 239                 fifo-depth = <0x40>;
 240                 status = "disabled";
 241         };
 242
 243         mmc_1: mmc@12210000 {
 244                 compatible = "samsung,exynos5420-dw-mshc-smu";
 245                 interrupts = <0 76 0>;
 246                 #address-cells = <1>;
 247                 #size-cells = <0>;
 248                 reg = <0x12210000 0x2000>;
 249                 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 250                 clock-names = "biu", "ciu";
 251                 fifo-depth = <0x40>;
 252                 status = "disabled";
 253         };
 254
 255         mmc_2: mmc@12220000 {
 256                 compatible = "samsung,exynos5420-dw-mshc";
 257                 interrupts = <0 77 0>;
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260                 reg = <0x12220000 0x1000>;
 261                 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 262                 clock-names = "biu", "ciu";
 263                 fifo-depth = <0x40>;
 264                 status = "disabled";
 265         };
 266
 267         mct: mct@101C0000 {
 268                 compatible = "samsung,exynos4210-mct";
 269                 reg = <0x101C0000 0x800>;
 270                 interrupt-controller;
 271                 #interrupt-cells = <1>;
 272                 interrupt-parent = <&mct_map>;
 273                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 274                                 <8>, <9>, <10>, <11>;
 275                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 276                 clock-names = "fin_pll", "mct";
 277
 278                 mct_map: mct-map {
 279                         #interrupt-cells = <1>;
 280                         #address-cells = <0>;
 281                         #size-cells = <0>;
 282                         interrupt-map = <0 &combiner 23 3>,
 283                                         <1 &combiner 23 4>,
 284                                         <2 &combiner 25 2>,
 285                                         <3 &combiner 25 3>,
 286                                         <4 &gic 0 120 0>,
 287                                         <5 &gic 0 121 0>,
 288                                         <6 &gic 0 122 0>,
 289                                         <7 &gic 0 123 0>,
 290                                         <8 &gic 0 128 0>,
 291                                         <9 &gic 0 129 0>,
 292                                         <10 &gic 0 130 0>,
 293                                         <11 &gic 0 131 0>;
 294                 };
 295         };
 296
 297         gsc_pd: power-domain@10044000 {
 298                 compatible = "samsung,exynos4210-pd";
 299                 reg = <0x10044000 0x20>;
 300                 #power-domain-cells = <0>;
 301                 clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
 302                 clock-names = "asb0", "asb1";
 303         };
 304
 305         isp_pd: power-domain@10044020 {
 306                 compatible = "samsung,exynos4210-pd";
 307                 reg = <0x10044020 0x20>;
 308                 #power-domain-cells = <0>;
 309         };
 310
 311         mfc_pd: power-domain@10044060 {
 312                 compatible = "samsung,exynos4210-pd";
 313                 reg = <0x10044060 0x20>;
 314                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
 315                 clock-names = "oscclk", "clk0";
 316                 #power-domain-cells = <0>;
 317         };
 318
 319         msc_pd: power-domain@10044120 {
 320                 compatible = "samsung,exynos4210-pd";
 321                 reg = <0x10044120 0x20>;
 322                 #power-domain-cells = <0>;
 323         };
 324
 325         disp_pd: power-domain@100440C0 {
 326                 compatible = "samsung,exynos4210-pd";
 327                 reg = <0x100440C0 0x20>;
 328                 #power-domain-cells = <0>;
 329                 clocks = <&clock CLK_FIN_PLL>,
 330                          <&clock CLK_MOUT_USER_ACLK200_DISP1>,
 331                          <&clock CLK_MOUT_USER_ACLK300_DISP1>,
 332                          <&clock CLK_MOUT_USER_ACLK400_DISP1>,
 333                          <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
 334                 clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
 335         };
 336
 337         pinctrl_0: pinctrl@13400000 {
 338                 compatible = "samsung,exynos5420-pinctrl";
 339                 reg = <0x13400000 0x1000>;
 340                 interrupts = <0 45 0>;
 341
 342                 wakeup-interrupt-controller {
 343                         compatible = "samsung,exynos4210-wakeup-eint";
 344                         interrupt-parent = <&gic>;
 345                         interrupts = <0 32 0>;
 346                 };
 347         };
 348
 349         pinctrl_1: pinctrl@13410000 {
 350                 compatible = "samsung,exynos5420-pinctrl";
 351                 reg = <0x13410000 0x1000>;
 352                 interrupts = <0 78 0>;
 353         };
 354
 355         pinctrl_2: pinctrl@14000000 {
 356                 compatible = "samsung,exynos5420-pinctrl";
 357                 reg = <0x14000000 0x1000>;
 358                 interrupts = <0 46 0>;
 359         };
 360
 361         pinctrl_3: pinctrl@14010000 {
 362                 compatible = "samsung,exynos5420-pinctrl";
 363                 reg = <0x14010000 0x1000>;
 364                 interrupts = <0 50 0>;
 365         };
 366
 367         pinctrl_4: pinctrl@03860000 {
 368                 compatible = "samsung,exynos5420-pinctrl";
 369                 reg = <0x03860000 0x1000>;
 370                 interrupts = <0 47 0>;
 371         };
 372
 373         amba {
 374                 #address-cells = <1>;
 375                 #size-cells = <1>;
 376                 compatible = "arm,amba-bus";
 377                 interrupt-parent = <&gic>;
 378                 ranges;
 379
 380                 adma: adma@03880000 {
 381                         compatible = "arm,pl330", "arm,primecell";
 382                         reg = <0x03880000 0x1000>;
 383                         interrupts = <0 110 0>;
 384                         clocks = <&clock_audss EXYNOS_ADMA>;
 385                         clock-names = "apb_pclk";
 386                         #dma-cells = <1>;
 387                         #dma-channels = <6>;
 388                         #dma-requests = <16>;
 389                 };
 390
 391                 pdma0: pdma@121A0000 {
 392                         compatible = "arm,pl330", "arm,primecell";
 393                         reg = <0x121A0000 0x1000>;
 394                         interrupts = <0 34 0>;
 395                         clocks = <&clock CLK_PDMA0>;
 396                         clock-names = "apb_pclk";
 397                         #dma-cells = <1>;
 398                         #dma-channels = <8>;
 399                         #dma-requests = <32>;
 400                 };
 401
 402                 pdma1: pdma@121B0000 {
 403                         compatible = "arm,pl330", "arm,primecell";
 404                         reg = <0x121B0000 0x1000>;
 405                         interrupts = <0 35 0>;
 406                         clocks = <&clock CLK_PDMA1>;
 407                         clock-names = "apb_pclk";
 408                         #dma-cells = <1>;
 409                         #dma-channels = <8>;
 410                         #dma-requests = <32>;
 411                 };
 412
 413                 mdma0: mdma@10800000 {
 414                         compatible = "arm,pl330", "arm,primecell";
 415                         reg = <0x10800000 0x1000>;
 416                         interrupts = <0 33 0>;
 417                         clocks = <&clock CLK_MDMA0>;
 418                         clock-names = "apb_pclk";
 419                         #dma-cells = <1>;
 420                         #dma-channels = <8>;
 421                         #dma-requests = <1>;
 422                 };
 423
 424                 mdma1: mdma@11C10000 {
 425                         compatible = "arm,pl330", "arm,primecell";
 426                         reg = <0x11C10000 0x1000>;
 427                         interrupts = <0 124 0>;
 428                         clocks = <&clock CLK_MDMA1>;
 429                         clock-names = "apb_pclk";
 430                         #dma-cells = <1>;
 431                         #dma-channels = <8>;
 432                         #dma-requests = <1>;
 433                         /*
 434                          * MDMA1 can support both secure and non-secure
 435                          * AXI transactions. When this is enabled in the kernel
 436                          * for boards that run in secure mode, we are getting
 437                          * imprecise external aborts causing the kernel to oops.
 438                          */
 439                         status = "disabled";
 440                 };
 441         };
 442
 443         i2s0: i2s@03830000 {
 444                 compatible = "samsung,exynos5420-i2s";
 445                 reg = <0x03830000 0x100>;
 446                 dmas = <&adma 0
 447                         &adma 2
 448                         &adma 1>;
 449                 dma-names = "tx", "rx", "tx-sec";
 450                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 451                         <&clock_audss EXYNOS_I2S_BUS>,
 452                         <&clock_audss EXYNOS_SCLK_I2S>;
 453                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 454                 #clock-cells = <1>;
 455                 clock-output-names = "i2s_cdclk0";
 456                 #sound-dai-cells = <1>;
 457                 samsung,idma-addr = <0x03000000>;
 458                 pinctrl-names = "default";
 459                 pinctrl-0 = <&i2s0_bus>;
 460                 status = "disabled";
 461         };
 462
 463         i2s1: i2s@12D60000 {
 464                 compatible = "samsung,exynos5420-i2s";
 465                 reg = <0x12D60000 0x100>;
 466                 dmas = <&pdma1 12
 467                         &pdma1 11>;
 468                 dma-names = "tx", "rx";
 469                 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 470                 clock-names = "iis", "i2s_opclk0";
 471                 #clock-cells = <1>;
 472                 clock-output-names = "i2s_cdclk1";
 473                 #sound-dai-cells = <1>;
 474                 pinctrl-names = "default";
 475                 pinctrl-0 = <&i2s1_bus>;
 476                 status = "disabled";
 477         };
 478
 479         i2s2: i2s@12D70000 {
 480                 compatible = "samsung,exynos5420-i2s";
 481                 reg = <0x12D70000 0x100>;
 482                 dmas = <&pdma0 12
 483                         &pdma0 11>;
 484                 dma-names = "tx", "rx";
 485                 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 486                 clock-names = "iis", "i2s_opclk0";
 487                 #clock-cells = <1>;
 488                 clock-output-names = "i2s_cdclk2";
 489                 #sound-dai-cells = <1>;
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&i2s2_bus>;
 492                 status = "disabled";
 493         };
 494
 495         spi_0: spi@12d20000 {
 496                 compatible = "samsung,exynos4210-spi";
 497                 reg = <0x12d20000 0x100>;
 498                 interrupts = <0 68 0>;
 499                 dmas = <&pdma0 5
 500                         &pdma0 4>;
 501                 dma-names = "tx", "rx";
 502                 #address-cells = <1>;
 503                 #size-cells = <0>;
 504                 pinctrl-names = "default";
 505                 pinctrl-0 = <&spi0_bus>;
 506                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 507                 clock-names = "spi", "spi_busclk0";
 508                 status = "disabled";
 509         };
 510
 511         spi_1: spi@12d30000 {
 512                 compatible = "samsung,exynos4210-spi";
 513                 reg = <0x12d30000 0x100>;
 514                 interrupts = <0 69 0>;
 515                 dmas = <&pdma1 5
 516                         &pdma1 4>;
 517                 dma-names = "tx", "rx";
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&spi1_bus>;
 522                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 523                 clock-names = "spi", "spi_busclk0";
 524                 status = "disabled";
 525         };
 526
 527         spi_2: spi@12d40000 {
 528                 compatible = "samsung,exynos4210-spi";
 529                 reg = <0x12d40000 0x100>;
 530                 interrupts = <0 70 0>;
 531                 dmas = <&pdma0 7
 532                         &pdma0 6>;
 533                 dma-names = "tx", "rx";
 534                 #address-cells = <1>;
 535                 #size-cells = <0>;
 536                 pinctrl-names = "default";
 537                 pinctrl-0 = <&spi2_bus>;
 538                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 539                 clock-names = "spi", "spi_busclk0";
 540                 status = "disabled";
 541         };
 542
 543         pwm: pwm@12dd0000 {
 544                 compatible = "samsung,exynos4210-pwm";
 545                 reg = <0x12dd0000 0x100>;
 546                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 547                 #pwm-cells = <3>;
 548                 clocks = <&clock CLK_PWM>;
 549                 clock-names = "timers";
 550         };
 551
 552         dp_phy: video-phy@10040728 {
 553                 compatible = "samsung,exynos5420-dp-video-phy";
 554                 samsung,pmu-syscon = <&pmu_system_controller>;
 555                 #phy-cells = <0>;
 556         };
 557
 558         mipi_phy: video-phy@10040714 {
 559                 compatible = "samsung,s5pv210-mipi-video-phy";
 560                 syscon = <&pmu_system_controller>;
 561                 #phy-cells = <1>;
 562         };
 563
 564         dsi@14500000 {
 565                 compatible = "samsung,exynos5410-mipi-dsi";
 566                 reg = <0x14500000 0x10000>;
 567                 interrupts = <0 82 0>;
 568                 phys = <&mipi_phy 1>;
 569                 phy-names = "dsim";
 570                 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
 571                 clock-names = "bus_clk", "pll_clk";
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 status = "disabled";
 575         };
 576
 577         adc: adc@12D10000 {
 578                 compatible = "samsung,exynos-adc-v2";
 579                 reg = <0x12D10000 0x100>;
 580                 interrupts = <0 106 0>;
 581                 clocks = <&clock CLK_TSADC>;
 582                 clock-names = "adc";
 583                 #io-channel-cells = <1>;
 584                 io-channel-ranges;
 585                 samsung,syscon-phandle = <&pmu_system_controller>;
 586                 status = "disabled";
 587         };
 588
 589         i2c_0: i2c@12C60000 {
 590                 compatible = "samsung,s3c2440-i2c";
 591                 reg = <0x12C60000 0x100>;
 592                 interrupts = <0 56 0>;
 593                 #address-cells = <1>;
 594                 #size-cells = <0>;
 595                 clocks = <&clock CLK_I2C0>;
 596                 clock-names = "i2c";
 597                 pinctrl-names = "default";
 598                 pinctrl-0 = <&i2c0_bus>;
 599                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 600                 status = "disabled";
 601         };
 602
 603         i2c_1: i2c@12C70000 {
 604                 compatible = "samsung,s3c2440-i2c";
 605                 reg = <0x12C70000 0x100>;
 606                 interrupts = <0 57 0>;
 607                 #address-cells = <1>;
 608                 #size-cells = <0>;
 609                 clocks = <&clock CLK_I2C1>;
 610                 clock-names = "i2c";
 611                 pinctrl-names = "default";
 612                 pinctrl-0 = <&i2c1_bus>;
 613                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 614                 status = "disabled";
 615         };
 616
 617         i2c_2: i2c@12C80000 {
 618                 compatible = "samsung,s3c2440-i2c";
 619                 reg = <0x12C80000 0x100>;
 620                 interrupts = <0 58 0>;
 621                 #address-cells = <1>;
 622                 #size-cells = <0>;
 623                 clocks = <&clock CLK_I2C2>;
 624                 clock-names = "i2c";
 625                 pinctrl-names = "default";
 626                 pinctrl-0 = <&i2c2_bus>;
 627                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 628                 status = "disabled";
 629         };
 630
 631         i2c_3: i2c@12C90000 {
 632                 compatible = "samsung,s3c2440-i2c";
 633                 reg = <0x12C90000 0x100>;
 634                 interrupts = <0 59 0>;
 635                 #address-cells = <1>;
 636                 #size-cells = <0>;
 637                 clocks = <&clock CLK_I2C3>;
 638                 clock-names = "i2c";
 639                 pinctrl-names = "default";
 640                 pinctrl-0 = <&i2c3_bus>;
 641                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 642                 status = "disabled";
 643         };
 644
 645         hsi2c_4: i2c@12CA0000 {
 646                 compatible = "samsung,exynos5-hsi2c";
 647                 reg = <0x12CA0000 0x1000>;
 648                 interrupts = <0 60 0>;
 649                 #address-cells = <1>;
 650                 #size-cells = <0>;
 651                 pinctrl-names = "default";
 652                 pinctrl-0 = <&i2c4_hs_bus>;
 653                 clocks = <&clock CLK_USI0>;
 654                 clock-names = "hsi2c";
 655                 status = "disabled";
 656         };
 657
 658         hsi2c_5: i2c@12CB0000 {
 659                 compatible = "samsung,exynos5-hsi2c";
 660                 reg = <0x12CB0000 0x1000>;
 661                 interrupts = <0 61 0>;
 662                 #address-cells = <1>;
 663                 #size-cells = <0>;
 664                 pinctrl-names = "default";
 665                 pinctrl-0 = <&i2c5_hs_bus>;
 666                 clocks = <&clock CLK_USI1>;
 667                 clock-names = "hsi2c";
 668                 status = "disabled";
 669         };
 670
 671         hsi2c_6: i2c@12CC0000 {
 672                 compatible = "samsung,exynos5-hsi2c";
 673                 reg = <0x12CC0000 0x1000>;
 674                 interrupts = <0 62 0>;
 675                 #address-cells = <1>;
 676                 #size-cells = <0>;
 677                 pinctrl-names = "default";
 678                 pinctrl-0 = <&i2c6_hs_bus>;
 679                 clocks = <&clock CLK_USI2>;
 680                 clock-names = "hsi2c";
 681                 status = "disabled";
 682         };
 683
 684         hsi2c_7: i2c@12CD0000 {
 685                 compatible = "samsung,exynos5-hsi2c";
 686                 reg = <0x12CD0000 0x1000>;
 687                 interrupts = <0 63 0>;
 688                 #address-cells = <1>;
 689                 #size-cells = <0>;
 690                 pinctrl-names = "default";
 691                 pinctrl-0 = <&i2c7_hs_bus>;
 692                 clocks = <&clock CLK_USI3>;
 693                 clock-names = "hsi2c";
 694                 status = "disabled";
 695         };
 696
 697         hsi2c_8: i2c@12E00000 {
 698                 compatible = "samsung,exynos5-hsi2c";
 699                 reg = <0x12E00000 0x1000>;
 700                 interrupts = <0 87 0>;
 701                 #address-cells = <1>;
 702                 #size-cells = <0>;
 703                 pinctrl-names = "default";
 704                 pinctrl-0 = <&i2c8_hs_bus>;
 705                 clocks = <&clock CLK_USI4>;
 706                 clock-names = "hsi2c";
 707                 status = "disabled";
 708         };
 709
 710         hsi2c_9: i2c@12E10000 {
 711                 compatible = "samsung,exynos5-hsi2c";
 712                 reg = <0x12E10000 0x1000>;
 713                 interrupts = <0 88 0>;
 714                 #address-cells = <1>;
 715                 #size-cells = <0>;
 716                 pinctrl-names = "default";
 717                 pinctrl-0 = <&i2c9_hs_bus>;
 718                 clocks = <&clock CLK_USI5>;
 719                 clock-names = "hsi2c";
 720                 status = "disabled";
 721         };
 722
 723         hsi2c_10: i2c@12E20000 {
 724                 compatible = "samsung,exynos5-hsi2c";
 725                 reg = <0x12E20000 0x1000>;
 726                 interrupts = <0 203 0>;
 727                 #address-cells = <1>;
 728                 #size-cells = <0>;
 729                 pinctrl-names = "default";
 730                 pinctrl-0 = <&i2c10_hs_bus>;
 731                 clocks = <&clock CLK_USI6>;
 732                 clock-names = "hsi2c";
 733                 status = "disabled";
 734         };
 735
 736         hdmi: hdmi@14530000 {
 737                 compatible = "samsung,exynos5420-hdmi";
 738                 reg = <0x14530000 0x70000>;
 739                 interrupts = <0 95 0>;
 740                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 741                          <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 742                          <&clock CLK_MOUT_HDMI>;
 743                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 744                         "sclk_hdmiphy", "mout_hdmi";
 745                 phy = <&hdmiphy>;
 746                 samsung,syscon-phandle = <&pmu_system_controller>;
 747                 status = "disabled";
 748                 power-domains = <&disp_pd>;
 749         };
 750
 751         hdmiphy: hdmiphy@145D0000 {
 752                 reg = <0x145D0000 0x20>;
 753         };
 754
 755         mixer: mixer@14450000 {
 756                 compatible = "samsung,exynos5420-mixer";
 757                 reg = <0x14450000 0x10000>;
 758                 interrupts = <0 94 0>;
 759                 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 760                          <&clock CLK_SCLK_HDMI>;
 761                 clock-names = "mixer", "hdmi", "sclk_hdmi";
 762                 power-domains = <&disp_pd>;
 763                 iommus = <&sysmmu_tv>;
 764         };
 765
 766         rotator: rotator@11C00000 {
 767                 compatible = "samsung,exynos5250-rotator";
 768                 reg = <0x11C00000 0x64>;
 769                 interrupts = <0 84 0>;
 770                 clocks = <&clock CLK_ROTATOR>;
 771                 clock-names = "rotator";
 772                 iommus = <&sysmmu_rotator>;
 773         };
 774
 775         gsc_0: video-scaler@13e00000 {
 776                 compatible = "samsung,exynos5-gsc";
 777                 reg = <0x13e00000 0x1000>;
 778                 interrupts = <0 85 0>;
 779                 clocks = <&clock CLK_GSCL0>;
 780                 clock-names = "gscl";
 781                 power-domains = <&gsc_pd>;
 782                 iommus = <&sysmmu_gscl0>;
 783         };
 784
 785         gsc_1: video-scaler@13e10000 {
 786                 compatible = "samsung,exynos5-gsc";
 787                 reg = <0x13e10000 0x1000>;
 788                 interrupts = <0 86 0>;
 789                 clocks = <&clock CLK_GSCL1>;
 790                 clock-names = "gscl";
 791                 power-domains = <&gsc_pd>;
 792                 iommus = <&sysmmu_gscl1>;
 793         };
 794
 795         jpeg_0: jpeg@11F50000 {
 796                 compatible = "samsung,exynos5420-jpeg";
 797                 reg = <0x11F50000 0x1000>;
 798                 interrupts = <0 89 0>;
 799                 clock-names = "jpeg";
 800                 clocks = <&clock CLK_JPEG>;
 801                 iommus = <&sysmmu_jpeg0>;
 802         };
 803
 804         jpeg_1: jpeg@11F60000 {
 805                 compatible = "samsung,exynos5420-jpeg";
 806                 reg = <0x11F60000 0x1000>;
 807                 interrupts = <0 168 0>;
 808                 clock-names = "jpeg";
 809                 clocks = <&clock CLK_JPEG2>;
 810                 iommus = <&sysmmu_jpeg1>;
 811         };
 812
 813         pmu_system_controller: system-controller@10040000 {
 814                 compatible = "samsung,exynos5420-pmu", "syscon";
 815                 reg = <0x10040000 0x5000>;
 816                 clock-names = "clkout16";
 817                 clocks = <&clock CLK_FIN_PLL>;
 818                 #clock-cells = <1>;
 819                 interrupt-controller;
 820                 #interrupt-cells = <3>;
 821                 interrupt-parent = <&gic>;
 822         };
 823
 824         sysreg_system_controller: syscon@10050000 {
 825                 compatible = "samsung,exynos5-sysreg", "syscon";
 826                 reg = <0x10050000 0x5000>;
 827         };
 828
 829         tmu_cpu0: tmu@10060000 {
 830                 compatible = "samsung,exynos5420-tmu";
 831                 reg = <0x10060000 0x100>;
 832                 interrupts = <0 65 0>;
 833                 clocks = <&clock CLK_TMU>;
 834                 clock-names = "tmu_apbif";
 835                 #include "exynos4412-tmu-sensor-conf.dtsi"
 836         };
 837
 838         tmu_cpu1: tmu@10064000 {
 839                 compatible = "samsung,exynos5420-tmu";
 840                 reg = <0x10064000 0x100>;
 841                 interrupts = <0 183 0>;
 842                 clocks = <&clock CLK_TMU>;
 843                 clock-names = "tmu_apbif";
 844                 #include "exynos4412-tmu-sensor-conf.dtsi"
 845         };
 846
 847         tmu_cpu2: tmu@10068000 {
 848                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 849                 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 850                 interrupts = <0 184 0>;
 851                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 852                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 853                 #include "exynos4412-tmu-sensor-conf.dtsi"
 854         };
 855
 856         tmu_cpu3: tmu@1006c000 {
 857                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 858                 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 859                 interrupts = <0 185 0>;
 860                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 861                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 862                 #include "exynos4412-tmu-sensor-conf.dtsi"
 863         };
 864
 865         tmu_gpu: tmu@100a0000 {
 866                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 867                 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 868                 interrupts = <0 215 0>;
 869                 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 870                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 871                 #include "exynos4412-tmu-sensor-conf.dtsi"
 872         };
 873
 874         thermal-zones {
 875                 cpu0_thermal: cpu0-thermal {
 876                         thermal-sensors = <&tmu_cpu0>;
 877                         #include "exynos5420-trip-points.dtsi"
 878                 };
 879                 cpu1_thermal: cpu1-thermal {
 880                        thermal-sensors = <&tmu_cpu1>;
 881                        #include "exynos5420-trip-points.dtsi"
 882                 };
 883                 cpu2_thermal: cpu2-thermal {
 884                        thermal-sensors = <&tmu_cpu2>;
 885                        #include "exynos5420-trip-points.dtsi"
 886                 };
 887                 cpu3_thermal: cpu3-thermal {
 888                        thermal-sensors = <&tmu_cpu3>;
 889                        #include "exynos5420-trip-points.dtsi"
 890                 };
 891                 gpu_thermal: gpu-thermal {
 892                        thermal-sensors = <&tmu_gpu>;
 893                        #include "exynos5420-trip-points.dtsi"
 894                 };
 895         };
 896
 897         watchdog: watchdog@101D0000 {
 898                 compatible = "samsung,exynos5420-wdt";
 899                 reg = <0x101D0000 0x100>;
 900                 interrupts = <0 42 0>;
 901                 clocks = <&clock CLK_WDT>;
 902                 clock-names = "watchdog";
 903                 samsung,syscon-phandle = <&pmu_system_controller>;
 904         };
 905
 906         sss: sss@10830000 {
 907                 compatible = "samsung,exynos4210-secss";
 908                 reg = <0x10830000 0x300>;
 909                 interrupts = <0 112 0>;
 910                 clocks = <&clock CLK_SSS>;
 911                 clock-names = "secss";
 912         };
 913
 914         usbdrd3_0: usb@12000000 {
 915                 compatible = "samsung,exynos5250-dwusb3";
 916                 clocks = <&clock CLK_USBD300>;
 917                 clock-names = "usbdrd30";
 918                 #address-cells = <1>;
 919                 #size-cells = <1>;
 920                 ranges;
 921
 922                 usbdrd_dwc3_0: dwc3 {
 923                         compatible = "snps,dwc3";
 924                         reg = <0x12000000 0x10000>;
 925                         interrupts = <0 72 0>;
 926                         phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
 927                         phy-names = "usb2-phy", "usb3-phy";
 928                 };
 929         };
 930
 931         usbdrd_phy0: phy@12100000 {
 932                 compatible = "samsung,exynos5420-usbdrd-phy";
 933                 reg = <0x12100000 0x100>;
 934                 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 935                 clock-names = "phy", "ref";
 936                 samsung,pmu-syscon = <&pmu_system_controller>;
 937                 #phy-cells = <1>;
 938         };
 939
 940         usbdrd3_1: usb@12400000 {
 941                 compatible = "samsung,exynos5250-dwusb3";
 942                 clocks = <&clock CLK_USBD301>;
 943                 clock-names = "usbdrd30";
 944                 #address-cells = <1>;
 945                 #size-cells = <1>;
 946                 ranges;
 947
 948                 usbdrd_dwc3_1: dwc3 {
 949                         compatible = "snps,dwc3";
 950                         reg = <0x12400000 0x10000>;
 951                         interrupts = <0 73 0>;
 952                         phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
 953                         phy-names = "usb2-phy", "usb3-phy";
 954                 };
 955         };
 956
 957         usbdrd_phy1: phy@12500000 {
 958                 compatible = "samsung,exynos5420-usbdrd-phy";
 959                 reg = <0x12500000 0x100>;
 960                 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 961                 clock-names = "phy", "ref";
 962                 samsung,pmu-syscon = <&pmu_system_controller>;
 963                 #phy-cells = <1>;
 964         };
 965
 966         usbhost2: usb@12110000 {
 967                 compatible = "samsung,exynos4210-ehci";
 968                 reg = <0x12110000 0x100>;
 969                 interrupts = <0 71 0>;
 970
 971                 clocks = <&clock CLK_USBH20>;
 972                 clock-names = "usbhost";
 973                 #address-cells = <1>;
 974                 #size-cells = <0>;
 975                 port@0 {
 976                         reg = <0>;
 977                         phys = <&usb2_phy 1>;
 978                 };
 979         };
 980
 981         usbhost1: usb@12120000 {
 982                 compatible = "samsung,exynos4210-ohci";
 983                 reg = <0x12120000 0x100>;
 984                 interrupts = <0 71 0>;
 985
 986                 clocks = <&clock CLK_USBH20>;
 987                 clock-names = "usbhost";
 988                 #address-cells = <1>;
 989                 #size-cells = <0>;
 990                 port@0 {
 991                         reg = <0>;
 992                         phys = <&usb2_phy 1>;
 993                 };
 994         };
 995
 996         usb2_phy: phy@12130000 {
 997                 compatible = "samsung,exynos5250-usb2-phy";
 998                 reg = <0x12130000 0x100>;
 999                 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1000                 clock-names = "phy", "ref";
1001                 #phy-cells = <1>;
1002                 samsung,sysreg-phandle = <&sysreg_system_controller>;
1003                 samsung,pmureg-phandle = <&pmu_system_controller>;
1004         };
1005
1006         sysmmu_g2dr: sysmmu@0x10A60000 {
1007                 compatible = "samsung,exynos-sysmmu";
1008                 reg = <0x10A60000 0x1000>;
1009                 interrupt-parent = <&combiner>;
1010                 interrupts = <24 5>;
1011                 clock-names = "sysmmu", "master";
1012                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
1013                 #iommu-cells = <0>;
1014         };
1015
1016         sysmmu_g2dw: sysmmu@0x10A70000 {
1017                 compatible = "samsung,exynos-sysmmu";
1018                 reg = <0x10A70000 0x1000>;
1019                 interrupt-parent = <&combiner>;
1020                 interrupts = <22 2>;
1021                 clock-names = "sysmmu", "master";
1022                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
1023                 #iommu-cells = <0>;
1024         };
1025
1026         sysmmu_tv: sysmmu@0x14650000 {
1027                 compatible = "samsung,exynos-sysmmu";
1028                 reg = <0x14650000 0x1000>;
1029                 interrupt-parent = <&combiner>;
1030                 interrupts = <7 4>;
1031                 clock-names = "sysmmu", "master";
1032                 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
1033                 power-domains = <&disp_pd>;
1034                 #iommu-cells = <0>;
1035         };
1036
1037         sysmmu_gscl0: sysmmu@0x13E80000 {
1038                 compatible = "samsung,exynos-sysmmu";
1039                 reg = <0x13E80000 0x1000>;
1040                 interrupt-parent = <&combiner>;
1041                 interrupts = <2 0>;
1042                 clock-names = "sysmmu", "master";
1043                 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1044                 power-domains = <&gsc_pd>;
1045                 #iommu-cells = <0>;
1046         };
1047
1048         sysmmu_gscl1: sysmmu@0x13E90000 {
1049                 compatible = "samsung,exynos-sysmmu";
1050                 reg = <0x13E90000 0x1000>;
1051                 interrupt-parent = <&combiner>;
1052                 interrupts = <2 2>;
1053                 clock-names = "sysmmu", "master";
1054                 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1055                 power-domains = <&gsc_pd>;
1056                 #iommu-cells = <0>;
1057         };
1058
1059         sysmmu_scaler0r: sysmmu@0x12880000 {
1060                 compatible = "samsung,exynos-sysmmu";
1061                 reg = <0x12880000 0x1000>;
1062                 interrupt-parent = <&combiner>;
1063                 interrupts = <22 4>;
1064                 clock-names = "sysmmu", "master";
1065                 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1066                 #iommu-cells = <0>;
1067         };
1068
1069         sysmmu_scaler1r: sysmmu@0x12890000 {
1070                 compatible = "samsung,exynos-sysmmu";
1071                 reg = <0x12890000 0x1000>;
1072                 interrupts = <0 186 0>;
1073                 clock-names = "sysmmu", "master";
1074                 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1075                 #iommu-cells = <0>;
1076         };
1077
1078         sysmmu_scaler2r: sysmmu@0x128A0000 {
1079                 compatible = "samsung,exynos-sysmmu";
1080                 reg = <0x128A0000 0x1000>;
1081                 interrupts = <0 188 0>;
1082                 clock-names = "sysmmu", "master";
1083                 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1084                 #iommu-cells = <0>;
1085         };
1086
1087         sysmmu_scaler0w: sysmmu@0x128C0000 {
1088                 compatible = "samsung,exynos-sysmmu";
1089                 reg = <0x128C0000 0x1000>;
1090                 interrupt-parent = <&combiner>;
1091                 interrupts = <27 2>;
1092                 clock-names = "sysmmu", "master";
1093                 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1094                 #iommu-cells = <0>;
1095         };
1096
1097         sysmmu_scaler1w: sysmmu@0x128D0000 {
1098                 compatible = "samsung,exynos-sysmmu";
1099                 reg = <0x128D0000 0x1000>;
1100                 interrupt-parent = <&combiner>;
1101                 interrupts = <22 6>;
1102                 clock-names = "sysmmu", "master";
1103                 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1104                 #iommu-cells = <0>;
1105         };
1106
1107         sysmmu_scaler2w: sysmmu@0x128E0000 {
1108                 compatible = "samsung,exynos-sysmmu";
1109                 reg = <0x128E0000 0x1000>;
1110                 interrupt-parent = <&combiner>;
1111                 interrupts = <19 6>;
1112                 clock-names = "sysmmu", "master";
1113                 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1114                 #iommu-cells = <0>;
1115         };
1116
1117         sysmmu_rotator: sysmmu@0x11D40000 {
1118                 compatible = "samsung,exynos-sysmmu";
1119                 reg = <0x11D40000 0x1000>;
1120                 interrupt-parent = <&combiner>;
1121                 interrupts = <4 0>;
1122                 clock-names = "sysmmu", "master";
1123                 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1124                 #iommu-cells = <0>;
1125         };
1126
1127         sysmmu_jpeg0: sysmmu@0x11F10000 {
1128                 compatible = "samsung,exynos-sysmmu";
1129                 reg = <0x11F10000 0x1000>;
1130                 interrupt-parent = <&combiner>;
1131                 interrupts = <4 2>;
1132                 clock-names = "sysmmu", "master";
1133                 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1134                 #iommu-cells = <0>;
1135         };
1136
1137         sysmmu_jpeg1: sysmmu@0x11F20000 {
1138                 compatible = "samsung,exynos-sysmmu";
1139                 reg = <0x11F20000 0x1000>;
1140                 interrupts = <0 169 0>;
1141                 clock-names = "sysmmu", "master";
1142                 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1143                 #iommu-cells = <0>;
1144         };
1145
1146         sysmmu_mfc_l: sysmmu@0x11200000 {
1147                 compatible = "samsung,exynos-sysmmu";
1148                 reg = <0x11200000 0x1000>;
1149                 interrupt-parent = <&combiner>;
1150                 interrupts = <6 2>;
1151                 clock-names = "sysmmu", "master";
1152                 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1153                 power-domains = <&mfc_pd>;
1154                 #iommu-cells = <0>;
1155         };
1156
1157         sysmmu_mfc_r: sysmmu@0x11210000 {
1158                 compatible = "samsung,exynos-sysmmu";
1159                 reg = <0x11210000 0x1000>;
1160                 interrupt-parent = <&combiner>;
1161                 interrupts = <8 5>;
1162                 clock-names = "sysmmu", "master";
1163                 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1164                 power-domains = <&mfc_pd>;
1165                 #iommu-cells = <0>;
1166         };
1167
1168         sysmmu_fimd1_0: sysmmu@0x14640000 {
1169                 compatible = "samsung,exynos-sysmmu";
1170                 reg = <0x14640000 0x1000>;
1171                 interrupt-parent = <&combiner>;
1172                 interrupts = <3 2>;
1173                 clock-names = "sysmmu", "master";
1174                 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1175                 power-domains = <&disp_pd>;
1176                 #iommu-cells = <0>;
1177         };
1178
1179         sysmmu_fimd1_1: sysmmu@0x14680000 {
1180                 compatible = "samsung,exynos-sysmmu";
1181                 reg = <0x14680000 0x1000>;
1182                 interrupt-parent = <&combiner>;
1183                 interrupts = <3 0>;
1184                 clock-names = "sysmmu", "master";
1185                 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1186                 power-domains = <&disp_pd>;
1187                 #iommu-cells = <0>;
1188         };
1189 };
1190
1191 &dp {
1192         clocks = <&clock CLK_DP1>;
1193         clock-names = "dp";
1194         phys = <&dp_phy>;
1195         phy-names = "dp";
1196         power-domains = <&disp_pd>;
1197 };
1198
1199 &fimd {
1200         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1201         clock-names = "sclk_fimd", "fimd";
1202         power-domains = <&disp_pd>;
1203         iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1204         iommu-names = "m0", "m1";
1205 };
1206
1207 &rtc {
1208         clocks = <&clock CLK_RTC>;
1209         clock-names = "rtc";
1210         interrupt-parent = <&pmu_system_controller>;
1211         status = "disabled";
1212 };
1213
1214 &serial_0 {
1215         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1216         clock-names = "uart", "clk_uart_baud0";
1217 };
1218
1219 &serial_1 {
1220         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1221         clock-names = "uart", "clk_uart_baud0";
1222 };
1223
1224 &serial_2 {
1225         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1226         clock-names = "uart", "clk_uart_baud0";
1227 };
1228
1229 &serial_3 {
1230         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1231         clock-names = "uart", "clk_uart_baud0";
1232 };
1233
1234 #include "exynos5420-pinctrl.dtsi"