arch/arm/boot/dts/exynos5422-cpus.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5422 SoC cpu device tree source
   3  *
   4  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
   8  *
   9  * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
  10  * but particular boards choose different booting order.
  11  *
  12  * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
  13  * booting cluster (big or LITTLE) is chosen by IROM code by reading
  14  * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
  15  * from the LITTLE: Cortex-A7.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 / {
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu0: cpu@100 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a7";
  30                         reg = <0x100>;
  31                         clocks = <&clock CLK_KFC_CLK>;
  32                         clock-frequency = <1000000000>;
  33                         cci-control-port = <&cci_control0>;
  34                         operating-points-v2 = <&cluster_a7_opp_table>;
  35                 };
  36
  37                 cpu1: cpu@101 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a7";
  40                         reg = <0x101>;
  41                         clock-frequency = <1000000000>;
  42                         cci-control-port = <&cci_control0>;
  43                         operating-points-v2 = <&cluster_a7_opp_table>;
  44                 };
  45
  46                 cpu2: cpu@102 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a7";
  49                         reg = <0x102>;
  50                         clock-frequency = <1000000000>;
  51                         cci-control-port = <&cci_control0>;
  52                         operating-points-v2 = <&cluster_a7_opp_table>;
  53                 };
  54
  55                 cpu3: cpu@103 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a7";
  58                         reg = <0x103>;
  59                         clock-frequency = <1000000000>;
  60                         cci-control-port = <&cci_control0>;
  61                         operating-points-v2 = <&cluster_a7_opp_table>;
  62                 };
  63
  64                 cpu4: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a15";
  67                         clocks = <&clock CLK_ARM_CLK>;
  68                         reg = <0x0>;
  69                         clock-frequency = <1800000000>;
  70                         cci-control-port = <&cci_control1>;
  71                         operating-points-v2 = <&cluster_a15_opp_table>;
  72                 };
  73
  74                 cpu5: cpu@1 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a15";
  77                         reg = <0x1>;
  78                         clock-frequency = <1800000000>;
  79                         cci-control-port = <&cci_control1>;
  80                         operating-points-v2 = <&cluster_a15_opp_table>;
  81                 };
  82
  83                 cpu6: cpu@2 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a15";
  86                         reg = <0x2>;
  87                         clock-frequency = <1800000000>;
  88                         cci-control-port = <&cci_control1>;
  89                         operating-points-v2 = <&cluster_a15_opp_table>;
  90                 };
  91
  92                 cpu7: cpu@3 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a15";
  95                         reg = <0x3>;
  96                         clock-frequency = <1800000000>;
  97                         cci-control-port = <&cci_control1>;
  98                         operating-points-v2 = <&cluster_a15_opp_table>;
  99                 };
 100         };
 101 };