2 * Device Tree file for Cortina systems Gemini SoC
5 /include/ "skeleton.dtsi"
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/gpio/gpio.h>
15 compatible = "simple-bus";
16 interrupt-parent = <&intcon>;
19 compatible = "cortina,gemini-flash", "cfi-flash";
27 syscon: syscon@40000000 {
28 compatible = "cortina,gemini-syscon",
29 "syscon", "simple-mfd";
30 reg = <0x40000000 0x1000>;
35 compatible = "syscon-reboot";
37 /* GLOBAL_RESET register */
39 /* RESET_GLOBAL | RESET_CPU1 */
45 compatible = "cortina,gemini-watchdog";
46 reg = <0x41000000 0x1000>;
47 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
48 resets = <&syscon 23>;
52 uart0: serial@42000000 {
53 compatible = "ns16550a";
54 reg = <0x42000000 0x100>;
55 resets = <&syscon 18>;
57 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
62 compatible = "faraday,fttmr010";
63 reg = <0x43000000 0x1000>;
64 interrupt-parent = <&intcon>;
65 interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
66 <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
67 <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
68 resets = <&syscon 17>;
69 /* APB clock or RTC clock */
70 clocks = <&syscon 2>, <&syscon 0>;
71 clock-names = "PCLK", "EXTCLK";
76 compatible = "cortina,gemini-rtc";
77 reg = <0x45000000 0x100>;
78 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
79 resets = <&syscon 16>;
80 clocks = <&syscon 2>, <&syscon 0>;
81 clock-names = "PCLK", "EXTCLK";
85 compatible = "cortina,gemini-sata-bridge";
86 reg = <0x46000000 0x100>;
87 resets = <&syscon 26>,
89 reset-names = "sata0", "sata1";
90 clocks = <&syscon 10>,
92 clock-names = "SATA0_PCLK", "SATA1_PCLK";
97 intcon: interrupt-controller@48000000 {
98 compatible = "faraday,ftintc010";
99 reg = <0x48000000 0x1000>;
100 resets = <&syscon 14>;
101 interrupt-controller;
102 #interrupt-cells = <2>;
105 power-controller@4b000000 {
106 compatible = "cortina,gemini-power-controller";
107 reg = <0x4b000000 0x100>;
108 interrupts = <26 IRQ_TYPE_EDGE_RISING>;
111 gpio0: gpio@4d000000 {
112 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
113 reg = <0x4d000000 0x100>;
114 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
115 resets = <&syscon 20>;
116 clocks = <&syscon 2>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
123 gpio1: gpio@4e000000 {
124 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
125 reg = <0x4e000000 0x100>;
126 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
127 resets = <&syscon 21>;
128 clocks = <&syscon 2>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
135 gpio2: gpio@4f000000 {
136 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
137 reg = <0x4f000000 0x100>;
138 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
139 resets = <&syscon 22>;
140 clocks = <&syscon 2>;
143 interrupt-controller;
144 #interrupt-cells = <2>;
148 compatible = "cortina,gemini-pci", "faraday,ftpci100";
150 * The first 256 bytes in the IO range is actually used
151 * to configure the host bridge.
153 reg = <0x50000000 0x100>;
154 resets = <&syscon 7>;
155 clocks = <&syscon 15>, <&syscon 4>;
156 clock-names = "PCLK", "PCICLK";
157 #address-cells = <3>;
159 #interrupt-cells = <1>;
162 bus-range = <0x00 0xff>;
163 /* PCI ranges mappings */
165 /* 1MiB I/O space 0x50000000-0x500fffff */
166 <0x01000000 0 0 0x50000000 0 0x00100000>,
167 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
168 <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
172 /* 128MiB at 0x00000000-0x07ffffff */
173 <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
174 /* 64MiB at 0x00000000-0x03ffffff */
175 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
176 /* 64MiB at 0x00000000-0x03ffffff */
177 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
180 * This PCI host bridge variant has a cascaded interrupt
181 * controller embedded in the host bridge.
183 pci_intc: interrupt-controller {
184 interrupt-parent = <&intcon>;
185 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
186 interrupt-controller;
187 #address-cells = <0>;
188 #interrupt-cells = <1>;
193 compatible = "cortina,gemini-pata", "faraday,ftide010";
194 reg = <0x63000000 0x1000>;
195 interrupts = <4 IRQ_TYPE_EDGE_RISING>;
196 resets = <&syscon 2>;
197 clocks = <&syscon 14>;
198 clock-names = "PCLK";
204 compatible = "cortina,gemini-pata", "faraday,ftide010";
205 reg = <0x63400000 0x1000>;
206 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
207 resets = <&syscon 2>;
208 clocks = <&syscon 14>;
209 clock-names = "PCLK";
214 dma-controller@67000000 {
215 compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
216 /* Faraday Technology FTDMAC020 variant */
217 arm,primecell-periphid = <0x0003b080>;
218 reg = <0x67000000 0x1000>;
219 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
220 resets = <&syscon 10>;
221 clocks = <&syscon 1>;
222 clock-names = "apb_pclk";
223 /* Bus interface AHB1 (AHB0) is totally tilted */
224 lli-bus-interface-ahb2;
225 mem-bus-interface-ahb2;
226 memcpy-burst-size = <256>;
227 memcpy-bus-width = <32>;