2 * Device Tree file for Cortina systems Gemini SoC
5 /include/ "skeleton.dtsi"
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/gpio/gpio.h>
15 compatible = "simple-bus";
16 interrupt-parent = <&intcon>;
19 compatible = "cortina,gemini-flash", "cfi-flash";
27 syscon: syscon@40000000 {
28 compatible = "cortina,gemini-syscon",
29 "syscon", "simple-mfd";
30 reg = <0x40000000 0x1000>;
35 compatible = "syscon-reboot";
37 /* GLOBAL_RESET register */
39 /* RESET_GLOBAL | RESET_CPU1 */
45 compatible = "cortina,gemini-watchdog";
46 reg = <0x41000000 0x1000>;
47 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
48 resets = <&syscon 23>;
52 uart0: serial@42000000 {
53 compatible = "ns16550a";
54 reg = <0x42000000 0x100>;
55 resets = <&syscon 18>;
57 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
62 compatible = "faraday,fttmr010";
63 reg = <0x43000000 0x1000>;
64 interrupt-parent = <&intcon>;
65 interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
66 <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
67 <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
68 resets = <&syscon 17>;
69 /* APB clock or RTC clock */
70 clocks = <&syscon 2>, <&syscon 0>;
71 clock-names = "PCLK", "EXTCLK";
76 compatible = "cortina,gemini-rtc";
77 reg = <0x45000000 0x100>;
78 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
79 resets = <&syscon 16>;
80 clocks = <&syscon 2>, <&syscon 0>;
81 clock-names = "PCLK", "EXTCLK";
84 intcon: interrupt-controller@48000000 {
85 compatible = "faraday,ftintc010";
86 reg = <0x48000000 0x1000>;
87 resets = <&syscon 14>;
89 #interrupt-cells = <2>;
92 power-controller@4b000000 {
93 compatible = "cortina,gemini-power-controller";
94 reg = <0x4b000000 0x100>;
95 interrupts = <26 IRQ_TYPE_EDGE_RISING>;
98 gpio0: gpio@4d000000 {
99 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
100 reg = <0x4d000000 0x100>;
101 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
102 resets = <&syscon 20>;
103 clocks = <&syscon 2>;
106 interrupt-controller;
107 #interrupt-cells = <2>;
110 gpio1: gpio@4e000000 {
111 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
112 reg = <0x4e000000 0x100>;
113 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
114 resets = <&syscon 21>;
115 clocks = <&syscon 2>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
122 gpio2: gpio@4f000000 {
123 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
124 reg = <0x4f000000 0x100>;
125 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
126 resets = <&syscon 22>;
127 clocks = <&syscon 2>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
135 compatible = "cortina,gemini-pci", "faraday,ftpci100";
137 * The first 256 bytes in the IO range is actually used
138 * to configure the host bridge.
140 reg = <0x50000000 0x100>;
141 resets = <&syscon 7>;
142 clocks = <&syscon 15>, <&syscon 4>;
143 clock-names = "PCLK", "PCICLK";
144 #address-cells = <3>;
146 #interrupt-cells = <1>;
149 bus-range = <0x00 0xff>;
150 /* PCI ranges mappings */
152 /* 1MiB I/O space 0x50000000-0x500fffff */
153 <0x01000000 0 0 0x50000000 0 0x00100000>,
154 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
155 <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
159 /* 128MiB at 0x00000000-0x07ffffff */
160 <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
161 /* 64MiB at 0x00000000-0x03ffffff */
162 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
163 /* 64MiB at 0x00000000-0x03ffffff */
164 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
167 * This PCI host bridge variant has a cascaded interrupt
168 * controller embedded in the host bridge.
170 pci_intc: interrupt-controller {
171 interrupt-parent = <&intcon>;
172 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
173 interrupt-controller;
174 #address-cells = <0>;
175 #interrupt-cells = <1>;