arch/arm/boot/dts/highbank.dts

   1 /*
   2  * Copyright 2011 Calxeda, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 /dts-v1/;
  18
  19 /* First 4KB has pen for secondary cores. */
  20 /memreserve/ 0x00000000 0x0001000;
  21
  22 / {
  23         model = "Calxeda Highbank";
  24         compatible = "calxeda,highbank";
  25         #address-cells = <1>;
  26         #size-cells = <1>;
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu@0 {
  33                         compatible = "arm,cortex-a9";
  34                         reg = <0>;
  35                         next-level-cache = <&L2>;
  36                 };
  37
  38                 cpu@1 {
  39                         compatible = "arm,cortex-a9";
  40                         reg = <1>;
  41                         next-level-cache = <&L2>;
  42                 };
  43
  44                 cpu@2 {
  45                         compatible = "arm,cortex-a9";
  46                         reg = <2>;
  47                         next-level-cache = <&L2>;
  48                 };
  49
  50                 cpu@3 {
  51                         compatible = "arm,cortex-a9";
  52                         reg = <3>;
  53                         next-level-cache = <&L2>;
  54                 };
  55         };
  56
  57         memory {
  58                 name = "memory";
  59                 device_type = "memory";
  60                 reg = <0x00000000 0xff900000>;
  61         };
  62
  63         chosen {
  64                 bootargs = "console=ttyAMA0";
  65         };
  66
  67         soc {
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 compatible = "simple-bus";
  71                 interrupt-parent = <&intc>;
  72                 ranges;
  73
  74                 timer@fff10600 {
  75                         compatible = "arm,cortex-a9-twd-timer";
  76                         reg = <0xfff10600 0x20>;
  77                         interrupts = <1 13 0xf01>;
  78                 };
  79
  80                 watchdog@fff10620 {
  81                         compatible = "arm,cortex-a9-twd-wdt";
  82                         reg = <0xfff10620 0x20>;
  83                         interrupts = <1 14 0xf01>;
  84                 };
  85
  86                 intc: interrupt-controller@fff11000 {
  87                         compatible = "arm,cortex-a9-gic";
  88                         #interrupt-cells = <3>;
  89                         #size-cells = <0>;
  90                         #address-cells = <1>;
  91                         interrupt-controller;
  92                         reg = <0xfff11000 0x1000>,
  93                               <0xfff10100 0x100>;
  94                 };
  95
  96                 L2: l2-cache {
  97                         compatible = "arm,pl310-cache";
  98                         reg = <0xfff12000 0x1000>;
  99                         interrupts = <0 70 4>;
 100                         cache-unified;
 101                         cache-level = <2>;
 102                 };
 103
 104                 pmu {
 105                         compatible = "arm,cortex-a9-pmu";
 106                         interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
 107                 };
 108
 109                 sata@ffe08000 {
 110                         compatible = "calxeda,hb-ahci";
 111                         reg = <0xffe08000 0x10000>;
 112                         interrupts = <0 83 4>;
 113                 };
 114
 115                 sdhci@ffe0e000 {
 116                         compatible = "calxeda,hb-sdhci";
 117                         reg = <0xffe0e000 0x1000>;
 118                         interrupts = <0 90 4>;
 119                 };
 120
 121                 ipc@fff20000 {
 122                         compatible = "arm,pl320", "arm,primecell";
 123                         reg = <0xfff20000 0x1000>;
 124                         interrupts = <0 7 4>;
 125                 };
 126
 127                 gpioe: gpio@fff30000 {
 128                         #gpio-cells = <2>;
 129                         compatible = "arm,pl061", "arm,primecell";
 130                         gpio-controller;
 131                         reg = <0xfff30000 0x1000>;
 132                         interrupts = <0 14 4>;
 133                 };
 134
 135                 gpiof: gpio@fff31000 {
 136                         #gpio-cells = <2>;
 137                         compatible = "arm,pl061", "arm,primecell";
 138                         gpio-controller;
 139                         reg = <0xfff31000 0x1000>;
 140                         interrupts = <0 15 4>;
 141                 };
 142
 143                 gpiog: gpio@fff32000 {
 144                         #gpio-cells = <2>;
 145                         compatible = "arm,pl061", "arm,primecell";
 146                         gpio-controller;
 147                         reg = <0xfff32000 0x1000>;
 148                         interrupts = <0 16 4>;
 149                 };
 150
 151                 gpioh: gpio@fff33000 {
 152                         #gpio-cells = <2>;
 153                         compatible = "arm,pl061", "arm,primecell";
 154                         gpio-controller;
 155                         reg = <0xfff33000 0x1000>;
 156                         interrupts = <0 17 4>;
 157                 };
 158
 159                 timer {
 160                         compatible = "arm,sp804", "arm,primecell";
 161                         reg = <0xfff34000 0x1000>;
 162                         interrupts = <0 18 4>;
 163                 };
 164
 165                 rtc@fff35000 {
 166                         compatible = "arm,pl031", "arm,primecell";
 167                         reg = <0xfff35000 0x1000>;
 168                         interrupts = <0 19 4>;
 169                 };
 170
 171                 serial@fff36000 {
 172                         compatible = "arm,pl011", "arm,primecell";
 173                         reg = <0xfff36000 0x1000>;
 174                         interrupts = <0 20 4>;
 175                 };
 176
 177                 smic@fff3a000 {
 178                         compatible = "ipmi-smic";
 179                         device_type = "ipmi";
 180                         reg = <0xfff3a000 0x1000>;
 181                         interrupts = <0 24 4>;
 182                         reg-size = <4>;
 183                         reg-spacing = <4>;
 184                 };
 185
 186                 sregs@fff3c000 {
 187                         compatible = "calxeda,hb-sregs";
 188                         reg = <0xfff3c000 0x1000>;
 189                 };
 190
 191                 dma@fff3d000 {
 192                         compatible = "arm,pl330", "arm,primecell";
 193                         reg = <0xfff3d000 0x1000>;
 194                         interrupts = <0 92 4>;
 195                 };
 196
 197                 ethernet@fff50000 {
 198                         compatible = "calxeda,hb-xgmac";
 199                         reg = <0xfff50000 0x1000>;
 200                         interrupts = <0 77 4  0 78 4  0 79 4>;
 201                 };
 202
 203                 ethernet@fff51000 {
 204                         compatible = "calxeda,hb-xgmac";
 205                         reg = <0xfff51000 0x1000>;
 206                         interrupts = <0 80 4  0 81 4  0 82 4>;
 207                 };
 208         };
 209 };