2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <dt-bindings/gpio/gpio.h>
13 #include "imx28-pinfunc.h"
19 interrupt-parent = <&icoll>;
21 * The decompressor and also some bootloaders rely on a
22 * pre-existing /chosen node to be available to insert the
23 * command line and merge other ATAGS info.
24 * Also for U-Boot there must be a pre-existing /memory node.
27 memory { device_type = "memory"; reg = <0 0>; };
55 compatible = "arm,arm926ej-s";
62 compatible = "simple-bus";
65 reg = <0x80000000 0x80000>;
69 compatible = "simple-bus";
72 reg = <0x80000000 0x3c900>;
75 icoll: interrupt-controller@80000000 {
76 compatible = "fsl,imx28-icoll", "fsl,icoll";
78 #interrupt-cells = <1>;
79 reg = <0x80000000 0x2000>;
82 hsadc: hsadc@80002000 {
83 reg = <0x80002000 0x2000>;
85 dmas = <&dma_apbh 12>;
90 dma_apbh: dma-apbh@80004000 {
91 compatible = "fsl,imx28-dma-apbh";
92 reg = <0x80004000 0x2000>;
93 interrupts = <82 83 84 85
97 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
98 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
99 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
100 "hsadc", "lcdif", "empty", "empty";
106 perfmon: perfmon@80006000 {
107 reg = <0x80006000 0x800>;
112 gpmi: gpmi-nand@8000c000 {
113 compatible = "fsl,imx28-gpmi-nand";
114 #address-cells = <1>;
116 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
117 reg-names = "gpmi-nand", "bch";
119 interrupt-names = "bch";
121 clock-names = "gpmi_io";
122 dmas = <&dma_apbh 4>;
128 #address-cells = <1>;
130 reg = <0x80010000 0x2000>;
133 dmas = <&dma_apbh 0>;
139 #address-cells = <1>;
141 reg = <0x80012000 0x2000>;
144 dmas = <&dma_apbh 1>;
150 #address-cells = <1>;
152 reg = <0x80014000 0x2000>;
155 dmas = <&dma_apbh 2>;
161 #address-cells = <1>;
163 reg = <0x80016000 0x2000>;
166 dmas = <&dma_apbh 3>;
171 pinctrl: pinctrl@80018000 {
172 #address-cells = <1>;
174 compatible = "fsl,imx28-pinctrl", "simple-bus";
175 reg = <0x80018000 0x2000>;
178 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
183 interrupt-controller;
184 #interrupt-cells = <2>;
188 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
193 interrupt-controller;
194 #interrupt-cells = <2>;
198 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
203 interrupt-controller;
204 #interrupt-cells = <2>;
208 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
213 interrupt-controller;
214 #interrupt-cells = <2>;
218 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
223 interrupt-controller;
224 #interrupt-cells = <2>;
227 duart_pins_a: duart@0 {
230 MX28_PAD_PWM0__DUART_RX
231 MX28_PAD_PWM1__DUART_TX
233 fsl,drive-strength = <MXS_DRIVE_4mA>;
234 fsl,voltage = <MXS_VOLTAGE_HIGH>;
235 fsl,pull-up = <MXS_PULL_DISABLE>;
238 duart_pins_b: duart@1 {
241 MX28_PAD_AUART0_CTS__DUART_RX
242 MX28_PAD_AUART0_RTS__DUART_TX
244 fsl,drive-strength = <MXS_DRIVE_4mA>;
245 fsl,voltage = <MXS_VOLTAGE_HIGH>;
246 fsl,pull-up = <MXS_PULL_DISABLE>;
249 duart_4pins_a: duart-4pins@0 {
252 MX28_PAD_AUART0_CTS__DUART_RX
253 MX28_PAD_AUART0_RTS__DUART_TX
254 MX28_PAD_AUART0_RX__DUART_CTS
255 MX28_PAD_AUART0_TX__DUART_RTS
257 fsl,drive-strength = <MXS_DRIVE_4mA>;
258 fsl,voltage = <MXS_VOLTAGE_HIGH>;
259 fsl,pull-up = <MXS_PULL_DISABLE>;
262 gpmi_pins_a: gpmi-nand@0 {
265 MX28_PAD_GPMI_D00__GPMI_D0
266 MX28_PAD_GPMI_D01__GPMI_D1
267 MX28_PAD_GPMI_D02__GPMI_D2
268 MX28_PAD_GPMI_D03__GPMI_D3
269 MX28_PAD_GPMI_D04__GPMI_D4
270 MX28_PAD_GPMI_D05__GPMI_D5
271 MX28_PAD_GPMI_D06__GPMI_D6
272 MX28_PAD_GPMI_D07__GPMI_D7
273 MX28_PAD_GPMI_CE0N__GPMI_CE0N
274 MX28_PAD_GPMI_RDY0__GPMI_READY0
275 MX28_PAD_GPMI_RDN__GPMI_RDN
276 MX28_PAD_GPMI_WRN__GPMI_WRN
277 MX28_PAD_GPMI_ALE__GPMI_ALE
278 MX28_PAD_GPMI_CLE__GPMI_CLE
279 MX28_PAD_GPMI_RESETN__GPMI_RESETN
281 fsl,drive-strength = <MXS_DRIVE_4mA>;
282 fsl,voltage = <MXS_VOLTAGE_HIGH>;
283 fsl,pull-up = <MXS_PULL_DISABLE>;
286 gpmi_status_cfg: gpmi-status-cfg {
288 MX28_PAD_GPMI_RDN__GPMI_RDN
289 MX28_PAD_GPMI_WRN__GPMI_WRN
290 MX28_PAD_GPMI_RESETN__GPMI_RESETN
292 fsl,drive-strength = <MXS_DRIVE_12mA>;
295 auart0_pins_a: auart0@0 {
298 MX28_PAD_AUART0_RX__AUART0_RX
299 MX28_PAD_AUART0_TX__AUART0_TX
300 MX28_PAD_AUART0_CTS__AUART0_CTS
301 MX28_PAD_AUART0_RTS__AUART0_RTS
303 fsl,drive-strength = <MXS_DRIVE_4mA>;
304 fsl,voltage = <MXS_VOLTAGE_HIGH>;
305 fsl,pull-up = <MXS_PULL_DISABLE>;
308 auart0_2pins_a: auart0-2pins@0 {
311 MX28_PAD_AUART0_RX__AUART0_RX
312 MX28_PAD_AUART0_TX__AUART0_TX
314 fsl,drive-strength = <MXS_DRIVE_4mA>;
315 fsl,voltage = <MXS_VOLTAGE_HIGH>;
316 fsl,pull-up = <MXS_PULL_DISABLE>;
319 auart1_pins_a: auart1@0 {
322 MX28_PAD_AUART1_RX__AUART1_RX
323 MX28_PAD_AUART1_TX__AUART1_TX
324 MX28_PAD_AUART1_CTS__AUART1_CTS
325 MX28_PAD_AUART1_RTS__AUART1_RTS
327 fsl,drive-strength = <MXS_DRIVE_4mA>;
328 fsl,voltage = <MXS_VOLTAGE_HIGH>;
329 fsl,pull-up = <MXS_PULL_DISABLE>;
332 auart1_2pins_a: auart1-2pins@0 {
335 MX28_PAD_AUART1_RX__AUART1_RX
336 MX28_PAD_AUART1_TX__AUART1_TX
338 fsl,drive-strength = <MXS_DRIVE_4mA>;
339 fsl,voltage = <MXS_VOLTAGE_HIGH>;
340 fsl,pull-up = <MXS_PULL_DISABLE>;
343 auart2_2pins_a: auart2-2pins@0 {
346 MX28_PAD_SSP2_SCK__AUART2_RX
347 MX28_PAD_SSP2_MOSI__AUART2_TX
349 fsl,drive-strength = <MXS_DRIVE_4mA>;
350 fsl,voltage = <MXS_VOLTAGE_HIGH>;
351 fsl,pull-up = <MXS_PULL_DISABLE>;
354 auart2_2pins_b: auart2-2pins@1 {
357 MX28_PAD_AUART2_RX__AUART2_RX
358 MX28_PAD_AUART2_TX__AUART2_TX
360 fsl,drive-strength = <MXS_DRIVE_4mA>;
361 fsl,voltage = <MXS_VOLTAGE_HIGH>;
362 fsl,pull-up = <MXS_PULL_DISABLE>;
365 auart2_pins_a: auart2-pins@0 {
368 MX28_PAD_AUART2_RX__AUART2_RX
369 MX28_PAD_AUART2_TX__AUART2_TX
370 MX28_PAD_AUART2_CTS__AUART2_CTS
371 MX28_PAD_AUART2_RTS__AUART2_RTS
373 fsl,drive-strength = <MXS_DRIVE_4mA>;
374 fsl,voltage = <MXS_VOLTAGE_HIGH>;
375 fsl,pull-up = <MXS_PULL_DISABLE>;
378 auart3_pins_a: auart3@0 {
381 MX28_PAD_AUART3_RX__AUART3_RX
382 MX28_PAD_AUART3_TX__AUART3_TX
383 MX28_PAD_AUART3_CTS__AUART3_CTS
384 MX28_PAD_AUART3_RTS__AUART3_RTS
386 fsl,drive-strength = <MXS_DRIVE_4mA>;
387 fsl,voltage = <MXS_VOLTAGE_HIGH>;
388 fsl,pull-up = <MXS_PULL_DISABLE>;
391 auart3_2pins_a: auart3-2pins@0 {
394 MX28_PAD_SSP2_MISO__AUART3_RX
395 MX28_PAD_SSP2_SS0__AUART3_TX
397 fsl,drive-strength = <MXS_DRIVE_4mA>;
398 fsl,voltage = <MXS_VOLTAGE_HIGH>;
399 fsl,pull-up = <MXS_PULL_DISABLE>;
402 auart3_2pins_b: auart3-2pins@1 {
405 MX28_PAD_AUART3_RX__AUART3_RX
406 MX28_PAD_AUART3_TX__AUART3_TX
408 fsl,drive-strength = <MXS_DRIVE_4mA>;
409 fsl,voltage = <MXS_VOLTAGE_HIGH>;
410 fsl,pull-up = <MXS_PULL_DISABLE>;
413 auart4_2pins_a: auart4@0 {
416 MX28_PAD_SSP3_SCK__AUART4_TX
417 MX28_PAD_SSP3_MOSI__AUART4_RX
419 fsl,drive-strength = <MXS_DRIVE_4mA>;
420 fsl,voltage = <MXS_VOLTAGE_HIGH>;
421 fsl,pull-up = <MXS_PULL_DISABLE>;
424 auart4_2pins_b: auart4@1 {
427 MX28_PAD_AUART0_CTS__AUART4_RX
428 MX28_PAD_AUART0_RTS__AUART4_TX
430 fsl,drive-strength = <MXS_DRIVE_4mA>;
431 fsl,voltage = <MXS_VOLTAGE_HIGH>;
432 fsl,pull-up = <MXS_PULL_DISABLE>;
435 mac0_pins_a: mac0@0 {
438 MX28_PAD_ENET0_MDC__ENET0_MDC
439 MX28_PAD_ENET0_MDIO__ENET0_MDIO
440 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
441 MX28_PAD_ENET0_RXD0__ENET0_RXD0
442 MX28_PAD_ENET0_RXD1__ENET0_RXD1
443 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
444 MX28_PAD_ENET0_TXD0__ENET0_TXD0
445 MX28_PAD_ENET0_TXD1__ENET0_TXD1
446 MX28_PAD_ENET_CLK__CLKCTRL_ENET
448 fsl,drive-strength = <MXS_DRIVE_8mA>;
449 fsl,voltage = <MXS_VOLTAGE_HIGH>;
450 fsl,pull-up = <MXS_PULL_ENABLE>;
453 mac0_pins_b: mac0@1 {
456 MX28_PAD_ENET0_MDC__ENET0_MDC
457 MX28_PAD_ENET0_MDIO__ENET0_MDIO
458 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
459 MX28_PAD_ENET0_RXD0__ENET0_RXD0
460 MX28_PAD_ENET0_RXD1__ENET0_RXD1
461 MX28_PAD_ENET0_RXD2__ENET0_RXD2
462 MX28_PAD_ENET0_RXD3__ENET0_RXD3
463 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
464 MX28_PAD_ENET0_TXD0__ENET0_TXD0
465 MX28_PAD_ENET0_TXD1__ENET0_TXD1
466 MX28_PAD_ENET0_TXD2__ENET0_TXD2
467 MX28_PAD_ENET0_TXD3__ENET0_TXD3
468 MX28_PAD_ENET_CLK__CLKCTRL_ENET
469 MX28_PAD_ENET0_COL__ENET0_COL
470 MX28_PAD_ENET0_CRS__ENET0_CRS
471 MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
472 MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
474 fsl,drive-strength = <MXS_DRIVE_8mA>;
475 fsl,voltage = <MXS_VOLTAGE_HIGH>;
476 fsl,pull-up = <MXS_PULL_ENABLE>;
479 mac1_pins_a: mac1@0 {
482 MX28_PAD_ENET0_CRS__ENET1_RX_EN
483 MX28_PAD_ENET0_RXD2__ENET1_RXD0
484 MX28_PAD_ENET0_RXD3__ENET1_RXD1
485 MX28_PAD_ENET0_COL__ENET1_TX_EN
486 MX28_PAD_ENET0_TXD2__ENET1_TXD0
487 MX28_PAD_ENET0_TXD3__ENET1_TXD1
489 fsl,drive-strength = <MXS_DRIVE_8mA>;
490 fsl,voltage = <MXS_VOLTAGE_HIGH>;
491 fsl,pull-up = <MXS_PULL_ENABLE>;
494 mmc0_8bit_pins_a: mmc0-8bit@0 {
497 MX28_PAD_SSP0_DATA0__SSP0_D0
498 MX28_PAD_SSP0_DATA1__SSP0_D1
499 MX28_PAD_SSP0_DATA2__SSP0_D2
500 MX28_PAD_SSP0_DATA3__SSP0_D3
501 MX28_PAD_SSP0_DATA4__SSP0_D4
502 MX28_PAD_SSP0_DATA5__SSP0_D5
503 MX28_PAD_SSP0_DATA6__SSP0_D6
504 MX28_PAD_SSP0_DATA7__SSP0_D7
505 MX28_PAD_SSP0_CMD__SSP0_CMD
506 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
507 MX28_PAD_SSP0_SCK__SSP0_SCK
509 fsl,drive-strength = <MXS_DRIVE_8mA>;
510 fsl,voltage = <MXS_VOLTAGE_HIGH>;
511 fsl,pull-up = <MXS_PULL_ENABLE>;
514 mmc0_4bit_pins_a: mmc0-4bit@0 {
517 MX28_PAD_SSP0_DATA0__SSP0_D0
518 MX28_PAD_SSP0_DATA1__SSP0_D1
519 MX28_PAD_SSP0_DATA2__SSP0_D2
520 MX28_PAD_SSP0_DATA3__SSP0_D3
521 MX28_PAD_SSP0_CMD__SSP0_CMD
522 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
523 MX28_PAD_SSP0_SCK__SSP0_SCK
525 fsl,drive-strength = <MXS_DRIVE_8mA>;
526 fsl,voltage = <MXS_VOLTAGE_HIGH>;
527 fsl,pull-up = <MXS_PULL_ENABLE>;
530 mmc0_cd_cfg: mmc0-cd-cfg {
532 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
534 fsl,pull-up = <MXS_PULL_DISABLE>;
537 mmc0_sck_cfg: mmc0-sck-cfg {
539 MX28_PAD_SSP0_SCK__SSP0_SCK
541 fsl,drive-strength = <MXS_DRIVE_12mA>;
542 fsl,pull-up = <MXS_PULL_DISABLE>;
545 mmc1_4bit_pins_a: mmc1-4bit@0 {
548 MX28_PAD_GPMI_D00__SSP1_D0
549 MX28_PAD_GPMI_D01__SSP1_D1
550 MX28_PAD_GPMI_D02__SSP1_D2
551 MX28_PAD_GPMI_D03__SSP1_D3
552 MX28_PAD_GPMI_RDY1__SSP1_CMD
553 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
554 MX28_PAD_GPMI_WRN__SSP1_SCK
556 fsl,drive-strength = <MXS_DRIVE_8mA>;
557 fsl,voltage = <MXS_VOLTAGE_HIGH>;
558 fsl,pull-up = <MXS_PULL_ENABLE>;
561 mmc1_cd_cfg: mmc1-cd-cfg {
563 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
565 fsl,pull-up = <MXS_PULL_DISABLE>;
568 mmc1_sck_cfg: mmc1-sck-cfg {
570 MX28_PAD_GPMI_WRN__SSP1_SCK
572 fsl,drive-strength = <MXS_DRIVE_12mA>;
573 fsl,pull-up = <MXS_PULL_DISABLE>;
577 mmc2_4bit_pins_a: mmc2-4bit@0 {
580 MX28_PAD_SSP0_DATA4__SSP2_D0
581 MX28_PAD_SSP1_SCK__SSP2_D1
582 MX28_PAD_SSP1_CMD__SSP2_D2
583 MX28_PAD_SSP0_DATA5__SSP2_D3
584 MX28_PAD_SSP0_DATA6__SSP2_CMD
585 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
586 MX28_PAD_SSP0_DATA7__SSP2_SCK
588 fsl,drive-strength = <MXS_DRIVE_8mA>;
589 fsl,voltage = <MXS_VOLTAGE_HIGH>;
590 fsl,pull-up = <MXS_PULL_ENABLE>;
593 mmc2_cd_cfg: mmc2-cd-cfg {
595 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
597 fsl,pull-up = <MXS_PULL_DISABLE>;
600 mmc2_sck_cfg: mmc2-sck-cfg {
602 MX28_PAD_SSP0_DATA7__SSP2_SCK
604 fsl,drive-strength = <MXS_DRIVE_12mA>;
605 fsl,pull-up = <MXS_PULL_DISABLE>;
608 i2c0_pins_a: i2c0@0 {
611 MX28_PAD_I2C0_SCL__I2C0_SCL
612 MX28_PAD_I2C0_SDA__I2C0_SDA
614 fsl,drive-strength = <MXS_DRIVE_8mA>;
615 fsl,voltage = <MXS_VOLTAGE_HIGH>;
616 fsl,pull-up = <MXS_PULL_ENABLE>;
619 i2c0_pins_b: i2c0@1 {
622 MX28_PAD_AUART0_RX__I2C0_SCL
623 MX28_PAD_AUART0_TX__I2C0_SDA
625 fsl,drive-strength = <MXS_DRIVE_8mA>;
626 fsl,voltage = <MXS_VOLTAGE_HIGH>;
627 fsl,pull-up = <MXS_PULL_ENABLE>;
630 i2c1_pins_a: i2c1@0 {
633 MX28_PAD_PWM0__I2C1_SCL
634 MX28_PAD_PWM1__I2C1_SDA
636 fsl,drive-strength = <MXS_DRIVE_8mA>;
637 fsl,voltage = <MXS_VOLTAGE_HIGH>;
638 fsl,pull-up = <MXS_PULL_ENABLE>;
641 i2c1_pins_b: i2c1@1 {
644 MX28_PAD_AUART2_CTS__I2C1_SCL
645 MX28_PAD_AUART2_RTS__I2C1_SDA
647 fsl,drive-strength = <MXS_DRIVE_8mA>;
648 fsl,voltage = <MXS_VOLTAGE_HIGH>;
649 fsl,pull-up = <MXS_PULL_ENABLE>;
652 saif0_pins_a: saif0@0 {
655 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
656 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
657 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
658 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
660 fsl,drive-strength = <MXS_DRIVE_12mA>;
661 fsl,voltage = <MXS_VOLTAGE_HIGH>;
662 fsl,pull-up = <MXS_PULL_ENABLE>;
665 saif0_pins_b: saif0@1 {
668 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
669 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
670 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
672 fsl,drive-strength = <MXS_DRIVE_12mA>;
673 fsl,voltage = <MXS_VOLTAGE_HIGH>;
674 fsl,pull-up = <MXS_PULL_ENABLE>;
677 saif1_pins_a: saif1@0 {
680 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
682 fsl,drive-strength = <MXS_DRIVE_12mA>;
683 fsl,voltage = <MXS_VOLTAGE_HIGH>;
684 fsl,pull-up = <MXS_PULL_ENABLE>;
687 pwm0_pins_a: pwm0@0 {
692 fsl,drive-strength = <MXS_DRIVE_4mA>;
693 fsl,voltage = <MXS_VOLTAGE_HIGH>;
694 fsl,pull-up = <MXS_PULL_DISABLE>;
697 pwm2_pins_a: pwm2@0 {
702 fsl,drive-strength = <MXS_DRIVE_4mA>;
703 fsl,voltage = <MXS_VOLTAGE_HIGH>;
704 fsl,pull-up = <MXS_PULL_DISABLE>;
707 pwm3_pins_a: pwm3@0 {
712 fsl,drive-strength = <MXS_DRIVE_4mA>;
713 fsl,voltage = <MXS_VOLTAGE_HIGH>;
714 fsl,pull-up = <MXS_PULL_DISABLE>;
717 pwm3_pins_b: pwm3@1 {
720 MX28_PAD_SAIF0_MCLK__PWM_3
722 fsl,drive-strength = <MXS_DRIVE_4mA>;
723 fsl,voltage = <MXS_VOLTAGE_HIGH>;
724 fsl,pull-up = <MXS_PULL_DISABLE>;
727 pwm4_pins_a: pwm4@0 {
732 fsl,drive-strength = <MXS_DRIVE_4mA>;
733 fsl,voltage = <MXS_VOLTAGE_HIGH>;
734 fsl,pull-up = <MXS_PULL_DISABLE>;
737 lcdif_24bit_pins_a: lcdif-24bit@0 {
740 MX28_PAD_LCD_D00__LCD_D0
741 MX28_PAD_LCD_D01__LCD_D1
742 MX28_PAD_LCD_D02__LCD_D2
743 MX28_PAD_LCD_D03__LCD_D3
744 MX28_PAD_LCD_D04__LCD_D4
745 MX28_PAD_LCD_D05__LCD_D5
746 MX28_PAD_LCD_D06__LCD_D6
747 MX28_PAD_LCD_D07__LCD_D7
748 MX28_PAD_LCD_D08__LCD_D8
749 MX28_PAD_LCD_D09__LCD_D9
750 MX28_PAD_LCD_D10__LCD_D10
751 MX28_PAD_LCD_D11__LCD_D11
752 MX28_PAD_LCD_D12__LCD_D12
753 MX28_PAD_LCD_D13__LCD_D13
754 MX28_PAD_LCD_D14__LCD_D14
755 MX28_PAD_LCD_D15__LCD_D15
756 MX28_PAD_LCD_D16__LCD_D16
757 MX28_PAD_LCD_D17__LCD_D17
758 MX28_PAD_LCD_D18__LCD_D18
759 MX28_PAD_LCD_D19__LCD_D19
760 MX28_PAD_LCD_D20__LCD_D20
761 MX28_PAD_LCD_D21__LCD_D21
762 MX28_PAD_LCD_D22__LCD_D22
763 MX28_PAD_LCD_D23__LCD_D23
765 fsl,drive-strength = <MXS_DRIVE_4mA>;
766 fsl,voltage = <MXS_VOLTAGE_HIGH>;
767 fsl,pull-up = <MXS_PULL_DISABLE>;
770 lcdif_18bit_pins_a: lcdif-18bit@0 {
773 MX28_PAD_LCD_D00__LCD_D0
774 MX28_PAD_LCD_D01__LCD_D1
775 MX28_PAD_LCD_D02__LCD_D2
776 MX28_PAD_LCD_D03__LCD_D3
777 MX28_PAD_LCD_D04__LCD_D4
778 MX28_PAD_LCD_D05__LCD_D5
779 MX28_PAD_LCD_D06__LCD_D6
780 MX28_PAD_LCD_D07__LCD_D7
781 MX28_PAD_LCD_D08__LCD_D8
782 MX28_PAD_LCD_D09__LCD_D9
783 MX28_PAD_LCD_D10__LCD_D10
784 MX28_PAD_LCD_D11__LCD_D11
785 MX28_PAD_LCD_D12__LCD_D12
786 MX28_PAD_LCD_D13__LCD_D13
787 MX28_PAD_LCD_D14__LCD_D14
788 MX28_PAD_LCD_D15__LCD_D15
789 MX28_PAD_LCD_D16__LCD_D16
790 MX28_PAD_LCD_D17__LCD_D17
792 fsl,drive-strength = <MXS_DRIVE_4mA>;
793 fsl,voltage = <MXS_VOLTAGE_HIGH>;
794 fsl,pull-up = <MXS_PULL_DISABLE>;
797 lcdif_16bit_pins_a: lcdif-16bit@0 {
800 MX28_PAD_LCD_D00__LCD_D0
801 MX28_PAD_LCD_D01__LCD_D1
802 MX28_PAD_LCD_D02__LCD_D2
803 MX28_PAD_LCD_D03__LCD_D3
804 MX28_PAD_LCD_D04__LCD_D4
805 MX28_PAD_LCD_D05__LCD_D5
806 MX28_PAD_LCD_D06__LCD_D6
807 MX28_PAD_LCD_D07__LCD_D7
808 MX28_PAD_LCD_D08__LCD_D8
809 MX28_PAD_LCD_D09__LCD_D9
810 MX28_PAD_LCD_D10__LCD_D10
811 MX28_PAD_LCD_D11__LCD_D11
812 MX28_PAD_LCD_D12__LCD_D12
813 MX28_PAD_LCD_D13__LCD_D13
814 MX28_PAD_LCD_D14__LCD_D14
815 MX28_PAD_LCD_D15__LCD_D15
817 fsl,drive-strength = <MXS_DRIVE_4mA>;
818 fsl,voltage = <MXS_VOLTAGE_HIGH>;
819 fsl,pull-up = <MXS_PULL_DISABLE>;
822 lcdif_sync_pins_a: lcdif-sync@0 {
825 MX28_PAD_LCD_RS__LCD_DOTCLK
826 MX28_PAD_LCD_CS__LCD_ENABLE
827 MX28_PAD_LCD_RD_E__LCD_VSYNC
828 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
830 fsl,drive-strength = <MXS_DRIVE_4mA>;
831 fsl,voltage = <MXS_VOLTAGE_HIGH>;
832 fsl,pull-up = <MXS_PULL_DISABLE>;
835 can0_pins_a: can0@0 {
838 MX28_PAD_GPMI_RDY2__CAN0_TX
839 MX28_PAD_GPMI_RDY3__CAN0_RX
841 fsl,drive-strength = <MXS_DRIVE_4mA>;
842 fsl,voltage = <MXS_VOLTAGE_HIGH>;
843 fsl,pull-up = <MXS_PULL_DISABLE>;
846 can1_pins_a: can1@0 {
849 MX28_PAD_GPMI_CE2N__CAN1_TX
850 MX28_PAD_GPMI_CE3N__CAN1_RX
852 fsl,drive-strength = <MXS_DRIVE_4mA>;
853 fsl,voltage = <MXS_VOLTAGE_HIGH>;
854 fsl,pull-up = <MXS_PULL_DISABLE>;
857 spi2_pins_a: spi2@0 {
860 MX28_PAD_SSP2_SCK__SSP2_SCK
861 MX28_PAD_SSP2_MOSI__SSP2_CMD
862 MX28_PAD_SSP2_MISO__SSP2_D0
863 MX28_PAD_SSP2_SS0__SSP2_D3
865 fsl,drive-strength = <MXS_DRIVE_8mA>;
866 fsl,voltage = <MXS_VOLTAGE_HIGH>;
867 fsl,pull-up = <MXS_PULL_ENABLE>;
870 spi3_pins_a: spi3@0 {
873 MX28_PAD_AUART2_RX__SSP3_D4
874 MX28_PAD_AUART2_TX__SSP3_D5
875 MX28_PAD_SSP3_SCK__SSP3_SCK
876 MX28_PAD_SSP3_MOSI__SSP3_CMD
877 MX28_PAD_SSP3_MISO__SSP3_D0
878 MX28_PAD_SSP3_SS0__SSP3_D3
880 fsl,drive-strength = <MXS_DRIVE_8mA>;
881 fsl,voltage = <MXS_VOLTAGE_HIGH>;
882 fsl,pull-up = <MXS_PULL_DISABLE>;
885 spi3_pins_b: spi3@1 {
888 MX28_PAD_SSP3_SCK__SSP3_SCK
889 MX28_PAD_SSP3_MOSI__SSP3_CMD
890 MX28_PAD_SSP3_MISO__SSP3_D0
891 MX28_PAD_SSP3_SS0__SSP3_D3
893 fsl,drive-strength = <MXS_DRIVE_8mA>;
894 fsl,voltage = <MXS_VOLTAGE_HIGH>;
895 fsl,pull-up = <MXS_PULL_ENABLE>;
898 usb0_pins_a: usb0@0 {
901 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
903 fsl,drive-strength = <MXS_DRIVE_12mA>;
904 fsl,voltage = <MXS_VOLTAGE_HIGH>;
905 fsl,pull-up = <MXS_PULL_DISABLE>;
908 usb0_pins_b: usb0@1 {
911 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
913 fsl,drive-strength = <MXS_DRIVE_12mA>;
914 fsl,voltage = <MXS_VOLTAGE_HIGH>;
915 fsl,pull-up = <MXS_PULL_DISABLE>;
918 usb1_pins_a: usb1@0 {
921 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
923 fsl,drive-strength = <MXS_DRIVE_12mA>;
924 fsl,voltage = <MXS_VOLTAGE_HIGH>;
925 fsl,pull-up = <MXS_PULL_DISABLE>;
928 usb0_id_pins_a: usb0id@0 {
931 MX28_PAD_AUART1_RTS__USB0_ID
933 fsl,drive-strength = <MXS_DRIVE_12mA>;
934 fsl,voltage = <MXS_VOLTAGE_HIGH>;
935 fsl,pull-up = <MXS_PULL_ENABLE>;
938 usb0_id_pins_b: usb0id1@0 {
941 MX28_PAD_PWM2__USB0_ID
943 fsl,drive-strength = <MXS_DRIVE_12mA>;
944 fsl,voltage = <MXS_VOLTAGE_HIGH>;
945 fsl,pull-up = <MXS_PULL_ENABLE>;
950 digctl: digctl@8001c000 {
951 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
952 reg = <0x8001c000 0x2000>;
958 reg = <0x80022000 0x2000>;
962 dma_apbx: dma-apbx@80024000 {
963 compatible = "fsl,imx28-dma-apbx";
964 reg = <0x80024000 0x2000>;
965 interrupts = <78 79 66 0
969 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
970 "saif0", "saif1", "i2c0", "i2c1",
971 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
972 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
979 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
980 reg = <0x80028000 0x2000>;
981 interrupts = <52 53 54>;
986 reg = <0x8002a000 0x2000>;
991 ocotp: ocotp@8002c000 {
992 compatible = "fsl,imx28-ocotp", "fsl,ocotp";
993 #address-cells = <1>;
995 reg = <0x8002c000 0x2000>;
1000 reg = <0x8002e000 0x2000>;
1001 status = "disabled";
1004 lcdif: lcdif@80030000 {
1005 compatible = "fsl,imx28-lcdif";
1006 reg = <0x80030000 0x2000>;
1008 clocks = <&clks 55>;
1009 dmas = <&dma_apbh 13>;
1011 status = "disabled";
1014 can0: can@80032000 {
1015 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
1016 reg = <0x80032000 0x2000>;
1018 clocks = <&clks 58>, <&clks 58>;
1019 clock-names = "ipg", "per";
1020 status = "disabled";
1023 can1: can@80034000 {
1024 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
1025 reg = <0x80034000 0x2000>;
1027 clocks = <&clks 59>, <&clks 59>;
1028 clock-names = "ipg", "per";
1029 status = "disabled";
1032 simdbg: simdbg@8003c000 {
1033 reg = <0x8003c000 0x200>;
1034 status = "disabled";
1037 simgpmisel: simgpmisel@8003c200 {
1038 reg = <0x8003c200 0x100>;
1039 status = "disabled";
1042 simsspsel: simsspsel@8003c300 {
1043 reg = <0x8003c300 0x100>;
1044 status = "disabled";
1047 simmemsel: simmemsel@8003c400 {
1048 reg = <0x8003c400 0x100>;
1049 status = "disabled";
1052 gpiomon: gpiomon@8003c500 {
1053 reg = <0x8003c500 0x100>;
1054 status = "disabled";
1057 simenet: simenet@8003c700 {
1058 reg = <0x8003c700 0x100>;
1059 status = "disabled";
1062 armjtag: armjtag@8003c800 {
1063 reg = <0x8003c800 0x100>;
1064 status = "disabled";
1069 compatible = "simple-bus";
1070 #address-cells = <1>;
1072 reg = <0x80040000 0x40000>;
1075 clks: clkctrl@80040000 {
1076 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
1077 reg = <0x80040000 0x2000>;
1081 saif0: saif@80042000 {
1082 #sound-dai-cells = <0>;
1083 compatible = "fsl,imx28-saif";
1084 reg = <0x80042000 0x2000>;
1087 clocks = <&clks 53>;
1088 dmas = <&dma_apbx 4>;
1089 dma-names = "rx-tx";
1090 status = "disabled";
1093 power: power@80044000 {
1094 reg = <0x80044000 0x2000>;
1095 status = "disabled";
1098 saif1: saif@80046000 {
1099 #sound-dai-cells = <0>;
1100 compatible = "fsl,imx28-saif";
1101 reg = <0x80046000 0x2000>;
1103 clocks = <&clks 54>;
1104 dmas = <&dma_apbx 5>;
1105 dma-names = "rx-tx";
1106 status = "disabled";
1109 lradc: lradc@80050000 {
1110 compatible = "fsl,imx28-lradc";
1111 reg = <0x80050000 0x2000>;
1112 interrupts = <10 14 15 16 17 18 19
1114 status = "disabled";
1115 clocks = <&clks 41>;
1116 #io-channel-cells = <1>;
1119 spdif: spdif@80054000 {
1120 reg = <0x80054000 0x2000>;
1122 dmas = <&dma_apbx 2>;
1124 status = "disabled";
1127 mxs_rtc: rtc@80056000 {
1128 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
1129 reg = <0x80056000 0x2000>;
1133 i2c0: i2c@80058000 {
1134 #address-cells = <1>;
1136 compatible = "fsl,imx28-i2c";
1137 reg = <0x80058000 0x2000>;
1139 clock-frequency = <100000>;
1140 dmas = <&dma_apbx 6>;
1141 dma-names = "rx-tx";
1142 status = "disabled";
1145 i2c1: i2c@8005a000 {
1146 #address-cells = <1>;
1148 compatible = "fsl,imx28-i2c";
1149 reg = <0x8005a000 0x2000>;
1151 clock-frequency = <100000>;
1152 dmas = <&dma_apbx 7>;
1153 dma-names = "rx-tx";
1154 status = "disabled";
1158 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
1159 reg = <0x80064000 0x2000>;
1160 clocks = <&clks 44>;
1162 fsl,pwm-number = <8>;
1163 status = "disabled";
1166 timer: timrot@80068000 {
1167 compatible = "fsl,imx28-timrot", "fsl,timrot";
1168 reg = <0x80068000 0x2000>;
1169 interrupts = <48 49 50 51>;
1170 clocks = <&clks 26>;
1173 auart0: serial@8006a000 {
1174 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1175 reg = <0x8006a000 0x2000>;
1177 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1178 dma-names = "rx", "tx";
1179 clocks = <&clks 45>;
1180 status = "disabled";
1183 auart1: serial@8006c000 {
1184 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1185 reg = <0x8006c000 0x2000>;
1187 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1188 dma-names = "rx", "tx";
1189 clocks = <&clks 45>;
1190 status = "disabled";
1193 auart2: serial@8006e000 {
1194 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1195 reg = <0x8006e000 0x2000>;
1197 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1198 dma-names = "rx", "tx";
1199 clocks = <&clks 45>;
1200 status = "disabled";
1203 auart3: serial@80070000 {
1204 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1205 reg = <0x80070000 0x2000>;
1207 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1208 dma-names = "rx", "tx";
1209 clocks = <&clks 45>;
1210 status = "disabled";
1213 auart4: serial@80072000 {
1214 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1215 reg = <0x80072000 0x2000>;
1217 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1218 dma-names = "rx", "tx";
1219 clocks = <&clks 45>;
1220 status = "disabled";
1223 duart: serial@80074000 {
1224 compatible = "arm,pl011", "arm,primecell";
1225 reg = <0x80074000 0x1000>;
1227 clocks = <&clks 45>, <&clks 26>;
1228 clock-names = "uart", "apb_pclk";
1229 status = "disabled";
1232 usbphy0: usbphy@8007c000 {
1233 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1234 reg = <0x8007c000 0x2000>;
1235 clocks = <&clks 62>;
1236 status = "disabled";
1239 usbphy1: usbphy@8007e000 {
1240 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1241 reg = <0x8007e000 0x2000>;
1242 clocks = <&clks 63>;
1243 status = "disabled";
1249 compatible = "simple-bus";
1250 #address-cells = <1>;
1252 reg = <0x80080000 0x80000>;
1255 usb0: usb@80080000 {
1256 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1257 reg = <0x80080000 0x10000>;
1259 clocks = <&clks 60>;
1260 fsl,usbphy = <&usbphy0>;
1261 status = "disabled";
1264 usb1: usb@80090000 {
1265 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1266 reg = <0x80090000 0x10000>;
1268 clocks = <&clks 61>;
1269 fsl,usbphy = <&usbphy1>;
1271 status = "disabled";
1274 dflpt: dflpt@800c0000 {
1275 reg = <0x800c0000 0x10000>;
1276 status = "disabled";
1279 mac0: ethernet@800f0000 {
1280 compatible = "fsl,imx28-fec";
1281 reg = <0x800f0000 0x4000>;
1283 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1284 clock-names = "ipg", "ahb", "enet_out";
1285 status = "disabled";
1288 mac1: ethernet@800f4000 {
1289 compatible = "fsl,imx28-fec";
1290 reg = <0x800f4000 0x4000>;
1292 clocks = <&clks 57>, <&clks 57>;
1293 clock-names = "ipg", "ahb";
1294 status = "disabled";
1297 etn_switch: switch@800f8000 {
1298 reg = <0x800f8000 0x8000>;
1299 status = "disabled";
1304 compatible = "iio-hwmon";
1305 io-channels = <&lradc 8>;