2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 /include/ "skeleton.dtsi"
15 interrupt-parent = <&icoll>;
36 compatible = "arm,arm926ejs";
41 compatible = "simple-bus";
44 reg = <0x80000000 0x80000>;
48 compatible = "simple-bus";
51 reg = <0x80000000 0x3c900>;
54 icoll: interrupt-controller@80000000 {
55 compatible = "fsl,imx28-icoll", "fsl,icoll";
57 #interrupt-cells = <1>;
58 reg = <0x80000000 0x2000>;
62 reg = <0x80002000 0x2000>;
68 compatible = "fsl,imx28-dma-apbh";
69 reg = <0x80004000 0x2000>;
74 reg = <0x80006000 0x800>;
80 compatible = "fsl,imx28-gpmi-nand";
83 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
84 reg-names = "gpmi-nand", "bch";
85 interrupts = <88>, <41>;
86 interrupt-names = "gpmi-dma", "bch";
88 fsl,gpmi-dma-channel = <4>;
95 reg = <0x80010000 0x2000>;
98 fsl,ssp-dma-channel = <0>;
103 #address-cells = <1>;
105 reg = <0x80012000 0x2000>;
106 interrupts = <97 83>;
108 fsl,ssp-dma-channel = <1>;
113 #address-cells = <1>;
115 reg = <0x80014000 0x2000>;
116 interrupts = <98 84>;
118 fsl,ssp-dma-channel = <2>;
123 #address-cells = <1>;
125 reg = <0x80016000 0x2000>;
126 interrupts = <99 85>;
128 fsl,ssp-dma-channel = <3>;
133 #address-cells = <1>;
135 compatible = "fsl,imx28-pinctrl", "simple-bus";
136 reg = <0x80018000 0x2000>;
139 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
143 interrupt-controller;
144 #interrupt-cells = <2>;
148 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
152 interrupt-controller;
153 #interrupt-cells = <2>;
157 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
161 interrupt-controller;
162 #interrupt-cells = <2>;
166 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
170 interrupt-controller;
171 #interrupt-cells = <2>;
175 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
179 interrupt-controller;
180 #interrupt-cells = <2>;
183 duart_pins_a: duart@0 {
186 0x3102 /* MX28_PAD_PWM0__DUART_RX */
187 0x3112 /* MX28_PAD_PWM1__DUART_TX */
189 fsl,drive-strength = <0>;
194 duart_pins_b: duart@1 {
197 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
198 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
200 fsl,drive-strength = <0>;
205 duart_4pins_a: duart-4pins@0 {
208 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
209 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
210 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
211 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
213 fsl,drive-strength = <0>;
218 gpmi_pins_a: gpmi-nand@0 {
221 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
222 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
223 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
224 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
225 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
226 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
227 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
228 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
229 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
230 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
231 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
232 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
233 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
234 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
235 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
237 fsl,drive-strength = <0>;
242 gpmi_status_cfg: gpmi-status-cfg {
244 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
245 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
246 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
248 fsl,drive-strength = <2>;
251 auart0_pins_a: auart0@0 {
254 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
255 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
256 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
257 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
259 fsl,drive-strength = <0>;
264 auart0_2pins_a: auart0-2pins@0 {
267 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
268 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
270 fsl,drive-strength = <0>;
275 auart1_pins_a: auart1@0 {
278 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
279 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
280 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
281 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
283 fsl,drive-strength = <0>;
288 auart1_2pins_a: auart1-2pins@0 {
291 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
292 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
294 fsl,drive-strength = <0>;
299 auart2_2pins_a: auart2-2pins@0 {
302 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
303 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
305 fsl,drive-strength = <0>;
310 auart3_pins_a: auart3@0 {
313 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
314 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
315 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
316 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
318 fsl,drive-strength = <0>;
323 auart3_2pins_a: auart3-2pins@0 {
326 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
327 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
329 fsl,drive-strength = <0>;
334 mac0_pins_a: mac0@0 {
337 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
338 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
339 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
340 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
341 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
342 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
343 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
344 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
345 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
347 fsl,drive-strength = <1>;
352 mac1_pins_a: mac1@0 {
355 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
356 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
357 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
358 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
359 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
360 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
362 fsl,drive-strength = <1>;
367 mmc0_8bit_pins_a: mmc0-8bit@0 {
370 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
371 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
372 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
373 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
374 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
375 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
376 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
377 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
378 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
379 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
380 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
382 fsl,drive-strength = <1>;
387 mmc0_4bit_pins_a: mmc0-4bit@0 {
390 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
391 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
392 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
393 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
394 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
395 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
396 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
398 fsl,drive-strength = <1>;
403 mmc0_cd_cfg: mmc0-cd-cfg {
405 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
410 mmc0_sck_cfg: mmc0-sck-cfg {
412 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
414 fsl,drive-strength = <2>;
418 i2c0_pins_a: i2c0@0 {
421 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
422 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
424 fsl,drive-strength = <1>;
429 i2c0_pins_b: i2c0@1 {
432 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
433 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
435 fsl,drive-strength = <1>;
440 i2c1_pins_a: i2c1@0 {
443 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
444 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
446 fsl,drive-strength = <1>;
451 saif0_pins_a: saif0@0 {
454 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
455 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
456 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
457 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
459 fsl,drive-strength = <2>;
464 saif1_pins_a: saif1@0 {
467 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
469 fsl,drive-strength = <2>;
474 pwm0_pins_a: pwm0@0 {
477 0x3100 /* MX28_PAD_PWM0__PWM_0 */
479 fsl,drive-strength = <0>;
484 pwm2_pins_a: pwm2@0 {
487 0x3120 /* MX28_PAD_PWM2__PWM_2 */
489 fsl,drive-strength = <0>;
494 pwm4_pins_a: pwm4@0 {
497 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
499 fsl,drive-strength = <0>;
504 lcdif_24bit_pins_a: lcdif-24bit@0 {
507 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
508 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
509 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
510 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
511 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
512 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
513 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
514 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
515 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
516 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
517 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
518 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
519 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
520 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
521 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
522 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
523 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
524 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
525 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
526 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
527 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
528 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
529 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
530 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
532 fsl,drive-strength = <0>;
537 can0_pins_a: can0@0 {
540 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
541 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
543 fsl,drive-strength = <0>;
548 can1_pins_a: can1@0 {
551 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
552 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
554 fsl,drive-strength = <0>;
559 spi2_pins_a: spi2@0 {
562 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
563 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
564 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
565 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
567 fsl,drive-strength = <1>;
572 usbphy0_pins_a: usbphy0@0 {
575 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
577 fsl,drive-strength = <2>;
582 usbphy0_pins_b: usbphy0@1 {
585 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
587 fsl,drive-strength = <2>;
592 usbphy1_pins_a: usbphy1@0 {
595 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
597 fsl,drive-strength = <2>;
604 reg = <0x8001c000 0x2000>;
610 reg = <0x80022000 0x2000>;
615 compatible = "fsl,imx28-dma-apbx";
616 reg = <0x80024000 0x2000>;
621 reg = <0x80028000 0x2000>;
622 interrupts = <52 53 54>;
627 reg = <0x8002a000 0x2000>;
633 reg = <0x8002c000 0x2000>;
638 reg = <0x8002e000 0x2000>;
643 compatible = "fsl,imx28-lcdif";
644 reg = <0x80030000 0x2000>;
645 interrupts = <38 86>;
651 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
652 reg = <0x80032000 0x2000>;
654 clocks = <&clks 58>, <&clks 58>;
655 clock-names = "ipg", "per";
660 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
661 reg = <0x80034000 0x2000>;
663 clocks = <&clks 59>, <&clks 59>;
664 clock-names = "ipg", "per";
669 reg = <0x8003c000 0x200>;
673 simgpmisel@8003c200 {
674 reg = <0x8003c200 0x100>;
679 reg = <0x8003c300 0x100>;
684 reg = <0x8003c400 0x100>;
689 reg = <0x8003c500 0x100>;
694 reg = <0x8003c700 0x100>;
699 reg = <0x8003c800 0x100>;
705 compatible = "simple-bus";
706 #address-cells = <1>;
708 reg = <0x80040000 0x40000>;
711 clks: clkctrl@80040000 {
712 compatible = "fsl,imx28-clkctrl";
713 reg = <0x80040000 0x2000>;
717 saif0: saif@80042000 {
718 compatible = "fsl,imx28-saif";
719 reg = <0x80042000 0x2000>;
720 interrupts = <59 80>;
722 fsl,saif-dma-channel = <4>;
727 reg = <0x80044000 0x2000>;
731 saif1: saif@80046000 {
732 compatible = "fsl,imx28-saif";
733 reg = <0x80046000 0x2000>;
734 interrupts = <58 81>;
736 fsl,saif-dma-channel = <5>;
741 compatible = "fsl,imx28-lradc";
742 reg = <0x80050000 0x2000>;
743 interrupts = <10 14 15 16 17 18 19
749 reg = <0x80054000 0x2000>;
750 interrupts = <45 66>;
755 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
756 reg = <0x80056000 0x2000>;
761 #address-cells = <1>;
763 compatible = "fsl,imx28-i2c";
764 reg = <0x80058000 0x2000>;
765 interrupts = <111 68>;
766 clock-frequency = <100000>;
767 fsl,i2c-dma-channel = <6>;
772 #address-cells = <1>;
774 compatible = "fsl,imx28-i2c";
775 reg = <0x8005a000 0x2000>;
776 interrupts = <110 69>;
777 clock-frequency = <100000>;
778 fsl,i2c-dma-channel = <7>;
783 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
784 reg = <0x80064000 0x2000>;
787 fsl,pwm-number = <8>;
792 compatible = "fsl,imx28-timrot", "fsl,timrot";
793 reg = <0x80068000 0x2000>;
794 interrupts = <48 49 50 51>;
797 auart0: serial@8006a000 {
798 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
799 reg = <0x8006a000 0x2000>;
800 interrupts = <112 70 71>;
805 auart1: serial@8006c000 {
806 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
807 reg = <0x8006c000 0x2000>;
808 interrupts = <113 72 73>;
813 auart2: serial@8006e000 {
814 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
815 reg = <0x8006e000 0x2000>;
816 interrupts = <114 74 75>;
821 auart3: serial@80070000 {
822 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
823 reg = <0x80070000 0x2000>;
824 interrupts = <115 76 77>;
829 auart4: serial@80072000 {
830 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
831 reg = <0x80072000 0x2000>;
832 interrupts = <116 78 79>;
837 duart: serial@80074000 {
838 compatible = "arm,pl011", "arm,primecell";
839 reg = <0x80074000 0x1000>;
841 clocks = <&clks 45>, <&clks 26>;
842 clock-names = "uart", "apb_pclk";
846 usbphy0: usbphy@8007c000 {
847 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
848 reg = <0x8007c000 0x2000>;
853 usbphy1: usbphy@8007e000 {
854 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
855 reg = <0x8007e000 0x2000>;
863 compatible = "simple-bus";
864 #address-cells = <1>;
866 reg = <0x80080000 0x80000>;
870 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
871 reg = <0x80080000 0x10000>;
874 fsl,usbphy = <&usbphy0>;
879 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
880 reg = <0x80090000 0x10000>;
883 fsl,usbphy = <&usbphy1>;
888 reg = <0x800c0000 0x10000>;
892 mac0: ethernet@800f0000 {
893 compatible = "fsl,imx28-fec";
894 reg = <0x800f0000 0x4000>;
896 clocks = <&clks 57>, <&clks 57>;
897 clock-names = "ipg", "ahb";
901 mac1: ethernet@800f4000 {
902 compatible = "fsl,imx28-fec";
903 reg = <0x800f4000 0x4000>;
905 clocks = <&clks 57>, <&clks 57>;
906 clock-names = "ipg", "ahb";
911 reg = <0x800f8000 0x8000>;