2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "imx51-pinfunc.h"
14 #include <dt-bindings/clock/imx5-clock.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
43 tzic: tz-interrupt-controller@e0000000 {
44 compatible = "fsl,imx51-tzic", "fsl,tzic";
46 #interrupt-cells = <1>;
47 reg = <0xe0000000 0x4000>;
55 compatible = "fsl,imx-ckil", "fixed-clock";
57 clock-frequency = <32768>;
61 compatible = "fsl,imx-ckih1", "fixed-clock";
63 clock-frequency = <0>;
67 compatible = "fsl,imx-ckih2", "fixed-clock";
69 clock-frequency = <0>;
73 compatible = "fsl,imx-osc", "fixed-clock";
75 clock-frequency = <24000000>;
84 compatible = "arm,cortex-a8";
86 clock-latency = <62500>;
87 clocks = <&clks IMX5_CLK_CPU_PODF>;
94 voltage-tolerance = <5>;
101 compatible = "simple-bus";
104 compatible = "usb-nop-xceiv";
106 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
107 clock-names = "main_clk";
112 compatible = "fsl,imx-display-subsystem";
113 ports = <&ipu_di0>, <&ipu_di1>;
117 #address-cells = <1>;
119 compatible = "simple-bus";
120 interrupt-parent = <&tzic>;
123 iram: iram@1ffe0000 {
124 compatible = "mmio-sram";
125 reg = <0x1ffe0000 0x20000>;
129 #address-cells = <1>;
131 compatible = "fsl,imx51-ipu";
132 reg = <0x40000000 0x20000000>;
133 interrupts = <11 10>;
134 clocks = <&clks IMX5_CLK_IPU_GATE>,
135 <&clks IMX5_CLK_IPU_DI0_GATE>,
136 <&clks IMX5_CLK_IPU_DI1_GATE>;
137 clock-names = "bus", "di0", "di1";
143 ipu_di0_disp0: endpoint {
150 ipu_di1_disp1: endpoint {
155 aips@70000000 { /* AIPS1 */
156 compatible = "fsl,aips-bus", "simple-bus";
157 #address-cells = <1>;
159 reg = <0x70000000 0x10000000>;
163 compatible = "fsl,spba-bus", "simple-bus";
164 #address-cells = <1>;
166 reg = <0x70000000 0x40000>;
169 esdhc1: esdhc@70004000 {
170 compatible = "fsl,imx51-esdhc";
171 reg = <0x70004000 0x4000>;
173 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
174 <&clks IMX5_CLK_DUMMY>,
175 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
176 clock-names = "ipg", "ahb", "per";
180 esdhc2: esdhc@70008000 {
181 compatible = "fsl,imx51-esdhc";
182 reg = <0x70008000 0x4000>;
184 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
185 <&clks IMX5_CLK_DUMMY>,
186 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
187 clock-names = "ipg", "ahb", "per";
192 uart3: serial@7000c000 {
193 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
194 reg = <0x7000c000 0x4000>;
196 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
197 <&clks IMX5_CLK_UART3_PER_GATE>;
198 clock-names = "ipg", "per";
202 ecspi1: ecspi@70010000 {
203 #address-cells = <1>;
205 compatible = "fsl,imx51-ecspi";
206 reg = <0x70010000 0x4000>;
208 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
209 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
210 clock-names = "ipg", "per";
215 #sound-dai-cells = <0>;
216 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
217 reg = <0x70014000 0x4000>;
219 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
220 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
221 clock-names = "ipg", "baud";
222 dmas = <&sdma 24 1 0>,
224 dma-names = "rx", "tx";
225 fsl,fifo-depth = <15>;
229 esdhc3: esdhc@70020000 {
230 compatible = "fsl,imx51-esdhc";
231 reg = <0x70020000 0x4000>;
233 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
234 <&clks IMX5_CLK_DUMMY>,
235 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
236 clock-names = "ipg", "ahb", "per";
241 esdhc4: esdhc@70024000 {
242 compatible = "fsl,imx51-esdhc";
243 reg = <0x70024000 0x4000>;
245 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
246 <&clks IMX5_CLK_DUMMY>,
247 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
248 clock-names = "ipg", "ahb", "per";
254 usbotg: usb@73f80000 {
255 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
256 reg = <0x73f80000 0x0200>;
258 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
259 fsl,usbmisc = <&usbmisc 0>;
260 fsl,usbphy = <&usbphy0>;
264 usbh1: usb@73f80200 {
265 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
266 reg = <0x73f80200 0x0200>;
268 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
269 fsl,usbmisc = <&usbmisc 1>;
274 usbh2: usb@73f80400 {
275 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
276 reg = <0x73f80400 0x0200>;
278 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
279 fsl,usbmisc = <&usbmisc 2>;
284 usbh3: usb@73f80600 {
285 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
286 reg = <0x73f80600 0x0200>;
288 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
289 fsl,usbmisc = <&usbmisc 3>;
294 usbmisc: usbmisc@73f80800 {
296 compatible = "fsl,imx51-usbmisc";
297 reg = <0x73f80800 0x200>;
298 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
301 gpio1: gpio@73f84000 {
302 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
303 reg = <0x73f84000 0x4000>;
304 interrupts = <50 51>;
307 interrupt-controller;
308 #interrupt-cells = <2>;
311 gpio2: gpio@73f88000 {
312 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
313 reg = <0x73f88000 0x4000>;
314 interrupts = <52 53>;
317 interrupt-controller;
318 #interrupt-cells = <2>;
321 gpio3: gpio@73f8c000 {
322 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
323 reg = <0x73f8c000 0x4000>;
324 interrupts = <54 55>;
327 interrupt-controller;
328 #interrupt-cells = <2>;
331 gpio4: gpio@73f90000 {
332 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
333 reg = <0x73f90000 0x4000>;
334 interrupts = <56 57>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
342 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
343 reg = <0x73f94000 0x4000>;
345 clocks = <&clks IMX5_CLK_DUMMY>;
349 wdog1: wdog@73f98000 {
350 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
351 reg = <0x73f98000 0x4000>;
353 clocks = <&clks IMX5_CLK_DUMMY>;
356 wdog2: wdog@73f9c000 {
357 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
358 reg = <0x73f9c000 0x4000>;
360 clocks = <&clks IMX5_CLK_DUMMY>;
364 gpt: timer@73fa0000 {
365 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
366 reg = <0x73fa0000 0x4000>;
368 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
369 <&clks IMX5_CLK_GPT_HF_GATE>;
370 clock-names = "ipg", "per";
373 iomuxc: iomuxc@73fa8000 {
374 compatible = "fsl,imx51-iomuxc";
375 reg = <0x73fa8000 0x4000>;
380 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
381 reg = <0x73fb4000 0x4000>;
382 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
383 <&clks IMX5_CLK_PWM1_HF_GATE>;
384 clock-names = "ipg", "per";
390 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
391 reg = <0x73fb8000 0x4000>;
392 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
393 <&clks IMX5_CLK_PWM2_HF_GATE>;
394 clock-names = "ipg", "per";
398 uart1: serial@73fbc000 {
399 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
400 reg = <0x73fbc000 0x4000>;
402 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
403 <&clks IMX5_CLK_UART1_PER_GATE>;
404 clock-names = "ipg", "per";
408 uart2: serial@73fc0000 {
409 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
410 reg = <0x73fc0000 0x4000>;
412 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
413 <&clks IMX5_CLK_UART2_PER_GATE>;
414 clock-names = "ipg", "per";
419 compatible = "fsl,imx51-src";
420 reg = <0x73fd0000 0x4000>;
425 compatible = "fsl,imx51-ccm";
426 reg = <0x73fd4000 0x4000>;
427 interrupts = <0 71 0x04 0 72 0x04>;
432 aips@80000000 { /* AIPS2 */
433 compatible = "fsl,aips-bus", "simple-bus";
434 #address-cells = <1>;
436 reg = <0x80000000 0x10000000>;
440 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
441 reg = <0x83f98000 0x4000>;
443 clocks = <&clks IMX5_CLK_IIM_GATE>;
446 owire: owire@83fa4000 {
447 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
448 reg = <0x83fa4000 0x4000>;
450 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
454 ecspi2: ecspi@83fac000 {
455 #address-cells = <1>;
457 compatible = "fsl,imx51-ecspi";
458 reg = <0x83fac000 0x4000>;
460 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
461 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
462 clock-names = "ipg", "per";
466 sdma: sdma@83fb0000 {
467 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
468 reg = <0x83fb0000 0x4000>;
470 clocks = <&clks IMX5_CLK_SDMA_GATE>,
471 <&clks IMX5_CLK_SDMA_GATE>;
472 clock-names = "ipg", "ahb";
474 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
477 cspi: cspi@83fc0000 {
478 #address-cells = <1>;
480 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
481 reg = <0x83fc0000 0x4000>;
483 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
484 <&clks IMX5_CLK_CSPI_IPG_GATE>;
485 clock-names = "ipg", "per";
490 #address-cells = <1>;
492 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
493 reg = <0x83fc4000 0x4000>;
495 clocks = <&clks IMX5_CLK_I2C2_GATE>;
500 #address-cells = <1>;
502 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
503 reg = <0x83fc8000 0x4000>;
505 clocks = <&clks IMX5_CLK_I2C1_GATE>;
510 #sound-dai-cells = <0>;
511 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
512 reg = <0x83fcc000 0x4000>;
514 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
515 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
516 clock-names = "ipg", "baud";
517 dmas = <&sdma 28 0 0>,
519 dma-names = "rx", "tx";
520 fsl,fifo-depth = <15>;
524 audmux: audmux@83fd0000 {
525 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
526 reg = <0x83fd0000 0x4000>;
527 clocks = <&clks IMX5_CLK_DUMMY>;
528 clock-names = "audmux";
532 weim: weim@83fda000 {
533 #address-cells = <2>;
535 compatible = "fsl,imx51-weim";
536 reg = <0x83fda000 0x1000>;
537 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
539 0 0 0xb0000000 0x08000000
540 1 0 0xb8000000 0x08000000
541 2 0 0xc0000000 0x08000000
542 3 0 0xc8000000 0x04000000
543 4 0 0xcc000000 0x02000000
544 5 0 0xce000000 0x02000000
550 #address-cells = <1>;
552 compatible = "fsl,imx51-nand";
553 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
555 clocks = <&clks IMX5_CLK_NFC_GATE>;
559 pata: pata@83fe0000 {
560 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
561 reg = <0x83fe0000 0x4000>;
563 clocks = <&clks IMX5_CLK_PATA_GATE>;
568 #sound-dai-cells = <0>;
569 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
570 reg = <0x83fe8000 0x4000>;
572 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
573 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
574 clock-names = "ipg", "baud";
575 dmas = <&sdma 46 0 0>,
577 dma-names = "rx", "tx";
578 fsl,fifo-depth = <15>;
582 fec: ethernet@83fec000 {
583 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
584 reg = <0x83fec000 0x4000>;
586 clocks = <&clks IMX5_CLK_FEC_GATE>,
587 <&clks IMX5_CLK_FEC_GATE>,
588 <&clks IMX5_CLK_FEC_GATE>;
589 clock-names = "ipg", "ahb", "ptp";