2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx51-pinfunc.h"
32 tzic: tz-interrupt-controller@e0000000 {
33 compatible = "fsl,imx51-tzic", "fsl,tzic";
35 #interrupt-cells = <1>;
36 reg = <0xe0000000 0x4000>;
44 compatible = "fsl,imx-ckil", "fixed-clock";
45 clock-frequency = <32768>;
49 compatible = "fsl,imx-ckih1", "fixed-clock";
50 clock-frequency = <0>;
54 compatible = "fsl,imx-ckih2", "fixed-clock";
55 clock-frequency = <0>;
59 compatible = "fsl,imx-osc", "fixed-clock";
60 clock-frequency = <24000000>;
69 compatible = "arm,cortex-a8";
71 clock-latency = <61036>; /* two CLK32 periods */
75 /* kHz uV (No regulator support) */
85 compatible = "simple-bus";
86 interrupt-parent = <&tzic>;
91 compatible = "fsl,imx51-ipu";
92 reg = <0x40000000 0x20000000>;
94 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
95 clock-names = "bus", "di0", "di1";
99 aips@70000000 { /* AIPS1 */
100 compatible = "fsl,aips-bus", "simple-bus";
101 #address-cells = <1>;
103 reg = <0x70000000 0x10000000>;
107 compatible = "fsl,spba-bus", "simple-bus";
108 #address-cells = <1>;
110 reg = <0x70000000 0x40000>;
113 esdhc1: esdhc@70004000 {
114 compatible = "fsl,imx51-esdhc";
115 reg = <0x70004000 0x4000>;
117 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
118 clock-names = "ipg", "ahb", "per";
122 esdhc2: esdhc@70008000 {
123 compatible = "fsl,imx51-esdhc";
124 reg = <0x70008000 0x4000>;
126 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
127 clock-names = "ipg", "ahb", "per";
132 uart3: serial@7000c000 {
133 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
134 reg = <0x7000c000 0x4000>;
136 clocks = <&clks 32>, <&clks 33>;
137 clock-names = "ipg", "per";
141 ecspi1: ecspi@70010000 {
142 #address-cells = <1>;
144 compatible = "fsl,imx51-ecspi";
145 reg = <0x70010000 0x4000>;
147 clocks = <&clks 51>, <&clks 52>;
148 clock-names = "ipg", "per";
153 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
154 reg = <0x70014000 0x4000>;
157 dmas = <&sdma 24 1 0>,
159 dma-names = "rx", "tx";
160 fsl,fifo-depth = <15>;
161 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
165 esdhc3: esdhc@70020000 {
166 compatible = "fsl,imx51-esdhc";
167 reg = <0x70020000 0x4000>;
169 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
170 clock-names = "ipg", "ahb", "per";
175 esdhc4: esdhc@70024000 {
176 compatible = "fsl,imx51-esdhc";
177 reg = <0x70024000 0x4000>;
179 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
180 clock-names = "ipg", "ahb", "per";
187 compatible = "usb-nop-xceiv";
188 clocks = <&clks 124>;
189 clock-names = "main_clk";
193 usbotg: usb@73f80000 {
194 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
195 reg = <0x73f80000 0x0200>;
197 clocks = <&clks 108>;
198 fsl,usbmisc = <&usbmisc 0>;
199 fsl,usbphy = <&usbphy0>;
203 usbh1: usb@73f80200 {
204 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
205 reg = <0x73f80200 0x0200>;
207 clocks = <&clks 108>;
208 fsl,usbmisc = <&usbmisc 1>;
212 usbh2: usb@73f80400 {
213 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
214 reg = <0x73f80400 0x0200>;
216 clocks = <&clks 108>;
217 fsl,usbmisc = <&usbmisc 2>;
221 usbh3: usb@73f80600 {
222 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
223 reg = <0x73f80600 0x0200>;
225 clocks = <&clks 108>;
226 fsl,usbmisc = <&usbmisc 3>;
230 usbmisc: usbmisc@73f80800 {
232 compatible = "fsl,imx51-usbmisc";
233 reg = <0x73f80800 0x200>;
234 clocks = <&clks 108>;
237 gpio1: gpio@73f84000 {
238 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
239 reg = <0x73f84000 0x4000>;
240 interrupts = <50 51>;
243 interrupt-controller;
244 #interrupt-cells = <2>;
247 gpio2: gpio@73f88000 {
248 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
249 reg = <0x73f88000 0x4000>;
250 interrupts = <52 53>;
253 interrupt-controller;
254 #interrupt-cells = <2>;
257 gpio3: gpio@73f8c000 {
258 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
259 reg = <0x73f8c000 0x4000>;
260 interrupts = <54 55>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
267 gpio4: gpio@73f90000 {
268 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
269 reg = <0x73f90000 0x4000>;
270 interrupts = <56 57>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
278 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
279 reg = <0x73f94000 0x4000>;
285 wdog1: wdog@73f98000 {
286 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
287 reg = <0x73f98000 0x4000>;
292 wdog2: wdog@73f9c000 {
293 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
294 reg = <0x73f9c000 0x4000>;
300 gpt: timer@73fa0000 {
301 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
302 reg = <0x73fa0000 0x4000>;
304 clocks = <&clks 36>, <&clks 41>;
305 clock-names = "ipg", "per";
308 iomuxc: iomuxc@73fa8000 {
309 compatible = "fsl,imx51-iomuxc";
310 reg = <0x73fa8000 0x4000>;
315 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
316 reg = <0x73fb4000 0x4000>;
317 clocks = <&clks 37>, <&clks 38>;
318 clock-names = "ipg", "per";
324 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
325 reg = <0x73fb8000 0x4000>;
326 clocks = <&clks 39>, <&clks 40>;
327 clock-names = "ipg", "per";
331 uart1: serial@73fbc000 {
332 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
333 reg = <0x73fbc000 0x4000>;
335 clocks = <&clks 28>, <&clks 29>;
336 clock-names = "ipg", "per";
340 uart2: serial@73fc0000 {
341 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
342 reg = <0x73fc0000 0x4000>;
344 clocks = <&clks 30>, <&clks 31>;
345 clock-names = "ipg", "per";
350 compatible = "fsl,imx51-src";
351 reg = <0x73fd0000 0x4000>;
356 compatible = "fsl,imx51-ccm";
357 reg = <0x73fd4000 0x4000>;
358 interrupts = <0 71 0x04 0 72 0x04>;
363 aips@80000000 { /* AIPS2 */
364 compatible = "fsl,aips-bus", "simple-bus";
365 #address-cells = <1>;
367 reg = <0x80000000 0x10000000>;
371 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
372 reg = <0x83f98000 0x4000>;
374 clocks = <&clks 107>;
377 ecspi2: ecspi@83fac000 {
378 #address-cells = <1>;
380 compatible = "fsl,imx51-ecspi";
381 reg = <0x83fac000 0x4000>;
383 clocks = <&clks 53>, <&clks 54>;
384 clock-names = "ipg", "per";
388 sdma: sdma@83fb0000 {
389 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
390 reg = <0x83fb0000 0x4000>;
392 clocks = <&clks 56>, <&clks 56>;
393 clock-names = "ipg", "ahb";
395 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
398 cspi: cspi@83fc0000 {
399 #address-cells = <1>;
401 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
402 reg = <0x83fc0000 0x4000>;
404 clocks = <&clks 55>, <&clks 55>;
405 clock-names = "ipg", "per";
410 #address-cells = <1>;
412 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
413 reg = <0x83fc4000 0x4000>;
420 #address-cells = <1>;
422 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
423 reg = <0x83fc8000 0x4000>;
430 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
431 reg = <0x83fcc000 0x4000>;
434 dmas = <&sdma 28 0 0>,
436 dma-names = "rx", "tx";
437 fsl,fifo-depth = <15>;
438 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
442 audmux: audmux@83fd0000 {
443 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
444 reg = <0x83fd0000 0x4000>;
448 weim: weim@83fda000 {
449 #address-cells = <2>;
451 compatible = "fsl,imx51-weim";
452 reg = <0x83fda000 0x1000>;
455 0 0 0xb0000000 0x08000000
456 1 0 0xb8000000 0x08000000
457 2 0 0xc0000000 0x08000000
458 3 0 0xc8000000 0x04000000
459 4 0 0xcc000000 0x02000000
460 5 0 0xce000000 0x02000000
466 compatible = "fsl,imx51-nand";
467 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
473 pata: pata@83fe0000 {
474 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
475 reg = <0x83fe0000 0x4000>;
477 clocks = <&clks 172>;
482 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
483 reg = <0x83fe8000 0x4000>;
486 dmas = <&sdma 46 0 0>,
488 dma-names = "rx", "tx";
489 fsl,fifo-depth = <15>;
490 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
494 fec: ethernet@83fec000 {
495 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
496 reg = <0x83fec000 0x4000>;
498 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
499 clock-names = "ipg", "ahb", "ptp";
508 pinctrl_audmux_1: audmuxgrp-1 {
510 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
511 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
512 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
513 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
519 pinctrl_fec_1: fecgrp-1 {
521 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
522 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
523 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
524 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
525 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
526 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
527 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
528 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
529 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
530 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
531 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
532 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
533 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
534 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
535 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
536 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
537 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
541 pinctrl_fec_2: fecgrp-2 {
543 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
544 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
545 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
546 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
547 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
548 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
549 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
550 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
551 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
552 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
553 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
554 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
555 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
556 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
557 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
558 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
559 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
560 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
566 pinctrl_ecspi1_1: ecspi1grp-1 {
568 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
569 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
570 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
576 pinctrl_ecspi2_1: ecspi2grp-1 {
578 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
579 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
580 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
586 pinctrl_esdhc1_1: esdhc1grp-1 {
588 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
589 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
590 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
591 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
592 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
593 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
599 pinctrl_esdhc2_1: esdhc2grp-1 {
601 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
602 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
603 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
604 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
605 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
606 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
612 pinctrl_i2c2_1: i2c2grp-1 {
614 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
615 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
619 pinctrl_i2c2_2: i2c2grp-2 {
621 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
622 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
626 pinctrl_i2c2_3: i2c2grp-3 {
628 MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
629 MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
635 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
637 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
638 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
639 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
640 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
641 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
642 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
643 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
644 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
645 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
646 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
647 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
648 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
649 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
650 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
651 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
652 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
653 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
654 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
655 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
656 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
657 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
658 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
659 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
660 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
661 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
662 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
668 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
670 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
671 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
672 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
673 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
674 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
675 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
676 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
677 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
678 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
679 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
680 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
681 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
682 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
683 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
684 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
685 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
686 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
687 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
688 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
689 MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */
695 pinctrl_kpp_1: kppgrp-1 {
697 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
698 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
699 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
700 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
701 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
702 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
703 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
704 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
710 pinctrl_pata_1: patagrp-1 {
712 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
713 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
714 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
715 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
716 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
717 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
718 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
719 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
720 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
721 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
722 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
723 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
724 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
725 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
726 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
727 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
728 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
729 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
730 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
731 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
732 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
733 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
734 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
735 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
736 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
737 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
738 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
739 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
740 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
746 pinctrl_uart1_1: uart1grp-1 {
748 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
749 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
750 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
751 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
757 pinctrl_uart2_1: uart2grp-1 {
759 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
760 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
766 pinctrl_uart3_1: uart3grp-1 {
768 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
769 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
770 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
771 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
775 pinctrl_uart3_2: uart3grp-2 {
777 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
778 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
784 pinctrl_usbh1_1: usbh1grp-1 {
786 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
787 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
788 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
789 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
790 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
791 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
792 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
793 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
794 MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
795 MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
796 MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
797 MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
803 pinctrl_usbh2_1: usbh2grp-1 {
805 MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
806 MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
807 MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
808 MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
809 MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
810 MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
811 MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
812 MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
813 MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
814 MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
815 MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
816 MX51_PAD_EIM_A26__USBH2_STP 0x1e5