2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
26 tzic: tz-interrupt-controller@e0000000 {
27 compatible = "fsl,imx51-tzic", "fsl,tzic";
29 #interrupt-cells = <1>;
30 reg = <0xe0000000 0x4000>;
38 compatible = "fsl,imx-ckil", "fixed-clock";
39 clock-frequency = <32768>;
43 compatible = "fsl,imx-ckih1", "fixed-clock";
44 clock-frequency = <22579200>;
48 compatible = "fsl,imx-ckih2", "fixed-clock";
49 clock-frequency = <0>;
53 compatible = "fsl,imx-osc", "fixed-clock";
54 clock-frequency = <24000000>;
61 compatible = "simple-bus";
62 interrupt-parent = <&tzic>;
65 aips@70000000 { /* AIPS1 */
66 compatible = "fsl,aips-bus", "simple-bus";
69 reg = <0x70000000 0x10000000>;
73 compatible = "fsl,spba-bus", "simple-bus";
76 reg = <0x70000000 0x40000>;
79 esdhc@70004000 { /* ESDHC1 */
80 compatible = "fsl,imx51-esdhc";
81 reg = <0x70004000 0x4000>;
86 esdhc@70008000 { /* ESDHC2 */
87 compatible = "fsl,imx51-esdhc";
88 reg = <0x70008000 0x4000>;
93 uart3: serial@7000c000 {
94 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
95 reg = <0x7000c000 0x4000>;
100 ecspi@70010000 { /* ECSPI1 */
101 #address-cells = <1>;
103 compatible = "fsl,imx51-ecspi";
104 reg = <0x70010000 0x4000>;
110 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
111 reg = <0x70014000 0x4000>;
113 fsl,fifo-depth = <15>;
114 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
118 esdhc@70020000 { /* ESDHC3 */
119 compatible = "fsl,imx51-esdhc";
120 reg = <0x70020000 0x4000>;
125 esdhc@70024000 { /* ESDHC4 */
126 compatible = "fsl,imx51-esdhc";
127 reg = <0x70024000 0x4000>;
134 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
135 reg = <0x73f80000 0x0200>;
141 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
142 reg = <0x73f80200 0x0200>;
148 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
149 reg = <0x73f80400 0x0200>;
155 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
156 reg = <0x73f80600 0x0200>;
161 gpio1: gpio@73f84000 {
162 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
163 reg = <0x73f84000 0x4000>;
164 interrupts = <50 51>;
167 interrupt-controller;
168 #interrupt-cells = <2>;
171 gpio2: gpio@73f88000 {
172 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
173 reg = <0x73f88000 0x4000>;
174 interrupts = <52 53>;
177 interrupt-controller;
178 #interrupt-cells = <2>;
181 gpio3: gpio@73f8c000 {
182 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
183 reg = <0x73f8c000 0x4000>;
184 interrupts = <54 55>;
187 interrupt-controller;
188 #interrupt-cells = <2>;
191 gpio4: gpio@73f90000 {
192 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
193 reg = <0x73f90000 0x4000>;
194 interrupts = <56 57>;
197 interrupt-controller;
198 #interrupt-cells = <2>;
201 wdog@73f98000 { /* WDOG1 */
202 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
203 reg = <0x73f98000 0x4000>;
207 wdog@73f9c000 { /* WDOG2 */
208 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
209 reg = <0x73f9c000 0x4000>;
215 compatible = "fsl,imx51-iomuxc";
216 reg = <0x73fa8000 0x4000>;
219 pinctrl_audmux_1: audmuxgrp-1 {
221 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
222 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
223 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
224 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
230 pinctrl_fec_1: fecgrp-1 {
232 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
233 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
234 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
235 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
236 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
237 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
238 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
239 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
240 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
241 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
242 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
243 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
244 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
245 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
246 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
247 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
248 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
254 pinctrl_ecspi1_1: ecspi1grp-1 {
256 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
257 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
258 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
264 pinctrl_esdhc1_1: esdhc1grp-1 {
266 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
267 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
268 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
269 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
270 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
271 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
277 pinctrl_esdhc2_1: esdhc2grp-1 {
279 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
280 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
281 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
282 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
283 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
284 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
290 pinctrl_i2c2_1: i2c2grp-1 {
292 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
293 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
299 pinctrl_uart1_1: uart1grp-1 {
301 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
302 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
303 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
304 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
310 pinctrl_uart2_1: uart2grp-1 {
312 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
313 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
319 pinctrl_uart3_1: uart3grp-1 {
321 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
322 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
323 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
324 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
330 uart1: serial@73fbc000 {
331 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
332 reg = <0x73fbc000 0x4000>;
337 uart2: serial@73fc0000 {
338 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
339 reg = <0x73fc0000 0x4000>;
345 aips@80000000 { /* AIPS2 */
346 compatible = "fsl,aips-bus", "simple-bus";
347 #address-cells = <1>;
349 reg = <0x80000000 0x10000000>;
352 ecspi@83fac000 { /* ECSPI2 */
353 #address-cells = <1>;
355 compatible = "fsl,imx51-ecspi";
356 reg = <0x83fac000 0x4000>;
362 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
363 reg = <0x83fb0000 0x4000>;
365 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
369 #address-cells = <1>;
371 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
372 reg = <0x83fc0000 0x4000>;
377 i2c@83fc4000 { /* I2C2 */
378 #address-cells = <1>;
380 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
381 reg = <0x83fc4000 0x4000>;
386 i2c@83fc8000 { /* I2C1 */
387 #address-cells = <1>;
389 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
390 reg = <0x83fc8000 0x4000>;
396 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
397 reg = <0x83fcc000 0x4000>;
399 fsl,fifo-depth = <15>;
400 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
405 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
406 reg = <0x83fd0000 0x4000>;
411 compatible = "fsl,imx51-nand";
412 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
418 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
419 reg = <0x83fe8000 0x4000>;
421 fsl,fifo-depth = <15>;
422 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
427 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
428 reg = <0x83fec000 0x4000>;