2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
22 tzic: tz-interrupt-controller@e0000000 {
23 compatible = "fsl,imx51-tzic", "fsl,tzic";
25 #interrupt-cells = <1>;
26 reg = <0xe0000000 0x4000>;
34 compatible = "fsl,imx-ckil", "fixed-clock";
35 clock-frequency = <32768>;
39 compatible = "fsl,imx-ckih1", "fixed-clock";
40 clock-frequency = <22579200>;
44 compatible = "fsl,imx-ckih2", "fixed-clock";
45 clock-frequency = <0>;
49 compatible = "fsl,imx-osc", "fixed-clock";
50 clock-frequency = <24000000>;
57 compatible = "simple-bus";
58 interrupt-parent = <&tzic>;
61 aips@70000000 { /* AIPS1 */
62 compatible = "fsl,aips-bus", "simple-bus";
65 reg = <0x70000000 0x10000000>;
69 compatible = "fsl,spba-bus", "simple-bus";
72 reg = <0x70000000 0x40000>;
75 esdhc@70004000 { /* ESDHC1 */
76 compatible = "fsl,imx51-esdhc";
77 reg = <0x70004000 0x4000>;
82 esdhc@70008000 { /* ESDHC2 */
83 compatible = "fsl,imx51-esdhc";
84 reg = <0x70008000 0x4000>;
89 uart3: serial@7000c000 {
90 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
91 reg = <0x7000c000 0x4000>;
96 ecspi@70010000 { /* ECSPI1 */
99 compatible = "fsl,imx51-ecspi";
100 reg = <0x70010000 0x4000>;
106 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
107 reg = <0x70014000 0x4000>;
109 fsl,fifo-depth = <15>;
110 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
114 esdhc@70020000 { /* ESDHC3 */
115 compatible = "fsl,imx51-esdhc";
116 reg = <0x70020000 0x4000>;
121 esdhc@70024000 { /* ESDHC4 */
122 compatible = "fsl,imx51-esdhc";
123 reg = <0x70024000 0x4000>;
129 gpio1: gpio@73f84000 {
130 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
131 reg = <0x73f84000 0x4000>;
132 interrupts = <50 51>;
135 interrupt-controller;
136 #interrupt-cells = <2>;
139 gpio2: gpio@73f88000 {
140 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
141 reg = <0x73f88000 0x4000>;
142 interrupts = <52 53>;
145 interrupt-controller;
146 #interrupt-cells = <2>;
149 gpio3: gpio@73f8c000 {
150 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
151 reg = <0x73f8c000 0x4000>;
152 interrupts = <54 55>;
155 interrupt-controller;
156 #interrupt-cells = <2>;
159 gpio4: gpio@73f90000 {
160 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
161 reg = <0x73f90000 0x4000>;
162 interrupts = <56 57>;
165 interrupt-controller;
166 #interrupt-cells = <2>;
169 wdog@73f98000 { /* WDOG1 */
170 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
171 reg = <0x73f98000 0x4000>;
176 wdog@73f9c000 { /* WDOG2 */
177 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
178 reg = <0x73f9c000 0x4000>;
183 uart1: serial@73fbc000 {
184 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
185 reg = <0x73fbc000 0x4000>;
190 uart2: serial@73fc0000 {
191 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
192 reg = <0x73fc0000 0x4000>;
198 aips@80000000 { /* AIPS2 */
199 compatible = "fsl,aips-bus", "simple-bus";
200 #address-cells = <1>;
202 reg = <0x80000000 0x10000000>;
205 ecspi@83fac000 { /* ECSPI2 */
206 #address-cells = <1>;
208 compatible = "fsl,imx51-ecspi";
209 reg = <0x83fac000 0x4000>;
215 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
216 reg = <0x83fb0000 0x4000>;
221 #address-cells = <1>;
223 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
224 reg = <0x83fc0000 0x4000>;
229 i2c@83fc4000 { /* I2C2 */
230 #address-cells = <1>;
232 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
233 reg = <0x83fc4000 0x4000>;
238 i2c@83fc8000 { /* I2C1 */
239 #address-cells = <1>;
241 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
242 reg = <0x83fc8000 0x4000>;
248 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
249 reg = <0x83fcc000 0x4000>;
251 fsl,fifo-depth = <15>;
252 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
257 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
258 reg = <0x83fd0000 0x4000>;
263 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
264 reg = <0x83fe8000 0x4000>;
266 fsl,fifo-depth = <15>;
267 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
272 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
273 reg = <0x83fec000 0x4000>;