2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx51-pinfunc.h"
32 tzic: tz-interrupt-controller@e0000000 {
33 compatible = "fsl,imx51-tzic", "fsl,tzic";
35 #interrupt-cells = <1>;
36 reg = <0xe0000000 0x4000>;
44 compatible = "fsl,imx-ckil", "fixed-clock";
45 clock-frequency = <32768>;
49 compatible = "fsl,imx-ckih1", "fixed-clock";
50 clock-frequency = <0>;
54 compatible = "fsl,imx-ckih2", "fixed-clock";
55 clock-frequency = <0>;
59 compatible = "fsl,imx-osc", "fixed-clock";
60 clock-frequency = <24000000>;
69 compatible = "arm,cortex-a8";
71 clock-latency = <61036>; /* two CLK32 periods */
75 /* kHz uV (No regulator support) */
85 compatible = "simple-bus";
86 interrupt-parent = <&tzic>;
90 compatible = "mmio-sram";
91 reg = <0x1ffe0000 0x20000>;
96 compatible = "fsl,imx51-ipu";
97 reg = <0x40000000 0x20000000>;
99 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
100 clock-names = "bus", "di0", "di1";
104 aips@70000000 { /* AIPS1 */
105 compatible = "fsl,aips-bus", "simple-bus";
106 #address-cells = <1>;
108 reg = <0x70000000 0x10000000>;
112 compatible = "fsl,spba-bus", "simple-bus";
113 #address-cells = <1>;
115 reg = <0x70000000 0x40000>;
118 esdhc1: esdhc@70004000 {
119 compatible = "fsl,imx51-esdhc";
120 reg = <0x70004000 0x4000>;
122 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
123 clock-names = "ipg", "ahb", "per";
127 esdhc2: esdhc@70008000 {
128 compatible = "fsl,imx51-esdhc";
129 reg = <0x70008000 0x4000>;
131 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
132 clock-names = "ipg", "ahb", "per";
137 uart3: serial@7000c000 {
138 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
139 reg = <0x7000c000 0x4000>;
141 clocks = <&clks 32>, <&clks 33>;
142 clock-names = "ipg", "per";
146 ecspi1: ecspi@70010000 {
147 #address-cells = <1>;
149 compatible = "fsl,imx51-ecspi";
150 reg = <0x70010000 0x4000>;
152 clocks = <&clks 51>, <&clks 52>;
153 clock-names = "ipg", "per";
158 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
159 reg = <0x70014000 0x4000>;
162 dmas = <&sdma 24 1 0>,
164 dma-names = "rx", "tx";
165 fsl,fifo-depth = <15>;
166 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
170 esdhc3: esdhc@70020000 {
171 compatible = "fsl,imx51-esdhc";
172 reg = <0x70020000 0x4000>;
174 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
175 clock-names = "ipg", "ahb", "per";
180 esdhc4: esdhc@70024000 {
181 compatible = "fsl,imx51-esdhc";
182 reg = <0x70024000 0x4000>;
184 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
185 clock-names = "ipg", "ahb", "per";
192 compatible = "usb-nop-xceiv";
194 clock-names = "main_clk";
198 usbotg: usb@73f80000 {
199 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
200 reg = <0x73f80000 0x0200>;
202 clocks = <&clks 108>;
203 fsl,usbmisc = <&usbmisc 0>;
204 fsl,usbphy = <&usbphy0>;
208 usbh1: usb@73f80200 {
209 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
210 reg = <0x73f80200 0x0200>;
212 clocks = <&clks 108>;
213 fsl,usbmisc = <&usbmisc 1>;
217 usbh2: usb@73f80400 {
218 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
219 reg = <0x73f80400 0x0200>;
221 clocks = <&clks 108>;
222 fsl,usbmisc = <&usbmisc 2>;
226 usbh3: usb@73f80600 {
227 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
228 reg = <0x73f80600 0x0200>;
230 clocks = <&clks 108>;
231 fsl,usbmisc = <&usbmisc 3>;
235 usbmisc: usbmisc@73f80800 {
237 compatible = "fsl,imx51-usbmisc";
238 reg = <0x73f80800 0x200>;
239 clocks = <&clks 108>;
242 gpio1: gpio@73f84000 {
243 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
244 reg = <0x73f84000 0x4000>;
245 interrupts = <50 51>;
248 interrupt-controller;
249 #interrupt-cells = <2>;
252 gpio2: gpio@73f88000 {
253 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
254 reg = <0x73f88000 0x4000>;
255 interrupts = <52 53>;
258 interrupt-controller;
259 #interrupt-cells = <2>;
262 gpio3: gpio@73f8c000 {
263 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
264 reg = <0x73f8c000 0x4000>;
265 interrupts = <54 55>;
268 interrupt-controller;
269 #interrupt-cells = <2>;
272 gpio4: gpio@73f90000 {
273 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
274 reg = <0x73f90000 0x4000>;
275 interrupts = <56 57>;
278 interrupt-controller;
279 #interrupt-cells = <2>;
283 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
284 reg = <0x73f94000 0x4000>;
290 wdog1: wdog@73f98000 {
291 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
292 reg = <0x73f98000 0x4000>;
297 wdog2: wdog@73f9c000 {
298 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
299 reg = <0x73f9c000 0x4000>;
305 gpt: timer@73fa0000 {
306 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
307 reg = <0x73fa0000 0x4000>;
309 clocks = <&clks 36>, <&clks 41>;
310 clock-names = "ipg", "per";
313 iomuxc: iomuxc@73fa8000 {
314 compatible = "fsl,imx51-iomuxc";
315 reg = <0x73fa8000 0x4000>;
320 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
321 reg = <0x73fb4000 0x4000>;
322 clocks = <&clks 37>, <&clks 38>;
323 clock-names = "ipg", "per";
329 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
330 reg = <0x73fb8000 0x4000>;
331 clocks = <&clks 39>, <&clks 40>;
332 clock-names = "ipg", "per";
336 uart1: serial@73fbc000 {
337 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
338 reg = <0x73fbc000 0x4000>;
340 clocks = <&clks 28>, <&clks 29>;
341 clock-names = "ipg", "per";
345 uart2: serial@73fc0000 {
346 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
347 reg = <0x73fc0000 0x4000>;
349 clocks = <&clks 30>, <&clks 31>;
350 clock-names = "ipg", "per";
355 compatible = "fsl,imx51-src";
356 reg = <0x73fd0000 0x4000>;
361 compatible = "fsl,imx51-ccm";
362 reg = <0x73fd4000 0x4000>;
363 interrupts = <0 71 0x04 0 72 0x04>;
368 aips@80000000 { /* AIPS2 */
369 compatible = "fsl,aips-bus", "simple-bus";
370 #address-cells = <1>;
372 reg = <0x80000000 0x10000000>;
376 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
377 reg = <0x83f98000 0x4000>;
379 clocks = <&clks 107>;
382 owire: owire@83fa4000 {
383 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
384 reg = <0x83fa4000 0x4000>;
386 clocks = <&clks 159>;
390 ecspi2: ecspi@83fac000 {
391 #address-cells = <1>;
393 compatible = "fsl,imx51-ecspi";
394 reg = <0x83fac000 0x4000>;
396 clocks = <&clks 53>, <&clks 54>;
397 clock-names = "ipg", "per";
401 sdma: sdma@83fb0000 {
402 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
403 reg = <0x83fb0000 0x4000>;
405 clocks = <&clks 56>, <&clks 56>;
406 clock-names = "ipg", "ahb";
408 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
411 cspi: cspi@83fc0000 {
412 #address-cells = <1>;
414 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
415 reg = <0x83fc0000 0x4000>;
417 clocks = <&clks 55>, <&clks 55>;
418 clock-names = "ipg", "per";
423 #address-cells = <1>;
425 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
426 reg = <0x83fc4000 0x4000>;
433 #address-cells = <1>;
435 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
436 reg = <0x83fc8000 0x4000>;
443 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
444 reg = <0x83fcc000 0x4000>;
447 dmas = <&sdma 28 0 0>,
449 dma-names = "rx", "tx";
450 fsl,fifo-depth = <15>;
451 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
455 audmux: audmux@83fd0000 {
456 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
457 reg = <0x83fd0000 0x4000>;
461 weim: weim@83fda000 {
462 #address-cells = <2>;
464 compatible = "fsl,imx51-weim";
465 reg = <0x83fda000 0x1000>;
468 0 0 0xb0000000 0x08000000
469 1 0 0xb8000000 0x08000000
470 2 0 0xc0000000 0x08000000
471 3 0 0xc8000000 0x04000000
472 4 0 0xcc000000 0x02000000
473 5 0 0xce000000 0x02000000
479 compatible = "fsl,imx51-nand";
480 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
486 pata: pata@83fe0000 {
487 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
488 reg = <0x83fe0000 0x4000>;
490 clocks = <&clks 172>;
495 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
496 reg = <0x83fe8000 0x4000>;
499 dmas = <&sdma 46 0 0>,
501 dma-names = "rx", "tx";
502 fsl,fifo-depth = <15>;
503 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
507 fec: ethernet@83fec000 {
508 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
509 reg = <0x83fec000 0x4000>;
511 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
512 clock-names = "ipg", "ahb", "ptp";
521 pinctrl_audmux_1: audmuxgrp-1 {
523 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
524 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
525 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
526 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
532 pinctrl_fec_1: fecgrp-1 {
534 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
535 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
536 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
537 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
538 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
539 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
540 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
541 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
542 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
543 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
544 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
545 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
546 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
547 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
548 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
549 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
550 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
554 pinctrl_fec_2: fecgrp-2 {
556 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
557 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
558 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
559 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
560 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
561 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
562 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
563 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
564 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
565 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
566 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
567 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
568 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
569 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
570 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
571 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
572 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
573 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
579 pinctrl_ecspi1_1: ecspi1grp-1 {
581 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
582 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
583 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
589 pinctrl_ecspi2_1: ecspi2grp-1 {
591 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
592 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
593 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
599 pinctrl_esdhc1_1: esdhc1grp-1 {
601 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
602 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
603 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
604 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
605 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
606 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
612 pinctrl_esdhc2_1: esdhc2grp-1 {
614 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
615 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
616 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
617 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
618 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
619 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
625 pinctrl_i2c2_1: i2c2grp-1 {
627 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
628 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
632 pinctrl_i2c2_2: i2c2grp-2 {
634 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
635 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
639 pinctrl_i2c2_3: i2c2grp-3 {
641 MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
642 MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
648 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
650 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
651 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
652 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
653 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
654 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
655 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
656 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
657 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
658 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
659 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
660 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
661 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
662 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
663 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
664 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
665 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
666 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
667 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
668 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
669 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
670 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
671 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
672 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
673 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
674 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
675 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
681 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
683 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
684 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
685 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
686 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
687 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
688 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
689 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
690 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
691 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
692 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
693 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
694 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
695 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
696 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
697 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
698 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
699 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
700 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
701 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
702 MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */
708 pinctrl_kpp_1: kppgrp-1 {
710 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
711 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
712 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
713 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
714 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
715 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
716 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
717 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
723 pinctrl_pata_1: patagrp-1 {
725 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
726 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
727 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
728 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
729 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
730 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
731 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
732 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
733 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
734 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
735 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
736 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
737 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
738 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
739 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
740 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
741 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
742 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
743 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
744 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
745 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
746 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
747 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
748 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
749 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
750 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
751 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
752 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
753 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
759 pinctrl_uart1_1: uart1grp-1 {
761 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
762 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
766 pinctrl_uart1_rtscts_1: uart1rtscts-1 {
768 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
769 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
775 pinctrl_uart2_1: uart2grp-1 {
777 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
778 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
784 pinctrl_uart3_1: uart3grp-1 {
786 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
787 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
791 pinctrl_uart3_rtscts_1: uart3rtscts-1 {
793 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
794 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
798 pinctrl_uart3_2: uart3grp-2 {
800 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
801 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
807 pinctrl_usbh1_1: usbh1grp-1 {
809 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
810 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
811 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
812 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
813 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
814 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
815 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
816 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
817 MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
818 MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
819 MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
820 MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
826 pinctrl_usbh2_1: usbh2grp-1 {
828 MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
829 MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
830 MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
831 MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
832 MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
833 MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
834 MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
835 MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
836 MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
837 MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
838 MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
839 MX51_PAD_EIM_A26__USBH2_STP 0x1e5