2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
43 compatible = "arm,cortex-a8";
48 tzic: tz-interrupt-controller@0fffc000 {
49 compatible = "fsl,imx53-tzic", "fsl,tzic";
51 #interrupt-cells = <1>;
52 reg = <0x0fffc000 0x4000>;
60 compatible = "fsl,imx-ckil", "fixed-clock";
61 clock-frequency = <32768>;
65 compatible = "fsl,imx-ckih1", "fixed-clock";
66 clock-frequency = <22579200>;
70 compatible = "fsl,imx-ckih2", "fixed-clock";
71 clock-frequency = <0>;
75 compatible = "fsl,imx-osc", "fixed-clock";
76 clock-frequency = <24000000>;
83 compatible = "simple-bus";
84 interrupt-parent = <&tzic>;
89 compatible = "fsl,imx53-ipu";
90 reg = <0x18000000 0x080000000>;
92 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
93 clock-names = "bus", "di0", "di1";
97 aips@50000000 { /* AIPS1 */
98 compatible = "fsl,aips-bus", "simple-bus";
101 reg = <0x50000000 0x10000000>;
105 compatible = "fsl,spba-bus", "simple-bus";
106 #address-cells = <1>;
108 reg = <0x50000000 0x40000>;
111 esdhc1: esdhc@50004000 {
112 compatible = "fsl,imx53-esdhc";
113 reg = <0x50004000 0x4000>;
115 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
116 clock-names = "ipg", "ahb", "per";
121 esdhc2: esdhc@50008000 {
122 compatible = "fsl,imx53-esdhc";
123 reg = <0x50008000 0x4000>;
125 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
126 clock-names = "ipg", "ahb", "per";
131 uart3: serial@5000c000 {
132 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
133 reg = <0x5000c000 0x4000>;
135 clocks = <&clks 32>, <&clks 33>;
136 clock-names = "ipg", "per";
140 ecspi1: ecspi@50010000 {
141 #address-cells = <1>;
143 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
144 reg = <0x50010000 0x4000>;
146 clocks = <&clks 51>, <&clks 52>;
147 clock-names = "ipg", "per";
152 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
153 reg = <0x50014000 0x4000>;
156 dmas = <&sdma 24 1 0>,
158 dma-names = "rx", "tx";
159 fsl,fifo-depth = <15>;
160 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
164 esdhc3: esdhc@50020000 {
165 compatible = "fsl,imx53-esdhc";
166 reg = <0x50020000 0x4000>;
168 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
169 clock-names = "ipg", "ahb", "per";
174 esdhc4: esdhc@50024000 {
175 compatible = "fsl,imx53-esdhc";
176 reg = <0x50024000 0x4000>;
178 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
179 clock-names = "ipg", "ahb", "per";
186 compatible = "usb-nop-xceiv";
187 clocks = <&clks 124>;
188 clock-names = "main_clk";
193 compatible = "usb-nop-xceiv";
194 clocks = <&clks 125>;
195 clock-names = "main_clk";
199 usbotg: usb@53f80000 {
200 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
201 reg = <0x53f80000 0x0200>;
203 clocks = <&clks 108>;
204 fsl,usbmisc = <&usbmisc 0>;
205 fsl,usbphy = <&usbphy0>;
209 usbh1: usb@53f80200 {
210 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
211 reg = <0x53f80200 0x0200>;
213 clocks = <&clks 108>;
214 fsl,usbmisc = <&usbmisc 1>;
215 fsl,usbphy = <&usbphy1>;
219 usbh2: usb@53f80400 {
220 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
221 reg = <0x53f80400 0x0200>;
223 clocks = <&clks 108>;
224 fsl,usbmisc = <&usbmisc 2>;
228 usbh3: usb@53f80600 {
229 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
230 reg = <0x53f80600 0x0200>;
232 clocks = <&clks 108>;
233 fsl,usbmisc = <&usbmisc 3>;
237 usbmisc: usbmisc@53f80800 {
239 compatible = "fsl,imx53-usbmisc";
240 reg = <0x53f80800 0x200>;
241 clocks = <&clks 108>;
244 gpio1: gpio@53f84000 {
245 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
246 reg = <0x53f84000 0x4000>;
247 interrupts = <50 51>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
254 gpio2: gpio@53f88000 {
255 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
256 reg = <0x53f88000 0x4000>;
257 interrupts = <52 53>;
260 interrupt-controller;
261 #interrupt-cells = <2>;
264 gpio3: gpio@53f8c000 {
265 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
266 reg = <0x53f8c000 0x4000>;
267 interrupts = <54 55>;
270 interrupt-controller;
271 #interrupt-cells = <2>;
274 gpio4: gpio@53f90000 {
275 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
276 reg = <0x53f90000 0x4000>;
277 interrupts = <56 57>;
280 interrupt-controller;
281 #interrupt-cells = <2>;
284 wdog1: wdog@53f98000 {
285 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
286 reg = <0x53f98000 0x4000>;
291 wdog2: wdog@53f9c000 {
292 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
293 reg = <0x53f9c000 0x4000>;
299 gpt: timer@53fa0000 {
300 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
301 reg = <0x53fa0000 0x4000>;
303 clocks = <&clks 36>, <&clks 41>;
304 clock-names = "ipg", "per";
307 iomuxc: iomuxc@53fa8000 {
308 compatible = "fsl,imx53-iomuxc";
309 reg = <0x53fa8000 0x4000>;
312 pinctrl_audmux_1: audmuxgrp-1 {
314 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
315 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
316 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
317 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
321 pinctrl_audmux_2: audmuxgrp-2 {
323 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
324 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
325 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
326 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
330 pinctrl_audmux_3: audmuxgrp-3 {
332 MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
333 MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
334 MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
335 MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
341 pinctrl_fec_1: fecgrp-1 {
343 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
344 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
345 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
346 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
347 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
348 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
349 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
350 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
351 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
352 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
356 pinctrl_fec_2: fecgrp-2 {
358 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
359 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
360 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
361 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
362 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
363 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
364 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
365 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
366 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
367 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
368 MX53_PAD_KEY_ROW1__FEC_COL 0x80000000
369 MX53_PAD_KEY_COL3__FEC_CRS 0x80000000
370 MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000
371 MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000
372 MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000
373 MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000
374 MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000
375 MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000
381 pinctrl_csi_1: csigrp-1 {
383 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
384 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
385 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
386 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
387 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
388 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
389 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
390 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
391 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
392 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
393 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
394 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
395 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
396 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
397 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
398 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
399 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
400 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
401 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
402 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
403 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
407 pinctrl_csi_2: csigrp-2 {
409 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
410 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
411 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
412 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
413 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
414 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
415 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
416 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
417 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
418 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
419 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
425 pinctrl_cspi_1: cspigrp-1 {
427 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
428 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
429 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
433 pinctrl_cspi_2: cspigrp-2 {
435 MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
436 MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
437 MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
443 pinctrl_ecspi1_1: ecspi1grp-1 {
445 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
446 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
447 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
451 pinctrl_ecspi1_2: ecspi1grp-2 {
453 MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
454 MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
455 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
456 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
457 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
458 MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
464 pinctrl_ecspi2_1: ecspi2grp-1 {
466 MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000
467 MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
468 MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
474 pinctrl_esdhc1_1: esdhc1grp-1 {
476 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
477 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
478 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
479 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
480 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
481 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
485 pinctrl_esdhc1_2: esdhc1grp-2 {
487 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
488 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
489 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
490 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
491 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
492 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
493 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
494 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
495 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
496 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
502 pinctrl_esdhc2_1: esdhc2grp-1 {
504 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
505 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
506 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
507 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
508 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
509 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
515 pinctrl_esdhc3_1: esdhc3grp-1 {
517 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
518 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
519 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
520 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
521 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
522 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
523 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
524 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
525 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
526 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
532 pinctrl_can1_1: can1grp-1 {
534 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
535 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
539 pinctrl_can1_2: can1grp-2 {
541 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
542 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
546 pinctrl_can1_3: can1grp-3 {
548 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
549 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
555 pinctrl_can2_1: can2grp-1 {
557 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
558 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
564 pinctrl_i2c1_1: i2c1grp-1 {
566 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
567 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
571 pinctrl_i2c1_2: i2c1grp-2 {
573 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
574 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
580 pinctrl_i2c2_1: i2c2grp-1 {
582 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
583 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
587 pinctrl_i2c2_2: i2c2grp-2 {
589 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
590 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
596 pinctrl_i2c3_1: i2c3grp-1 {
598 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
599 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
603 pinctrl_i2c3_2: i2c3grp-2 {
605 MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000
606 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
612 pinctrl_ipu_disp0_1: ipudisp0grp-1 {
614 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
615 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
616 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
617 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
618 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
619 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
620 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
621 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
622 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
623 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
624 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
625 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
626 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
627 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
628 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
629 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
630 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
631 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
632 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
633 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
634 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
635 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
636 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
637 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
638 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
639 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
640 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
641 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
647 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
649 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
650 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
651 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
652 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
653 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
654 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
655 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
656 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
657 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
658 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
659 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
660 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
661 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
662 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
663 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
664 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
665 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
666 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
667 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
668 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
669 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
670 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
671 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
672 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
673 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
674 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
675 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
676 MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
677 MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
678 MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
679 MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
680 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
686 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
688 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
689 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
690 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
691 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
692 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
693 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
694 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
695 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
696 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
697 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
703 pinctrl_nand_1: nandgrp-1 {
705 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
706 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
707 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
708 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
709 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
710 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
711 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
712 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
713 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
714 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
715 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
716 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
717 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
718 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
719 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
725 pinctrl_owire_1: owiregrp-1 {
727 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
733 pinctrl_pwm1_1: pwm1grp-1 {
735 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
741 pinctrl_pwm2_1: pwm2grp-1 {
743 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
749 pinctrl_uart1_1: uart1grp-1 {
751 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
752 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
756 pinctrl_uart1_2: uart1grp-2 {
758 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
759 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
763 pinctrl_uart1_3: uart1grp-3 {
765 MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
766 MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
772 pinctrl_uart2_1: uart2grp-1 {
774 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
775 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
779 pinctrl_uart2_2: uart2grp-2 {
781 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
782 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
783 MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
784 MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
790 pinctrl_uart3_1: uart3grp-1 {
792 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
793 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
794 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
795 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
799 pinctrl_uart3_2: uart3grp-2 {
801 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
802 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
809 pinctrl_uart4_1: uart4grp-1 {
811 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4
812 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4
818 pinctrl_uart5_1: uart5grp-1 {
820 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1e4
821 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1e4
827 gpr: iomuxc-gpr@53fa8000 {
828 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
829 reg = <0x53fa8000 0xc>;
833 #address-cells = <1>;
835 compatible = "fsl,imx53-ldb";
836 reg = <0x53fa8008 0x4>;
838 clocks = <&clks 122>, <&clks 120>,
839 <&clks 115>, <&clks 116>,
840 <&clks 123>, <&clks 85>;
841 clock-names = "di0_pll", "di1_pll",
842 "di0_sel", "di1_sel",
861 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
862 reg = <0x53fb4000 0x4000>;
863 clocks = <&clks 37>, <&clks 38>;
864 clock-names = "ipg", "per";
870 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
871 reg = <0x53fb8000 0x4000>;
872 clocks = <&clks 39>, <&clks 40>;
873 clock-names = "ipg", "per";
877 uart1: serial@53fbc000 {
878 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
879 reg = <0x53fbc000 0x4000>;
881 clocks = <&clks 28>, <&clks 29>;
882 clock-names = "ipg", "per";
886 uart2: serial@53fc0000 {
887 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
888 reg = <0x53fc0000 0x4000>;
890 clocks = <&clks 30>, <&clks 31>;
891 clock-names = "ipg", "per";
896 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
897 reg = <0x53fc8000 0x4000>;
899 clocks = <&clks 158>, <&clks 157>;
900 clock-names = "ipg", "per";
905 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
906 reg = <0x53fcc000 0x4000>;
908 clocks = <&clks 87>, <&clks 86>;
909 clock-names = "ipg", "per";
914 compatible = "fsl,imx53-src", "fsl,imx51-src";
915 reg = <0x53fd0000 0x4000>;
920 compatible = "fsl,imx53-ccm";
921 reg = <0x53fd4000 0x4000>;
922 interrupts = <0 71 0x04 0 72 0x04>;
926 gpio5: gpio@53fdc000 {
927 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
928 reg = <0x53fdc000 0x4000>;
929 interrupts = <103 104>;
932 interrupt-controller;
933 #interrupt-cells = <2>;
936 gpio6: gpio@53fe0000 {
937 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
938 reg = <0x53fe0000 0x4000>;
939 interrupts = <105 106>;
942 interrupt-controller;
943 #interrupt-cells = <2>;
946 gpio7: gpio@53fe4000 {
947 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
948 reg = <0x53fe4000 0x4000>;
949 interrupts = <107 108>;
952 interrupt-controller;
953 #interrupt-cells = <2>;
957 #address-cells = <1>;
959 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
960 reg = <0x53fec000 0x4000>;
966 uart4: serial@53ff0000 {
967 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
968 reg = <0x53ff0000 0x4000>;
970 clocks = <&clks 65>, <&clks 66>;
971 clock-names = "ipg", "per";
976 aips@60000000 { /* AIPS2 */
977 compatible = "fsl,aips-bus", "simple-bus";
978 #address-cells = <1>;
980 reg = <0x60000000 0x10000000>;
984 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
985 reg = <0x63f98000 0x4000>;
987 clocks = <&clks 107>;
990 uart5: serial@63f90000 {
991 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
992 reg = <0x63f90000 0x4000>;
994 clocks = <&clks 67>, <&clks 68>;
995 clock-names = "ipg", "per";
999 owire: owire@63fa4000 {
1000 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
1001 reg = <0x63fa4000 0x4000>;
1002 clocks = <&clks 159>;
1003 status = "disabled";
1006 ecspi2: ecspi@63fac000 {
1007 #address-cells = <1>;
1009 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
1010 reg = <0x63fac000 0x4000>;
1012 clocks = <&clks 53>, <&clks 54>;
1013 clock-names = "ipg", "per";
1014 status = "disabled";
1017 sdma: sdma@63fb0000 {
1018 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
1019 reg = <0x63fb0000 0x4000>;
1021 clocks = <&clks 56>, <&clks 56>;
1022 clock-names = "ipg", "ahb";
1024 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
1027 cspi: cspi@63fc0000 {
1028 #address-cells = <1>;
1030 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
1031 reg = <0x63fc0000 0x4000>;
1033 clocks = <&clks 55>, <&clks 55>;
1034 clock-names = "ipg", "per";
1035 status = "disabled";
1038 i2c2: i2c@63fc4000 {
1039 #address-cells = <1>;
1041 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1042 reg = <0x63fc4000 0x4000>;
1044 clocks = <&clks 35>;
1045 status = "disabled";
1048 i2c1: i2c@63fc8000 {
1049 #address-cells = <1>;
1051 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
1052 reg = <0x63fc8000 0x4000>;
1054 clocks = <&clks 34>;
1055 status = "disabled";
1058 ssi1: ssi@63fcc000 {
1059 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1060 reg = <0x63fcc000 0x4000>;
1062 clocks = <&clks 48>;
1063 dmas = <&sdma 28 0 0>,
1065 dma-names = "rx", "tx";
1066 fsl,fifo-depth = <15>;
1067 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
1068 status = "disabled";
1071 audmux: audmux@63fd0000 {
1072 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
1073 reg = <0x63fd0000 0x4000>;
1074 status = "disabled";
1077 nfc: nand@63fdb000 {
1078 compatible = "fsl,imx53-nand";
1079 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
1081 clocks = <&clks 60>;
1082 status = "disabled";
1085 ssi3: ssi@63fe8000 {
1086 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1087 reg = <0x63fe8000 0x4000>;
1089 clocks = <&clks 50>;
1090 dmas = <&sdma 46 0 0>,
1092 dma-names = "rx", "tx";
1093 fsl,fifo-depth = <15>;
1094 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
1095 status = "disabled";
1098 fec: ethernet@63fec000 {
1099 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
1100 reg = <0x63fec000 0x4000>;
1102 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
1103 clock-names = "ipg", "ahb", "ptp";
1104 status = "disabled";
1108 compatible = "fsl,imx53-tve";
1109 reg = <0x63ff0000 0x1000>;
1111 clocks = <&clks 69>, <&clks 116>;
1112 clock-names = "tve", "di_sel";
1114 status = "disabled";
1118 compatible = "fsl,imx53-vpu";
1119 reg = <0x63ff4000 0x1000>;
1121 clocks = <&clks 63>, <&clks 63>;
1122 clock-names = "per", "ahb";
1124 status = "disabled";
1128 ocram: sram@f8000000 {
1129 compatible = "mmio-sram";
1130 reg = <0xf8000000 0x20000>;
1131 clocks = <&clks 186>;