arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx53-pinfunc.h"
  15
  16 / {
  17         aliases {
  18                 serial0 = &uart1;
  19                 serial1 = &uart2;
  20                 serial2 = &uart3;
  21                 serial3 = &uart4;
  22                 serial4 = &uart5;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 gpio5 = &gpio6;
  29                 gpio6 = &gpio7;
  30                 i2c0 = &i2c1;
  31                 i2c1 = &i2c2;
  32                 i2c2 = &i2c3;
  33         };
  34
  35         tzic: tz-interrupt-controller@0fffc000 {
  36                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  37                 interrupt-controller;
  38                 #interrupt-cells = <1>;
  39                 reg = <0x0fffc000 0x4000>;
  40         };
  41
  42         clocks {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 ckil {
  47                         compatible = "fsl,imx-ckil", "fixed-clock";
  48                         clock-frequency = <32768>;
  49                 };
  50
  51                 ckih1 {
  52                         compatible = "fsl,imx-ckih1", "fixed-clock";
  53                         clock-frequency = <22579200>;
  54                 };
  55
  56                 ckih2 {
  57                         compatible = "fsl,imx-ckih2", "fixed-clock";
  58                         clock-frequency = <0>;
  59                 };
  60
  61                 osc {
  62                         compatible = "fsl,imx-osc", "fixed-clock";
  63                         clock-frequency = <24000000>;
  64                 };
  65         };
  66
  67         soc {
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 compatible = "simple-bus";
  71                 interrupt-parent = <&tzic>;
  72                 ranges;
  73
  74                 ipu: ipu@18000000 {
  75                         #crtc-cells = <1>;
  76                         compatible = "fsl,imx53-ipu";
  77                         reg = <0x18000000 0x080000000>;
  78                         interrupts = <11 10>;
  79                         clocks = <&clks 59>, <&clks 110>, <&clks 61>;
  80                         clock-names = "bus", "di0", "di1";
  81                         resets = <&src 2>;
  82                 };
  83
  84                 aips@50000000 { /* AIPS1 */
  85                         compatible = "fsl,aips-bus", "simple-bus";
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         reg = <0x50000000 0x10000000>;
  89                         ranges;
  90
  91                         spba@50000000 {
  92                                 compatible = "fsl,spba-bus", "simple-bus";
  93                                 #address-cells = <1>;
  94                                 #size-cells = <1>;
  95                                 reg = <0x50000000 0x40000>;
  96                                 ranges;
  97
  98                                 esdhc1: esdhc@50004000 {
  99                                         compatible = "fsl,imx53-esdhc";
 100                                         reg = <0x50004000 0x4000>;
 101                                         interrupts = <1>;
 102                                         clocks = <&clks 44>, <&clks 0>, <&clks 71>;
 103                                         clock-names = "ipg", "ahb", "per";
 104                                         bus-width = <4>;
 105                                         status = "disabled";
 106                                 };
 107
 108                                 esdhc2: esdhc@50008000 {
 109                                         compatible = "fsl,imx53-esdhc";
 110                                         reg = <0x50008000 0x4000>;
 111                                         interrupts = <2>;
 112                                         clocks = <&clks 45>, <&clks 0>, <&clks 72>;
 113                                         clock-names = "ipg", "ahb", "per";
 114                                         bus-width = <4>;
 115                                         status = "disabled";
 116                                 };
 117
 118                                 uart3: serial@5000c000 {
 119                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 120                                         reg = <0x5000c000 0x4000>;
 121                                         interrupts = <33>;
 122                                         clocks = <&clks 32>, <&clks 33>;
 123                                         clock-names = "ipg", "per";
 124                                         status = "disabled";
 125                                 };
 126
 127                                 ecspi1: ecspi@50010000 {
 128                                         #address-cells = <1>;
 129                                         #size-cells = <0>;
 130                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 131                                         reg = <0x50010000 0x4000>;
 132                                         interrupts = <36>;
 133                                         clocks = <&clks 51>, <&clks 52>;
 134                                         clock-names = "ipg", "per";
 135                                         status = "disabled";
 136                                 };
 137
 138                                 ssi2: ssi@50014000 {
 139                                         compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 140                                         reg = <0x50014000 0x4000>;
 141                                         interrupts = <30>;
 142                                         clocks = <&clks 49>;
 143                                         fsl,fifo-depth = <15>;
 144                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 145                                         status = "disabled";
 146                                 };
 147
 148                                 esdhc3: esdhc@50020000 {
 149                                         compatible = "fsl,imx53-esdhc";
 150                                         reg = <0x50020000 0x4000>;
 151                                         interrupts = <3>;
 152                                         clocks = <&clks 46>, <&clks 0>, <&clks 73>;
 153                                         clock-names = "ipg", "ahb", "per";
 154                                         bus-width = <4>;
 155                                         status = "disabled";
 156                                 };
 157
 158                                 esdhc4: esdhc@50024000 {
 159                                         compatible = "fsl,imx53-esdhc";
 160                                         reg = <0x50024000 0x4000>;
 161                                         interrupts = <4>;
 162                                         clocks = <&clks 47>, <&clks 0>, <&clks 74>;
 163                                         clock-names = "ipg", "ahb", "per";
 164                                         bus-width = <4>;
 165                                         status = "disabled";
 166                                 };
 167                         };
 168
 169                         usbphy0: usbphy@0 {
 170                                 compatible = "usb-nop-xceiv";
 171                                 clocks = <&clks 124>;
 172                                 clock-names = "main_clk";
 173                                 status = "okay";
 174                         };
 175
 176                         usbphy1: usbphy@1 {
 177                                 compatible = "usb-nop-xceiv";
 178                                 clocks = <&clks 125>;
 179                                 clock-names = "main_clk";
 180                                 status = "okay";
 181                         };
 182
 183                         usbotg: usb@53f80000 {
 184                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 185                                 reg = <0x53f80000 0x0200>;
 186                                 interrupts = <18>;
 187                                 clocks = <&clks 108>;
 188                                 fsl,usbmisc = <&usbmisc 0>;
 189                                 fsl,usbphy = <&usbphy0>;
 190                                 status = "disabled";
 191                         };
 192
 193                         usbh1: usb@53f80200 {
 194                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 195                                 reg = <0x53f80200 0x0200>;
 196                                 interrupts = <14>;
 197                                 clocks = <&clks 108>;
 198                                 fsl,usbmisc = <&usbmisc 1>;
 199                                 fsl,usbphy = <&usbphy1>;
 200                                 status = "disabled";
 201                         };
 202
 203                         usbh2: usb@53f80400 {
 204                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 205                                 reg = <0x53f80400 0x0200>;
 206                                 interrupts = <16>;
 207                                 clocks = <&clks 108>;
 208                                 fsl,usbmisc = <&usbmisc 2>;
 209                                 status = "disabled";
 210                         };
 211
 212                         usbh3: usb@53f80600 {
 213                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 214                                 reg = <0x53f80600 0x0200>;
 215                                 interrupts = <17>;
 216                                 clocks = <&clks 108>;
 217                                 fsl,usbmisc = <&usbmisc 3>;
 218                                 status = "disabled";
 219                         };
 220
 221                         usbmisc: usbmisc@53f80800 {
 222                                 #index-cells = <1>;
 223                                 compatible = "fsl,imx53-usbmisc";
 224                                 reg = <0x53f80800 0x200>;
 225                                 clocks = <&clks 108>;
 226                         };
 227
 228                         gpio1: gpio@53f84000 {
 229                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 230                                 reg = <0x53f84000 0x4000>;
 231                                 interrupts = <50 51>;
 232                                 gpio-controller;
 233                                 #gpio-cells = <2>;
 234                                 interrupt-controller;
 235                                 #interrupt-cells = <2>;
 236                         };
 237
 238                         gpio2: gpio@53f88000 {
 239                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 240                                 reg = <0x53f88000 0x4000>;
 241                                 interrupts = <52 53>;
 242                                 gpio-controller;
 243                                 #gpio-cells = <2>;
 244                                 interrupt-controller;
 245                                 #interrupt-cells = <2>;
 246                         };
 247
 248                         gpio3: gpio@53f8c000 {
 249                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 250                                 reg = <0x53f8c000 0x4000>;
 251                                 interrupts = <54 55>;
 252                                 gpio-controller;
 253                                 #gpio-cells = <2>;
 254                                 interrupt-controller;
 255                                 #interrupt-cells = <2>;
 256                         };
 257
 258                         gpio4: gpio@53f90000 {
 259                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 260                                 reg = <0x53f90000 0x4000>;
 261                                 interrupts = <56 57>;
 262                                 gpio-controller;
 263                                 #gpio-cells = <2>;
 264                                 interrupt-controller;
 265                                 #interrupt-cells = <2>;
 266                         };
 267
 268                         wdog1: wdog@53f98000 {
 269                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 270                                 reg = <0x53f98000 0x4000>;
 271                                 interrupts = <58>;
 272                                 clocks = <&clks 0>;
 273                         };
 274
 275                         wdog2: wdog@53f9c000 {
 276                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 277                                 reg = <0x53f9c000 0x4000>;
 278                                 interrupts = <59>;
 279                                 clocks = <&clks 0>;
 280                                 status = "disabled";
 281                         };
 282
 283                         gpt: timer@53fa0000 {
 284                                 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
 285                                 reg = <0x53fa0000 0x4000>;
 286                                 interrupts = <39>;
 287                                 clocks = <&clks 36>, <&clks 41>;
 288                                 clock-names = "ipg", "per";
 289                         };
 290
 291                         iomuxc: iomuxc@53fa8000 {
 292                                 compatible = "fsl,imx53-iomuxc";
 293                                 reg = <0x53fa8000 0x4000>;
 294
 295                                 audmux {
 296                                         pinctrl_audmux_1: audmuxgrp-1 {
 297                                                 fsl,pins = <
 298                                                         MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x80000000
 299                                                         MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x80000000
 300                                                         MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
 301                                                         MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000
 302                                                 >;
 303                                         };
 304
 305                                         pinctrl_audmux_2: audmuxgrp-2 {
 306                                                 fsl,pins = <
 307                                                         MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC     0x80000000
 308                                                         MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD     0x80000000
 309                                                         MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS    0x80000000
 310                                                         MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD     0x80000000
 311                                                 >;
 312                                         };
 313
 314                                         pinctrl_audmux_3: audmuxgrp-3 {
 315                                                 fsl,pins = <
 316                                                         MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC     0x80000000
 317                                                         MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD     0x80000000
 318                                                         MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS    0x80000000
 319                                                         MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD     0x80000000
 320                                                 >;
 321                                         };
 322                                 };
 323
 324                                 fec {
 325                                         pinctrl_fec_1: fecgrp-1 {
 326                                                 fsl,pins = <
 327                                                         MX53_PAD_FEC_MDC__FEC_MDC        0x80000000
 328                                                         MX53_PAD_FEC_MDIO__FEC_MDIO      0x80000000
 329                                                         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
 330                                                         MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
 331                                                         MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
 332                                                         MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
 333                                                         MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
 334                                                         MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
 335                                                         MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
 336                                                         MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
 337                                                 >;
 338                                         };
 339                                 };
 340
 341                                 csi {
 342                                         pinctrl_csi_1: csigrp-1 {
 343                                                 fsl,pins = <
 344                                                         MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
 345                                                         MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
 346                                                         MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
 347                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
 348                                                         MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
 349                                                         MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
 350                                                         MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
 351                                                         MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
 352                                                         MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
 353                                                         MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
 354                                                         MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
 355                                                         MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
 356                                                         MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11      0x1d5
 357                                                         MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10      0x1d5
 358                                                         MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9        0x1d5
 359                                                         MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8        0x1d5
 360                                                         MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7        0x1d5
 361                                                         MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6        0x1d5
 362                                                         MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5        0x1d5
 363                                                         MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4        0x1d5
 364                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
 365                                                 >;
 366                                         };
 367
 368                                         pinctrl_csi_2: csigrp-2 {
 369                                                 fsl,pins = <
 370                                                         MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
 371                                                         MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
 372                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
 373                                                         MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
 374                                                         MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
 375                                                         MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
 376                                                         MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
 377                                                         MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
 378                                                         MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
 379                                                         MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
 380                                                         MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
 381                                                 >;
 382                                         };
 383                                 };
 384
 385                                 cspi {
 386                                         pinctrl_cspi_1: cspigrp-1 {
 387                                                 fsl,pins = <
 388                                                         MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
 389                                                         MX53_PAD_SD1_CMD__CSPI_MOSI   0x1d5
 390                                                         MX53_PAD_SD1_CLK__CSPI_SCLK   0x1d5
 391                                                 >;
 392                                         };
 393
 394                                         pinctrl_cspi_2: cspigrp-2 {
 395                                                 fsl,pins = <
 396                                                         MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
 397                                                         MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
 398                                                         MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
 399                                                 >;
 400                                         };
 401                                 };
 402
 403                                 ecspi1 {
 404                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 405                                                 fsl,pins = <
 406                                                         MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
 407                                                         MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
 408                                                         MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
 409                                                 >;
 410                                         };
 411
 412                                         pinctrl_ecspi1_2: ecspi1grp-2 {
 413                                                 fsl,pins = <
 414                                                         MX53_PAD_GPIO_19__ECSPI1_RDY    0x80000000
 415                                                         MX53_PAD_EIM_EB2__ECSPI1_SS0    0x80000000
 416                                                         MX53_PAD_EIM_D16__ECSPI1_SCLK   0x80000000
 417                                                         MX53_PAD_EIM_D17__ECSPI1_MISO   0x80000000
 418                                                         MX53_PAD_EIM_D18__ECSPI1_MOSI   0x80000000
 419                                                         MX53_PAD_EIM_D19__ECSPI1_SS1    0x80000000
 420                                                 >;
 421                                         };
 422                                 };
 423
 424                                 esdhc1 {
 425                                         pinctrl_esdhc1_1: esdhc1grp-1 {
 426                                                 fsl,pins = <
 427                                                         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
 428                                                         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
 429                                                         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
 430                                                         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
 431                                                         MX53_PAD_SD1_CMD__ESDHC1_CMD    0x1d5
 432                                                         MX53_PAD_SD1_CLK__ESDHC1_CLK    0x1d5
 433                                                 >;
 434                                         };
 435
 436                                         pinctrl_esdhc1_2: esdhc1grp-2 {
 437                                                 fsl,pins = <
 438                                                         MX53_PAD_SD1_DATA0__ESDHC1_DAT0   0x1d5
 439                                                         MX53_PAD_SD1_DATA1__ESDHC1_DAT1   0x1d5
 440                                                         MX53_PAD_SD1_DATA2__ESDHC1_DAT2   0x1d5
 441                                                         MX53_PAD_SD1_DATA3__ESDHC1_DAT3   0x1d5
 442                                                         MX53_PAD_PATA_DATA8__ESDHC1_DAT4  0x1d5
 443                                                         MX53_PAD_PATA_DATA9__ESDHC1_DAT5  0x1d5
 444                                                         MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
 445                                                         MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
 446                                                         MX53_PAD_SD1_CMD__ESDHC1_CMD      0x1d5
 447                                                         MX53_PAD_SD1_CLK__ESDHC1_CLK      0x1d5
 448                                                 >;
 449                                         };
 450                                 };
 451
 452                                 esdhc2 {
 453                                         pinctrl_esdhc2_1: esdhc2grp-1 {
 454                                                 fsl,pins = <
 455                                                         MX53_PAD_SD2_CMD__ESDHC2_CMD    0x1d5
 456                                                         MX53_PAD_SD2_CLK__ESDHC2_CLK    0x1d5
 457                                                         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
 458                                                         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
 459                                                         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
 460                                                         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
 461                                                 >;
 462                                         };
 463                                 };
 464
 465                                 esdhc3 {
 466                                         pinctrl_esdhc3_1: esdhc3grp-1 {
 467                                                 fsl,pins = <
 468                                                         MX53_PAD_PATA_DATA8__ESDHC3_DAT0  0x1d5
 469                                                         MX53_PAD_PATA_DATA9__ESDHC3_DAT1  0x1d5
 470                                                         MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
 471                                                         MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
 472                                                         MX53_PAD_PATA_DATA0__ESDHC3_DAT4  0x1d5
 473                                                         MX53_PAD_PATA_DATA1__ESDHC3_DAT5  0x1d5
 474                                                         MX53_PAD_PATA_DATA2__ESDHC3_DAT6  0x1d5
 475                                                         MX53_PAD_PATA_DATA3__ESDHC3_DAT7  0x1d5
 476                                                         MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
 477                                                         MX53_PAD_PATA_IORDY__ESDHC3_CLK   0x1d5
 478                                                 >;
 479                                         };
 480                                 };
 481
 482                                 can1 {
 483                                         pinctrl_can1_1: can1grp-1 {
 484                                                 fsl,pins = <
 485                                                         MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
 486                                                         MX53_PAD_PATA_DIOR__CAN1_RXCAN  0x80000000
 487                                                 >;
 488                                         };
 489
 490                                         pinctrl_can1_2: can1grp-2 {
 491                                                 fsl,pins = <
 492                                                         MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
 493                                                         MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
 494                                                 >;
 495                                         };
 496
 497                                         pinctrl_can1_3: can1grp-3 {
 498                                                 fsl,pins = <
 499                                                         MX53_PAD_GPIO_7__CAN1_TXCAN     0x80000000
 500                                                         MX53_PAD_GPIO_8__CAN1_RXCAN     0x80000000
 501                                                 >;
 502                                         };
 503                                 };
 504
 505                                 can2 {
 506                                         pinctrl_can2_1: can2grp-1 {
 507                                                 fsl,pins = <
 508                                                         MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
 509                                                         MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
 510                                                 >;
 511                                         };
 512                                 };
 513
 514                                 i2c1 {
 515                                         pinctrl_i2c1_1: i2c1grp-1 {
 516                                                 fsl,pins = <
 517                                                         MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
 518                                                         MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
 519                                                 >;
 520                                         };
 521
 522                                         pinctrl_i2c1_2: i2c1grp-2 {
 523                                                 fsl,pins = <
 524                                                         MX53_PAD_EIM_D21__I2C1_SCL      0xc0000000
 525                                                         MX53_PAD_EIM_D28__I2C1_SDA      0xc0000000
 526                                                 >;
 527                                         };
 528                                 };
 529
 530                                 i2c2 {
 531                                         pinctrl_i2c2_1: i2c2grp-1 {
 532                                                 fsl,pins = <
 533                                                         MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
 534                                                         MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
 535                                                 >;
 536                                         };
 537
 538                                         pinctrl_i2c2_2: i2c2grp-2 {
 539                                                 fsl,pins = <
 540                                                         MX53_PAD_EIM_D16__I2C2_SDA      0xc0000000
 541                                                         MX53_PAD_EIM_EB2__I2C2_SCL      0xc0000000
 542                                                 >;
 543                                         };
 544                                 };
 545
 546                                 i2c3 {
 547                                         pinctrl_i2c3_1: i2c3grp-1 {
 548                                                 fsl,pins = <
 549                                                         MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
 550                                                         MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
 551                                                 >;
 552                                         };
 553                                 };
 554
 555                                 ipu_disp0 {
 556                                         pinctrl_ipu_disp0_1: ipudisp0grp-1 {
 557                                                 fsl,pins = <
 558                                                 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
 559                                                 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               0x5
 560                                                 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2         0x5
 561                                                 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                 0x5
 562                                                 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            0x5
 563                                                 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            0x5
 564                                                 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            0x5
 565                                                 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            0x5
 566                                                 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            0x5
 567                                                 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            0x5
 568                                                 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            0x5
 569                                                 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            0x5
 570                                                 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            0x5
 571                                                 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            0x5
 572                                                 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          0x5
 573                                                 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          0x5
 574                                                 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          0x5
 575                                                 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          0x5
 576                                                 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          0x5
 577                                                 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          0x5
 578                                                 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          0x5
 579                                                 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          0x5
 580                                                 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          0x5
 581                                                 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          0x5
 582                                                 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          0x5
 583                                                 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          0x5
 584                                                 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          0x5
 585                                                 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          0x5
 586                                                 >;
 587                                         };
 588                                 };
 589
 590                                 ipu_disp1 {
 591                                         pinctrl_ipu_disp1_1: ipudisp1grp-1 {
 592                                                 fsl,pins = <
 593                                                         MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0       0x5
 594                                                         MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1       0x5
 595                                                         MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2       0x5
 596                                                         MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3       0x5
 597                                                         MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4       0x5
 598                                                         MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5       0x5
 599                                                         MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6       0x5
 600                                                         MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7       0x5
 601                                                         MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8       0x5
 602                                                         MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9       0x5
 603                                                         MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10      0x5
 604                                                         MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11      0x5
 605                                                         MX53_PAD_EIM_A17__IPU_DISP1_DAT_12      0x5
 606                                                         MX53_PAD_EIM_A18__IPU_DISP1_DAT_13      0x5
 607                                                         MX53_PAD_EIM_A19__IPU_DISP1_DAT_14      0x5
 608                                                         MX53_PAD_EIM_A20__IPU_DISP1_DAT_15      0x5
 609                                                         MX53_PAD_EIM_A21__IPU_DISP1_DAT_16      0x5
 610                                                         MX53_PAD_EIM_A22__IPU_DISP1_DAT_17      0x5
 611                                                         MX53_PAD_EIM_A23__IPU_DISP1_DAT_18      0x5
 612                                                         MX53_PAD_EIM_A24__IPU_DISP1_DAT_19      0x5
 613                                                         MX53_PAD_EIM_D31__IPU_DISP1_DAT_20      0x5
 614                                                         MX53_PAD_EIM_D30__IPU_DISP1_DAT_21      0x5
 615                                                         MX53_PAD_EIM_D26__IPU_DISP1_DAT_22      0x5
 616                                                         MX53_PAD_EIM_D27__IPU_DISP1_DAT_23      0x5
 617                                                         MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK      0x5
 618                                                         MX53_PAD_EIM_DA13__IPU_DI1_D0_CS        0x5
 619                                                         MX53_PAD_EIM_DA14__IPU_DI1_D1_CS        0x5
 620                                                         MX53_PAD_EIM_DA15__IPU_DI1_PIN1         0x5
 621                                                         MX53_PAD_EIM_DA11__IPU_DI1_PIN2         0x5
 622                                                         MX53_PAD_EIM_DA12__IPU_DI1_PIN3         0x5
 623                                                         MX53_PAD_EIM_A25__IPU_DI1_PIN12         0x5
 624                                                         MX53_PAD_EIM_DA10__IPU_DI1_PIN15        0x5
 625                                                 >;
 626                                         };
 627                                 };
 628
 629                                 ipu_disp2 {
 630                                         pinctrl_ipu_disp2_1: ipudisp2grp-1 {
 631                                                 fsl,pins = <
 632                                                         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0     0x80000000
 633                                                         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1     0x80000000
 634                                                         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2     0x80000000
 635                                                         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3     0x80000000
 636                                                         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK     0x80000000
 637                                                         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0     0x80000000
 638                                                         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1     0x80000000
 639                                                         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2     0x80000000
 640                                                         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3     0x80000000
 641                                                         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK     0x80000000
 642                                                 >;
 643                                         };
 644                                 };
 645
 646                                 nand {
 647                                         pinctrl_nand_1: nandgrp-1 {
 648                                                 fsl,pins = <
 649                                                         MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B     0x4
 650                                                         MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B     0x4
 651                                                         MX53_PAD_NANDF_CLE__EMI_NANDF_CLE       0x4
 652                                                         MX53_PAD_NANDF_ALE__EMI_NANDF_ALE       0x4
 653                                                         MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B     0xe0
 654                                                         MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0      0xe0
 655                                                         MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0      0x4
 656                                                         MX53_PAD_PATA_DATA0__EMI_NANDF_D_0      0xa4
 657                                                         MX53_PAD_PATA_DATA1__EMI_NANDF_D_1      0xa4
 658                                                         MX53_PAD_PATA_DATA2__EMI_NANDF_D_2      0xa4
 659                                                         MX53_PAD_PATA_DATA3__EMI_NANDF_D_3      0xa4
 660                                                         MX53_PAD_PATA_DATA4__EMI_NANDF_D_4      0xa4
 661                                                         MX53_PAD_PATA_DATA5__EMI_NANDF_D_5      0xa4
 662                                                         MX53_PAD_PATA_DATA6__EMI_NANDF_D_6      0xa4
 663                                                         MX53_PAD_PATA_DATA7__EMI_NANDF_D_7      0xa4
 664                                                 >;
 665                                         };
 666                                 };
 667
 668                                 owire {
 669                                         pinctrl_owire_1: owiregrp-1 {
 670                                                 fsl,pins = <
 671                                                         MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
 672                                                 >;
 673                                         };
 674                                 };
 675
 676                                 pwm1 {
 677                                         pinctrl_pwm1_1: pwm1grp-1 {
 678                                                 fsl,pins = <
 679                                                         MX53_PAD_DISP0_DAT8__PWM1_PWMO  0x5
 680                                                 >;
 681                                         };
 682                                 };
 683
 684                                 pwm2 {
 685                                         pinctrl_pwm2_1: pwm2grp-1 {
 686                                                 fsl,pins = <
 687                                                         MX53_PAD_GPIO_1__PWM2_PWMO      0x80000000
 688                                                 >;
 689                                         };
 690                                 };
 691
 692                                 uart1 {
 693                                         pinctrl_uart1_1: uart1grp-1 {
 694                                                 fsl,pins = <
 695                                                         MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
 696                                                         MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
 697                                                 >;
 698                                         };
 699
 700                                         pinctrl_uart1_2: uart1grp-2 {
 701                                                 fsl,pins = <
 702                                                         MX53_PAD_PATA_DIOW__UART1_TXD_MUX  0x1c5
 703                                                         MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
 704                                                 >;
 705                                         };
 706
 707                                         pinctrl_uart1_3: uart1grp-3 {
 708                                                 fsl,pins = <
 709                                                         MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
 710                                                         MX53_PAD_PATA_IORDY__UART1_RTS   0x1c5
 711                                                 >;
 712                                         };
 713                                 };
 714
 715                                 uart2 {
 716                                         pinctrl_uart2_1: uart2grp-1 {
 717                                                 fsl,pins = <
 718                                                         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
 719                                                         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     0x1c5
 720                                                 >;
 721                                         };
 722
 723                                         pinctrl_uart2_2: uart2grp-2 {
 724                                                 fsl,pins = <
 725                                                         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1c5
 726                                                         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1c5
 727                                                         MX53_PAD_PATA_DIOR__UART2_RTS           0x1c5
 728                                                         MX53_PAD_PATA_INTRQ__UART2_CTS          0x1c5
 729                                                 >;
 730                                         };
 731                                 };
 732
 733                                 uart3 {
 734                                         pinctrl_uart3_1: uart3grp-1 {
 735                                                 fsl,pins = <
 736                                                         MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
 737                                                         MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
 738                                                         MX53_PAD_PATA_DA_1__UART3_CTS     0x1c5
 739                                                         MX53_PAD_PATA_DA_2__UART3_RTS     0x1c5
 740                                                 >;
 741                                         };
 742
 743                                         pinctrl_uart3_2: uart3grp-2 {
 744                                                 fsl,pins = <
 745                                                         MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
 746                                                         MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
 747                                                 >;
 748                                         };
 749
 750                                 };
 751
 752                                 uart4 {
 753                                         pinctrl_uart4_1: uart4grp-1 {
 754                                                 fsl,pins = <
 755                                                         MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
 756                                                         MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
 757                                                 >;
 758                                         };
 759                                 };
 760
 761                                 uart5 {
 762                                         pinctrl_uart5_1: uart5grp-1 {
 763                                                 fsl,pins = <
 764                                                         MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
 765                                                         MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
 766                                                 >;
 767                                         };
 768                                 };
 769                         };
 770
 771                         gpr: iomuxc-gpr@53fa8000 {
 772                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
 773                                 reg = <0x53fa8000 0xc>;
 774                         };
 775
 776                         ldb: ldb@53fa8008 {
 777                                 #address-cells = <1>;
 778                                 #size-cells = <0>;
 779                                 compatible = "fsl,imx53-ldb";
 780                                 reg = <0x53fa8008 0x4>;
 781                                 gpr = <&gpr>;
 782                                 clocks = <&clks 122>, <&clks 120>,
 783                                          <&clks 115>, <&clks 116>,
 784                                          <&clks 123>, <&clks 85>;
 785                                 clock-names = "di0_pll", "di1_pll",
 786                                               "di0_sel", "di1_sel",
 787                                               "di0", "di1";
 788                                 status = "disabled";
 789
 790                                 lvds-channel@0 {
 791                                         reg = <0>;
 792                                         crtcs = <&ipu 0>;
 793                                         status = "disabled";
 794                                 };
 795
 796                                 lvds-channel@1 {
 797                                         reg = <1>;
 798                                         crtcs = <&ipu 1>;
 799                                         status = "disabled";
 800                                 };
 801                         };
 802
 803                         pwm1: pwm@53fb4000 {
 804                                 #pwm-cells = <2>;
 805                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 806                                 reg = <0x53fb4000 0x4000>;
 807                                 clocks = <&clks 37>, <&clks 38>;
 808                                 clock-names = "ipg", "per";
 809                                 interrupts = <61>;
 810                         };
 811
 812                         pwm2: pwm@53fb8000 {
 813                                 #pwm-cells = <2>;
 814                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 815                                 reg = <0x53fb8000 0x4000>;
 816                                 clocks = <&clks 39>, <&clks 40>;
 817                                 clock-names = "ipg", "per";
 818                                 interrupts = <94>;
 819                         };
 820
 821                         uart1: serial@53fbc000 {
 822                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 823                                 reg = <0x53fbc000 0x4000>;
 824                                 interrupts = <31>;
 825                                 clocks = <&clks 28>, <&clks 29>;
 826                                 clock-names = "ipg", "per";
 827                                 status = "disabled";
 828                         };
 829
 830                         uart2: serial@53fc0000 {
 831                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 832                                 reg = <0x53fc0000 0x4000>;
 833                                 interrupts = <32>;
 834                                 clocks = <&clks 30>, <&clks 31>;
 835                                 clock-names = "ipg", "per";
 836                                 status = "disabled";
 837                         };
 838
 839                         can1: can@53fc8000 {
 840                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 841                                 reg = <0x53fc8000 0x4000>;
 842                                 interrupts = <82>;
 843                                 clocks = <&clks 158>, <&clks 157>;
 844                                 clock-names = "ipg", "per";
 845                                 status = "disabled";
 846                         };
 847
 848                         can2: can@53fcc000 {
 849                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 850                                 reg = <0x53fcc000 0x4000>;
 851                                 interrupts = <83>;
 852                                 clocks = <&clks 87>, <&clks 86>;
 853                                 clock-names = "ipg", "per";
 854                                 status = "disabled";
 855                         };
 856
 857                         src: src@53fd0000 {
 858                                 compatible = "fsl,imx53-src", "fsl,imx51-src";
 859                                 reg = <0x53fd0000 0x4000>;
 860                                 #reset-cells = <1>;
 861                         };
 862
 863                         clks: ccm@53fd4000{
 864                                 compatible = "fsl,imx53-ccm";
 865                                 reg = <0x53fd4000 0x4000>;
 866                                 interrupts = <0 71 0x04 0 72 0x04>;
 867                                 #clock-cells = <1>;
 868                         };
 869
 870                         gpio5: gpio@53fdc000 {
 871                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 872                                 reg = <0x53fdc000 0x4000>;
 873                                 interrupts = <103 104>;
 874                                 gpio-controller;
 875                                 #gpio-cells = <2>;
 876                                 interrupt-controller;
 877                                 #interrupt-cells = <2>;
 878                         };
 879
 880                         gpio6: gpio@53fe0000 {
 881                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 882                                 reg = <0x53fe0000 0x4000>;
 883                                 interrupts = <105 106>;
 884                                 gpio-controller;
 885                                 #gpio-cells = <2>;
 886                                 interrupt-controller;
 887                                 #interrupt-cells = <2>;
 888                         };
 889
 890                         gpio7: gpio@53fe4000 {
 891                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 892                                 reg = <0x53fe4000 0x4000>;
 893                                 interrupts = <107 108>;
 894                                 gpio-controller;
 895                                 #gpio-cells = <2>;
 896                                 interrupt-controller;
 897                                 #interrupt-cells = <2>;
 898                         };
 899
 900                         i2c3: i2c@53fec000 {
 901                                 #address-cells = <1>;
 902                                 #size-cells = <0>;
 903                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 904                                 reg = <0x53fec000 0x4000>;
 905                                 interrupts = <64>;
 906                                 clocks = <&clks 88>;
 907                                 status = "disabled";
 908                         };
 909
 910                         uart4: serial@53ff0000 {
 911                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 912                                 reg = <0x53ff0000 0x4000>;
 913                                 interrupts = <13>;
 914                                 clocks = <&clks 65>, <&clks 66>;
 915                                 clock-names = "ipg", "per";
 916                                 status = "disabled";
 917                         };
 918                 };
 919
 920                 aips@60000000 { /* AIPS2 */
 921                         compatible = "fsl,aips-bus", "simple-bus";
 922                         #address-cells = <1>;
 923                         #size-cells = <1>;
 924                         reg = <0x60000000 0x10000000>;
 925                         ranges;
 926
 927                         uart5: serial@63f90000 {
 928                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 929                                 reg = <0x63f90000 0x4000>;
 930                                 interrupts = <86>;
 931                                 clocks = <&clks 67>, <&clks 68>;
 932                                 clock-names = "ipg", "per";
 933                                 status = "disabled";
 934                         };
 935
 936                         owire: owire@63fa4000 {
 937                                 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
 938                                 reg = <0x63fa4000 0x4000>;
 939                                 clocks = <&clks 159>;
 940                                 status = "disabled";
 941                         };
 942
 943                         ecspi2: ecspi@63fac000 {
 944                                 #address-cells = <1>;
 945                                 #size-cells = <0>;
 946                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 947                                 reg = <0x63fac000 0x4000>;
 948                                 interrupts = <37>;
 949                                 clocks = <&clks 53>, <&clks 54>;
 950                                 clock-names = "ipg", "per";
 951                                 status = "disabled";
 952                         };
 953
 954                         sdma: sdma@63fb0000 {
 955                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 956                                 reg = <0x63fb0000 0x4000>;
 957                                 interrupts = <6>;
 958                                 clocks = <&clks 56>, <&clks 56>;
 959                                 clock-names = "ipg", "ahb";
 960                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 961                         };
 962
 963                         cspi: cspi@63fc0000 {
 964                                 #address-cells = <1>;
 965                                 #size-cells = <0>;
 966                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 967                                 reg = <0x63fc0000 0x4000>;
 968                                 interrupts = <38>;
 969                                 clocks = <&clks 55>, <&clks 55>;
 970                                 clock-names = "ipg", "per";
 971                                 status = "disabled";
 972                         };
 973
 974                         i2c2: i2c@63fc4000 {
 975                                 #address-cells = <1>;
 976                                 #size-cells = <0>;
 977                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 978                                 reg = <0x63fc4000 0x4000>;
 979                                 interrupts = <63>;
 980                                 clocks = <&clks 35>;
 981                                 status = "disabled";
 982                         };
 983
 984                         i2c1: i2c@63fc8000 {
 985                                 #address-cells = <1>;
 986                                 #size-cells = <0>;
 987                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 988                                 reg = <0x63fc8000 0x4000>;
 989                                 interrupts = <62>;
 990                                 clocks = <&clks 34>;
 991                                 status = "disabled";
 992                         };
 993
 994                         ssi1: ssi@63fcc000 {
 995                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 996                                 reg = <0x63fcc000 0x4000>;
 997                                 interrupts = <29>;
 998                                 clocks = <&clks 48>;
 999                                 fsl,fifo-depth = <15>;
1000                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
1001                                 status = "disabled";
1002                         };
1003
1004                         audmux: audmux@63fd0000 {
1005                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
1006                                 reg = <0x63fd0000 0x4000>;
1007                                 status = "disabled";
1008                         };
1009
1010                         nfc: nand@63fdb000 {
1011                                 compatible = "fsl,imx53-nand";
1012                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
1013                                 interrupts = <8>;
1014                                 clocks = <&clks 60>;
1015                                 status = "disabled";
1016                         };
1017
1018                         ssi3: ssi@63fe8000 {
1019                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
1020                                 reg = <0x63fe8000 0x4000>;
1021                                 interrupts = <96>;
1022                                 clocks = <&clks 50>;
1023                                 fsl,fifo-depth = <15>;
1024                                 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
1025                                 status = "disabled";
1026                         };
1027
1028                         fec: ethernet@63fec000 {
1029                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
1030                                 reg = <0x63fec000 0x4000>;
1031                                 interrupts = <87>;
1032                                 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
1033                                 clock-names = "ipg", "ahb", "ptp";
1034                                 status = "disabled";
1035                         };
1036                 };
1037         };
1038 };