2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
50 compatible = "arm,cortex-a8";
56 compatible = "fsl,imx-display-subsystem";
57 ports = <&ipu_di0>, <&ipu_di1>;
60 tzic: tz-interrupt-controller@0fffc000 {
61 compatible = "fsl,imx53-tzic", "fsl,tzic";
63 #interrupt-cells = <1>;
64 reg = <0x0fffc000 0x4000>;
72 compatible = "fsl,imx-ckil", "fixed-clock";
73 clock-frequency = <32768>;
77 compatible = "fsl,imx-ckih1", "fixed-clock";
78 clock-frequency = <22579200>;
82 compatible = "fsl,imx-ckih2", "fixed-clock";
83 clock-frequency = <0>;
87 compatible = "fsl,imx-osc", "fixed-clock";
88 clock-frequency = <24000000>;
95 compatible = "simple-bus";
96 interrupt-parent = <&tzic>;
100 compatible = "fsl,imx53-ahci";
101 reg = <0x10000000 0x1000>;
103 clocks = <&clks IMX5_CLK_SATA_GATE>,
104 <&clks IMX5_CLK_SATA_REF>,
105 <&clks IMX5_CLK_AHB>;
106 clock-names = "sata_gate", "sata_ref", "ahb";
111 #address-cells = <1>;
113 compatible = "fsl,imx53-ipu";
114 reg = <0x18000000 0x080000000>;
115 interrupts = <11 10>;
116 clocks = <&clks IMX5_CLK_IPU_GATE>,
117 <&clks IMX5_CLK_IPU_DI0_GATE>,
118 <&clks IMX5_CLK_IPU_DI1_GATE>;
119 clock-names = "bus", "di0", "di1";
123 #address-cells = <1>;
127 ipu_di0_disp0: endpoint@0 {
131 ipu_di0_lvds0: endpoint@1 {
133 remote-endpoint = <&lvds0_in>;
138 #address-cells = <1>;
142 ipu_di1_disp1: endpoint@0 {
146 ipu_di1_lvds1: endpoint@1 {
148 remote-endpoint = <&lvds1_in>;
151 ipu_di1_tve: endpoint@2 {
153 remote-endpoint = <&tve_in>;
158 aips@50000000 { /* AIPS1 */
159 compatible = "fsl,aips-bus", "simple-bus";
160 #address-cells = <1>;
162 reg = <0x50000000 0x10000000>;
166 compatible = "fsl,spba-bus", "simple-bus";
167 #address-cells = <1>;
169 reg = <0x50000000 0x40000>;
172 esdhc1: esdhc@50004000 {
173 compatible = "fsl,imx53-esdhc";
174 reg = <0x50004000 0x4000>;
176 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
177 <&clks IMX5_CLK_DUMMY>,
178 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
179 clock-names = "ipg", "ahb", "per";
184 esdhc2: esdhc@50008000 {
185 compatible = "fsl,imx53-esdhc";
186 reg = <0x50008000 0x4000>;
188 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
189 <&clks IMX5_CLK_DUMMY>,
190 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
191 clock-names = "ipg", "ahb", "per";
196 uart3: serial@5000c000 {
197 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
198 reg = <0x5000c000 0x4000>;
200 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
201 <&clks IMX5_CLK_UART3_PER_GATE>;
202 clock-names = "ipg", "per";
206 ecspi1: ecspi@50010000 {
207 #address-cells = <1>;
209 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
210 reg = <0x50010000 0x4000>;
212 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
213 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
214 clock-names = "ipg", "per";
219 compatible = "fsl,imx53-ssi",
222 reg = <0x50014000 0x4000>;
224 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
225 dmas = <&sdma 24 1 0>,
227 dma-names = "rx", "tx";
228 fsl,fifo-depth = <15>;
229 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
233 esdhc3: esdhc@50020000 {
234 compatible = "fsl,imx53-esdhc";
235 reg = <0x50020000 0x4000>;
237 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
238 <&clks IMX5_CLK_DUMMY>,
239 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
240 clock-names = "ipg", "ahb", "per";
245 esdhc4: esdhc@50024000 {
246 compatible = "fsl,imx53-esdhc";
247 reg = <0x50024000 0x4000>;
249 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
250 <&clks IMX5_CLK_DUMMY>,
251 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
252 clock-names = "ipg", "ahb", "per";
259 compatible = "usb-nop-xceiv";
260 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
261 clock-names = "main_clk";
266 compatible = "usb-nop-xceiv";
267 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
268 clock-names = "main_clk";
272 usbotg: usb@53f80000 {
273 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
274 reg = <0x53f80000 0x0200>;
276 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
277 fsl,usbmisc = <&usbmisc 0>;
278 fsl,usbphy = <&usbphy0>;
282 usbh1: usb@53f80200 {
283 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
284 reg = <0x53f80200 0x0200>;
286 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
287 fsl,usbmisc = <&usbmisc 1>;
288 fsl,usbphy = <&usbphy1>;
292 usbh2: usb@53f80400 {
293 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
294 reg = <0x53f80400 0x0200>;
296 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
297 fsl,usbmisc = <&usbmisc 2>;
301 usbh3: usb@53f80600 {
302 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
303 reg = <0x53f80600 0x0200>;
305 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
306 fsl,usbmisc = <&usbmisc 3>;
310 usbmisc: usbmisc@53f80800 {
312 compatible = "fsl,imx53-usbmisc";
313 reg = <0x53f80800 0x200>;
314 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
317 gpio1: gpio@53f84000 {
318 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
319 reg = <0x53f84000 0x4000>;
320 interrupts = <50 51>;
323 interrupt-controller;
324 #interrupt-cells = <2>;
327 gpio2: gpio@53f88000 {
328 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
329 reg = <0x53f88000 0x4000>;
330 interrupts = <52 53>;
333 interrupt-controller;
334 #interrupt-cells = <2>;
337 gpio3: gpio@53f8c000 {
338 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
339 reg = <0x53f8c000 0x4000>;
340 interrupts = <54 55>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
347 gpio4: gpio@53f90000 {
348 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
349 reg = <0x53f90000 0x4000>;
350 interrupts = <56 57>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
358 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
359 reg = <0x53f94000 0x4000>;
361 clocks = <&clks IMX5_CLK_DUMMY>;
365 wdog1: wdog@53f98000 {
366 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
367 reg = <0x53f98000 0x4000>;
369 clocks = <&clks IMX5_CLK_DUMMY>;
372 wdog2: wdog@53f9c000 {
373 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
374 reg = <0x53f9c000 0x4000>;
376 clocks = <&clks IMX5_CLK_DUMMY>;
380 gpt: timer@53fa0000 {
381 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
382 reg = <0x53fa0000 0x4000>;
384 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
385 <&clks IMX5_CLK_GPT_HF_GATE>;
386 clock-names = "ipg", "per";
389 iomuxc: iomuxc@53fa8000 {
390 compatible = "fsl,imx53-iomuxc";
391 reg = <0x53fa8000 0x4000>;
394 gpr: iomuxc-gpr@53fa8000 {
395 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
396 reg = <0x53fa8000 0xc>;
400 #address-cells = <1>;
402 compatible = "fsl,imx53-ldb";
403 reg = <0x53fa8008 0x4>;
405 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
406 <&clks IMX5_CLK_LDB_DI1_SEL>,
407 <&clks IMX5_CLK_IPU_DI0_SEL>,
408 <&clks IMX5_CLK_IPU_DI1_SEL>,
409 <&clks IMX5_CLK_LDB_DI0_GATE>,
410 <&clks IMX5_CLK_LDB_DI1_GATE>;
411 clock-names = "di0_pll", "di1_pll",
412 "di0_sel", "di1_sel",
422 remote-endpoint = <&ipu_di0_lvds0>;
433 remote-endpoint = <&ipu_di0_lvds0>;
441 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
442 reg = <0x53fb4000 0x4000>;
443 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
444 <&clks IMX5_CLK_PWM1_HF_GATE>;
445 clock-names = "ipg", "per";
451 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
452 reg = <0x53fb8000 0x4000>;
453 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
454 <&clks IMX5_CLK_PWM2_HF_GATE>;
455 clock-names = "ipg", "per";
459 uart1: serial@53fbc000 {
460 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
461 reg = <0x53fbc000 0x4000>;
463 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
464 <&clks IMX5_CLK_UART1_PER_GATE>;
465 clock-names = "ipg", "per";
469 uart2: serial@53fc0000 {
470 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
471 reg = <0x53fc0000 0x4000>;
473 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
474 <&clks IMX5_CLK_UART2_PER_GATE>;
475 clock-names = "ipg", "per";
480 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
481 reg = <0x53fc8000 0x4000>;
483 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
484 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
485 clock-names = "ipg", "per";
490 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
491 reg = <0x53fcc000 0x4000>;
493 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
494 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
495 clock-names = "ipg", "per";
500 compatible = "fsl,imx53-src", "fsl,imx51-src";
501 reg = <0x53fd0000 0x4000>;
506 compatible = "fsl,imx53-ccm";
507 reg = <0x53fd4000 0x4000>;
508 interrupts = <0 71 0x04 0 72 0x04>;
512 gpio5: gpio@53fdc000 {
513 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
514 reg = <0x53fdc000 0x4000>;
515 interrupts = <103 104>;
518 interrupt-controller;
519 #interrupt-cells = <2>;
522 gpio6: gpio@53fe0000 {
523 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
524 reg = <0x53fe0000 0x4000>;
525 interrupts = <105 106>;
528 interrupt-controller;
529 #interrupt-cells = <2>;
532 gpio7: gpio@53fe4000 {
533 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
534 reg = <0x53fe4000 0x4000>;
535 interrupts = <107 108>;
538 interrupt-controller;
539 #interrupt-cells = <2>;
543 #address-cells = <1>;
545 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
546 reg = <0x53fec000 0x4000>;
548 clocks = <&clks IMX5_CLK_I2C3_GATE>;
552 uart4: serial@53ff0000 {
553 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
554 reg = <0x53ff0000 0x4000>;
556 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
557 <&clks IMX5_CLK_UART4_PER_GATE>;
558 clock-names = "ipg", "per";
563 aips@60000000 { /* AIPS2 */
564 compatible = "fsl,aips-bus", "simple-bus";
565 #address-cells = <1>;
567 reg = <0x60000000 0x10000000>;
571 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
572 reg = <0x63f98000 0x4000>;
574 clocks = <&clks IMX5_CLK_IIM_GATE>;
577 uart5: serial@63f90000 {
578 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
579 reg = <0x63f90000 0x4000>;
581 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
582 <&clks IMX5_CLK_UART5_PER_GATE>;
583 clock-names = "ipg", "per";
587 owire: owire@63fa4000 {
588 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
589 reg = <0x63fa4000 0x4000>;
590 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
594 ecspi2: ecspi@63fac000 {
595 #address-cells = <1>;
597 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
598 reg = <0x63fac000 0x4000>;
600 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
601 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
602 clock-names = "ipg", "per";
606 sdma: sdma@63fb0000 {
607 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
608 reg = <0x63fb0000 0x4000>;
610 clocks = <&clks IMX5_CLK_SDMA_GATE>,
611 <&clks IMX5_CLK_SDMA_GATE>;
612 clock-names = "ipg", "ahb";
614 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
617 cspi: cspi@63fc0000 {
618 #address-cells = <1>;
620 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
621 reg = <0x63fc0000 0x4000>;
623 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
624 <&clks IMX5_CLK_CSPI_IPG_GATE>;
625 clock-names = "ipg", "per";
630 #address-cells = <1>;
632 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
633 reg = <0x63fc4000 0x4000>;
635 clocks = <&clks IMX5_CLK_I2C2_GATE>;
640 #address-cells = <1>;
642 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
643 reg = <0x63fc8000 0x4000>;
645 clocks = <&clks IMX5_CLK_I2C1_GATE>;
650 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
652 reg = <0x63fcc000 0x4000>;
654 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
655 dmas = <&sdma 28 0 0>,
657 dma-names = "rx", "tx";
658 fsl,fifo-depth = <15>;
659 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
663 audmux: audmux@63fd0000 {
664 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
665 reg = <0x63fd0000 0x4000>;
670 compatible = "fsl,imx53-nand";
671 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
673 clocks = <&clks IMX5_CLK_NFC_GATE>;
678 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
680 reg = <0x63fe8000 0x4000>;
682 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
683 dmas = <&sdma 46 0 0>,
685 dma-names = "rx", "tx";
686 fsl,fifo-depth = <15>;
687 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
691 fec: ethernet@63fec000 {
692 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
693 reg = <0x63fec000 0x4000>;
695 clocks = <&clks IMX5_CLK_FEC_GATE>,
696 <&clks IMX5_CLK_FEC_GATE>,
697 <&clks IMX5_CLK_FEC_GATE>;
698 clock-names = "ipg", "ahb", "ptp";
703 compatible = "fsl,imx53-tve";
704 reg = <0x63ff0000 0x1000>;
706 clocks = <&clks IMX5_CLK_TVE_GATE>,
707 <&clks IMX5_CLK_IPU_DI1_SEL>;
708 clock-names = "tve", "di_sel";
713 remote-endpoint = <&ipu_di1_tve>;
719 compatible = "fsl,imx53-vpu";
720 reg = <0x63ff4000 0x1000>;
722 clocks = <&clks IMX5_CLK_VPU_GATE>,
723 <&clks IMX5_CLK_VPU_GATE>;
724 clock-names = "per", "ahb";
730 ocram: sram@f8000000 {
731 compatible = "mmio-sram";
732 reg = <0xf8000000 0x20000>;
733 clocks = <&clks IMX5_CLK_OCRAM>;