2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
50 compatible = "arm,cortex-a8";
56 compatible = "fsl,imx-display-subsystem";
57 ports = <&ipu_di0>, <&ipu_di1>;
60 tzic: tz-interrupt-controller@0fffc000 {
61 compatible = "fsl,imx53-tzic", "fsl,tzic";
63 #interrupt-cells = <1>;
64 reg = <0x0fffc000 0x4000>;
72 compatible = "fsl,imx-ckil", "fixed-clock";
74 clock-frequency = <32768>;
78 compatible = "fsl,imx-ckih1", "fixed-clock";
80 clock-frequency = <22579200>;
84 compatible = "fsl,imx-ckih2", "fixed-clock";
86 clock-frequency = <0>;
90 compatible = "fsl,imx-osc", "fixed-clock";
92 clock-frequency = <24000000>;
99 compatible = "simple-bus";
100 interrupt-parent = <&tzic>;
103 sata: sata@10000000 {
104 compatible = "fsl,imx53-ahci";
105 reg = <0x10000000 0x1000>;
107 clocks = <&clks IMX5_CLK_SATA_GATE>,
108 <&clks IMX5_CLK_SATA_REF>,
109 <&clks IMX5_CLK_AHB>;
110 clock-names = "sata_gate", "sata_ref", "ahb";
115 #address-cells = <1>;
117 compatible = "fsl,imx53-ipu";
118 reg = <0x18000000 0x080000000>;
119 interrupts = <11 10>;
120 clocks = <&clks IMX5_CLK_IPU_GATE>,
121 <&clks IMX5_CLK_IPU_DI0_GATE>,
122 <&clks IMX5_CLK_IPU_DI1_GATE>;
123 clock-names = "bus", "di0", "di1";
127 #address-cells = <1>;
131 ipu_di0_disp0: endpoint@0 {
135 ipu_di0_lvds0: endpoint@1 {
137 remote-endpoint = <&lvds0_in>;
142 #address-cells = <1>;
146 ipu_di1_disp1: endpoint@0 {
150 ipu_di1_lvds1: endpoint@1 {
152 remote-endpoint = <&lvds1_in>;
155 ipu_di1_tve: endpoint@2 {
157 remote-endpoint = <&tve_in>;
162 aips@50000000 { /* AIPS1 */
163 compatible = "fsl,aips-bus", "simple-bus";
164 #address-cells = <1>;
166 reg = <0x50000000 0x10000000>;
170 compatible = "fsl,spba-bus", "simple-bus";
171 #address-cells = <1>;
173 reg = <0x50000000 0x40000>;
176 esdhc1: esdhc@50004000 {
177 compatible = "fsl,imx53-esdhc";
178 reg = <0x50004000 0x4000>;
180 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
181 <&clks IMX5_CLK_DUMMY>,
182 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
183 clock-names = "ipg", "ahb", "per";
188 esdhc2: esdhc@50008000 {
189 compatible = "fsl,imx53-esdhc";
190 reg = <0x50008000 0x4000>;
192 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
193 <&clks IMX5_CLK_DUMMY>,
194 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
195 clock-names = "ipg", "ahb", "per";
200 uart3: serial@5000c000 {
201 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
202 reg = <0x5000c000 0x4000>;
204 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
205 <&clks IMX5_CLK_UART3_PER_GATE>;
206 clock-names = "ipg", "per";
210 ecspi1: ecspi@50010000 {
211 #address-cells = <1>;
213 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
214 reg = <0x50010000 0x4000>;
216 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
217 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
218 clock-names = "ipg", "per";
223 compatible = "fsl,imx53-ssi",
226 reg = <0x50014000 0x4000>;
228 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
229 dmas = <&sdma 24 1 0>,
231 dma-names = "rx", "tx";
232 fsl,fifo-depth = <15>;
233 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
237 esdhc3: esdhc@50020000 {
238 compatible = "fsl,imx53-esdhc";
239 reg = <0x50020000 0x4000>;
241 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
242 <&clks IMX5_CLK_DUMMY>,
243 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
244 clock-names = "ipg", "ahb", "per";
249 esdhc4: esdhc@50024000 {
250 compatible = "fsl,imx53-esdhc";
251 reg = <0x50024000 0x4000>;
253 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
254 <&clks IMX5_CLK_DUMMY>,
255 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
256 clock-names = "ipg", "ahb", "per";
263 compatible = "usb-nop-xceiv";
264 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
265 clock-names = "main_clk";
270 compatible = "usb-nop-xceiv";
271 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
272 clock-names = "main_clk";
276 usbotg: usb@53f80000 {
277 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
278 reg = <0x53f80000 0x0200>;
280 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
281 fsl,usbmisc = <&usbmisc 0>;
282 fsl,usbphy = <&usbphy0>;
286 usbh1: usb@53f80200 {
287 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
288 reg = <0x53f80200 0x0200>;
290 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
291 fsl,usbmisc = <&usbmisc 1>;
292 fsl,usbphy = <&usbphy1>;
296 usbh2: usb@53f80400 {
297 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
298 reg = <0x53f80400 0x0200>;
300 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
301 fsl,usbmisc = <&usbmisc 2>;
305 usbh3: usb@53f80600 {
306 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
307 reg = <0x53f80600 0x0200>;
309 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
310 fsl,usbmisc = <&usbmisc 3>;
314 usbmisc: usbmisc@53f80800 {
316 compatible = "fsl,imx53-usbmisc";
317 reg = <0x53f80800 0x200>;
318 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
321 gpio1: gpio@53f84000 {
322 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
323 reg = <0x53f84000 0x4000>;
324 interrupts = <50 51>;
327 interrupt-controller;
328 #interrupt-cells = <2>;
331 gpio2: gpio@53f88000 {
332 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
333 reg = <0x53f88000 0x4000>;
334 interrupts = <52 53>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
341 gpio3: gpio@53f8c000 {
342 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
343 reg = <0x53f8c000 0x4000>;
344 interrupts = <54 55>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
351 gpio4: gpio@53f90000 {
352 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
353 reg = <0x53f90000 0x4000>;
354 interrupts = <56 57>;
357 interrupt-controller;
358 #interrupt-cells = <2>;
362 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
363 reg = <0x53f94000 0x4000>;
365 clocks = <&clks IMX5_CLK_DUMMY>;
369 wdog1: wdog@53f98000 {
370 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
371 reg = <0x53f98000 0x4000>;
373 clocks = <&clks IMX5_CLK_DUMMY>;
376 wdog2: wdog@53f9c000 {
377 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
378 reg = <0x53f9c000 0x4000>;
380 clocks = <&clks IMX5_CLK_DUMMY>;
384 gpt: timer@53fa0000 {
385 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
386 reg = <0x53fa0000 0x4000>;
388 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
389 <&clks IMX5_CLK_GPT_HF_GATE>;
390 clock-names = "ipg", "per";
393 iomuxc: iomuxc@53fa8000 {
394 compatible = "fsl,imx53-iomuxc";
395 reg = <0x53fa8000 0x4000>;
398 gpr: iomuxc-gpr@53fa8000 {
399 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
400 reg = <0x53fa8000 0xc>;
404 #address-cells = <1>;
406 compatible = "fsl,imx53-ldb";
407 reg = <0x53fa8008 0x4>;
409 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
410 <&clks IMX5_CLK_LDB_DI1_SEL>,
411 <&clks IMX5_CLK_IPU_DI0_SEL>,
412 <&clks IMX5_CLK_IPU_DI1_SEL>,
413 <&clks IMX5_CLK_LDB_DI0_GATE>,
414 <&clks IMX5_CLK_LDB_DI1_GATE>;
415 clock-names = "di0_pll", "di1_pll",
416 "di0_sel", "di1_sel",
426 remote-endpoint = <&ipu_di0_lvds0>;
437 remote-endpoint = <&ipu_di1_lvds1>;
445 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
446 reg = <0x53fb4000 0x4000>;
447 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
448 <&clks IMX5_CLK_PWM1_HF_GATE>;
449 clock-names = "ipg", "per";
455 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
456 reg = <0x53fb8000 0x4000>;
457 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
458 <&clks IMX5_CLK_PWM2_HF_GATE>;
459 clock-names = "ipg", "per";
463 uart1: serial@53fbc000 {
464 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
465 reg = <0x53fbc000 0x4000>;
467 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
468 <&clks IMX5_CLK_UART1_PER_GATE>;
469 clock-names = "ipg", "per";
473 uart2: serial@53fc0000 {
474 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
475 reg = <0x53fc0000 0x4000>;
477 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
478 <&clks IMX5_CLK_UART2_PER_GATE>;
479 clock-names = "ipg", "per";
484 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
485 reg = <0x53fc8000 0x4000>;
487 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
488 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
489 clock-names = "ipg", "per";
494 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
495 reg = <0x53fcc000 0x4000>;
497 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
498 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
499 clock-names = "ipg", "per";
504 compatible = "fsl,imx53-src", "fsl,imx51-src";
505 reg = <0x53fd0000 0x4000>;
510 compatible = "fsl,imx53-ccm";
511 reg = <0x53fd4000 0x4000>;
512 interrupts = <0 71 0x04 0 72 0x04>;
516 gpio5: gpio@53fdc000 {
517 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
518 reg = <0x53fdc000 0x4000>;
519 interrupts = <103 104>;
522 interrupt-controller;
523 #interrupt-cells = <2>;
526 gpio6: gpio@53fe0000 {
527 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
528 reg = <0x53fe0000 0x4000>;
529 interrupts = <105 106>;
532 interrupt-controller;
533 #interrupt-cells = <2>;
536 gpio7: gpio@53fe4000 {
537 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
538 reg = <0x53fe4000 0x4000>;
539 interrupts = <107 108>;
542 interrupt-controller;
543 #interrupt-cells = <2>;
547 #address-cells = <1>;
549 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
550 reg = <0x53fec000 0x4000>;
552 clocks = <&clks IMX5_CLK_I2C3_GATE>;
556 uart4: serial@53ff0000 {
557 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
558 reg = <0x53ff0000 0x4000>;
560 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
561 <&clks IMX5_CLK_UART4_PER_GATE>;
562 clock-names = "ipg", "per";
567 aips@60000000 { /* AIPS2 */
568 compatible = "fsl,aips-bus", "simple-bus";
569 #address-cells = <1>;
571 reg = <0x60000000 0x10000000>;
575 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
576 reg = <0x63f98000 0x4000>;
578 clocks = <&clks IMX5_CLK_IIM_GATE>;
581 uart5: serial@63f90000 {
582 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
583 reg = <0x63f90000 0x4000>;
585 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
586 <&clks IMX5_CLK_UART5_PER_GATE>;
587 clock-names = "ipg", "per";
591 owire: owire@63fa4000 {
592 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
593 reg = <0x63fa4000 0x4000>;
594 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
598 ecspi2: ecspi@63fac000 {
599 #address-cells = <1>;
601 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
602 reg = <0x63fac000 0x4000>;
604 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
605 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
606 clock-names = "ipg", "per";
610 sdma: sdma@63fb0000 {
611 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
612 reg = <0x63fb0000 0x4000>;
614 clocks = <&clks IMX5_CLK_SDMA_GATE>,
615 <&clks IMX5_CLK_SDMA_GATE>;
616 clock-names = "ipg", "ahb";
618 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
621 cspi: cspi@63fc0000 {
622 #address-cells = <1>;
624 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
625 reg = <0x63fc0000 0x4000>;
627 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
628 <&clks IMX5_CLK_CSPI_IPG_GATE>;
629 clock-names = "ipg", "per";
634 #address-cells = <1>;
636 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
637 reg = <0x63fc4000 0x4000>;
639 clocks = <&clks IMX5_CLK_I2C2_GATE>;
644 #address-cells = <1>;
646 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
647 reg = <0x63fc8000 0x4000>;
649 clocks = <&clks IMX5_CLK_I2C1_GATE>;
654 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
656 reg = <0x63fcc000 0x4000>;
658 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
659 dmas = <&sdma 28 0 0>,
661 dma-names = "rx", "tx";
662 fsl,fifo-depth = <15>;
663 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
667 audmux: audmux@63fd0000 {
668 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
669 reg = <0x63fd0000 0x4000>;
674 compatible = "fsl,imx53-nand";
675 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
677 clocks = <&clks IMX5_CLK_NFC_GATE>;
682 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
684 reg = <0x63fe8000 0x4000>;
686 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
687 dmas = <&sdma 46 0 0>,
689 dma-names = "rx", "tx";
690 fsl,fifo-depth = <15>;
691 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
695 fec: ethernet@63fec000 {
696 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
697 reg = <0x63fec000 0x4000>;
699 clocks = <&clks IMX5_CLK_FEC_GATE>,
700 <&clks IMX5_CLK_FEC_GATE>,
701 <&clks IMX5_CLK_FEC_GATE>;
702 clock-names = "ipg", "ahb", "ptp";
707 compatible = "fsl,imx53-tve";
708 reg = <0x63ff0000 0x1000>;
710 clocks = <&clks IMX5_CLK_TVE_GATE>,
711 <&clks IMX5_CLK_IPU_DI1_SEL>;
712 clock-names = "tve", "di_sel";
717 remote-endpoint = <&ipu_di1_tve>;
723 compatible = "fsl,imx53-vpu";
724 reg = <0x63ff4000 0x1000>;
726 clocks = <&clks IMX5_CLK_VPU_GATE>,
727 <&clks IMX5_CLK_VPU_GATE>;
728 clock-names = "per", "ahb";
734 ocram: sram@f8000000 {
735 compatible = "mmio-sram";
736 reg = <0xf8000000 0x20000>;
737 clocks = <&clks IMX5_CLK_OCRAM>;