arch/arm/boot/dts/imx6dl.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include "imx6qdl.dtsi"
  12 #include "imx6dl-pinfunc.h"
  13
  14 / {
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                 };
  25
  26                 cpu@1 {
  27                         compatible = "arm,cortex-a9";
  28                         device_type = "cpu";
  29                         reg = <1>;
  30                         next-level-cache = <&L2>;
  31                 };
  32         };
  33
  34         soc {
  35                 aips1: aips-bus@02000000 {
  36                         iomuxc: iomuxc@020e0000 {
  37                                 compatible = "fsl,imx6dl-iomuxc";
  38                                 reg = <0x020e0000 0x4000>;
  39
  40                                 audmux {
  41                                         pinctrl_audmux_1: audmux-1 {
  42                                                 fsl,pins = <
  43                                                         MX6DL_PAD_SD2_DAT0__AUD4_RXD  0x80000000
  44                                                         MX6DL_PAD_SD2_DAT3__AUD4_TXC  0x80000000
  45                                                         MX6DL_PAD_SD2_DAT2__AUD4_TXD  0x80000000
  46                                                         MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
  47                                                 >;
  48                                         };
  49
  50                                         pinctrl_audmux_2: audmux-2 {
  51                                                 fsl,pins = <
  52                                                         MX6DL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
  53                                                         MX6DL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
  54                                                         MX6DL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
  55                                                         MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
  56                                                 >;
  57                                         };
  58                                 };
  59
  60                                 ecspi1 {
  61                                         pinctrl_ecspi1_1: ecspi1grp-1 {
  62                                                 fsl,pins = <
  63                                                         MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  64                                                         MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  65                                                         MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  66                                                 >;
  67                                         };
  68
  69                                         pinctrl_ecspi1_2: ecspi1grp-2 {
  70                                                 fsl,pins = <
  71                                                         MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
  72                                                         MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
  73                                                         MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
  74                                                 >;
  75                                         };
  76                                 };
  77
  78                                 ecspi3 {
  79                                         pinctrl_ecspi3_1: ecspi3grp-1 {
  80                                                 fsl,pins = <
  81                                                         MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
  82                                                         MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
  83                                                         MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
  84                                                 >;
  85                                         };
  86                                 };
  87
  88                                 enet {
  89                                         pinctrl_enet_1: enetgrp-1 {
  90                                                 fsl,pins = <
  91                                                         MX6DL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
  92                                                         MX6DL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
  93                                                         MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
  94                                                         MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
  95                                                         MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
  96                                                         MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
  97                                                         MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
  98                                                         MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  99                                                         MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 100                                                         MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 101                                                         MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 102                                                         MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 103                                                         MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 104                                                         MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 105                                                         MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 106                                                         MX6DL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
 107                                                 >;
 108                                         };
 109
 110                                         pinctrl_enet_2: enetgrp-2 {
 111                                                 fsl,pins = <
 112                                                         MX6DL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
 113                                                         MX6DL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
 114                                                         MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 115                                                         MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 116                                                         MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 117                                                         MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 118                                                         MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 119                                                         MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 120                                                         MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 121                                                         MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 122                                                         MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 123                                                         MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 124                                                         MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 125                                                         MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 126                                                         MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 127                                                 >;
 128                                         };
 129
 130                                         pinctrl_enet_3: enetgrp-3 {
 131                                                 fsl,pins = <
 132                                                         MX6DL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 133                                                         MX6DL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 134                                                         MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
 135                                                         MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
 136                                                         MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
 137                                                         MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
 138                                                         MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
 139                                                         MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
 140                                                         MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
 141                                                         MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
 142                                                         MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
 143                                                         MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
 144                                                         MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
 145                                                         MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
 146                                                         MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 147                                                         MX6DL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
 148                                                 >;
 149                                         };
 150                                 };
 151
 152                                 gpmi-nand {
 153                                         pinctrl_gpmi_nand_1: gpmi-nand-1 {
 154                                                 fsl,pins = <
 155                                                         MX6DL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 156                                                         MX6DL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 157                                                         MX6DL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 158                                                         MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 159                                                         MX6DL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 160                                                         MX6DL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
 161                                                         MX6DL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 162                                                         MX6DL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 163                                                         MX6DL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 164                                                         MX6DL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 165                                                         MX6DL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 166                                                         MX6DL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 167                                                         MX6DL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 168                                                         MX6DL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 169                                                         MX6DL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 170                                                         MX6DL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 171                                                         MX6DL_PAD_SD4_DAT0__NAND_DQS      0x00b1
 172                                                 >;
 173                                         };
 174                                 };
 175
 176                                 i2c1 {
 177                                         pinctrl_i2c1_1: i2c1grp-1 {
 178                                                 fsl,pins = <
 179                                                         MX6DL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
 180                                                         MX6DL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
 181                                                 >;
 182                                         };
 183
 184                                         pinctrl_i2c1_2: i2c1grp-2 {
 185                                                 fsl,pins = <
 186                                                         MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
 187                                                         MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
 188                                                 >;
 189                                         };
 190                                 };
 191
 192                                 i2c2 {
 193                                         pinctrl_i2c2_1: i2c2grp-1 {
 194                                                 fsl,pins = <
 195                                                         MX6DL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
 196                                                         MX6DL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
 197                                                 >;
 198                                         };
 199
 200                                         pinctrl_i2c2_2: i2c2grp-2 {
 201                                                 fsl,pins = <
 202                                                         MX6DL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
 203                                                         MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 204                                                 >;
 205                                         };
 206                                 };
 207
 208                                 i2c3 {
 209                                         pinctrl_i2c3_1: i2c3grp-1 {
 210                                                 fsl,pins = <
 211                                                         MX6DL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
 212                                                         MX6DL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 213                                                 >;
 214                                         };
 215                                 };
 216
 217                                 uart1 {
 218                                         pinctrl_uart1_1: uart1grp-1 {
 219                                                 fsl,pins = <
 220                                                         MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 221                                                         MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 222                                                 >;
 223                                         };
 224                                 };
 225
 226                                 uart2 {
 227                                         pinctrl_uart2_1: uart2grp-1 {
 228                                                 fsl,pins = <
 229                                                         MX6DL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
 230                                                         MX6DL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
 231                                                 >;
 232                                         };
 233
 234                                         pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
 235                                                 fsl,pins = <
 236                                                         MX6DL_PAD_EIM_D26__UART2_RX_DATA   0x1b0b1
 237                                                         MX6DL_PAD_EIM_D27__UART2_TX_DATA   0x1b0b1
 238                                                         MX6DL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
 239                                                         MX6DL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
 240                                                 >;
 241                                         };
 242                                 };
 243
 244                                 uart4 {
 245                                         pinctrl_uart4_1: uart4grp-1 {
 246                                                 fsl,pins = <
 247                                                         MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 248                                                         MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 249                                                 >;
 250                                         };
 251                                 };
 252
 253                                 usbotg {
 254                                         pinctrl_usbotg_1: usbotggrp-1 {
 255                                                 fsl,pins = <
 256                                                         MX6DL_PAD_GPIO_1__USB_OTG_ID 0x17059
 257                                                 >;
 258                                         };
 259
 260                                         pinctrl_usbotg_2: usbotggrp-2 {
 261                                                 fsl,pins = <
 262                                                         MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 263                                                 >;
 264                                         };
 265                                 };
 266
 267                                 usdhc2 {
 268                                         pinctrl_usdhc2_1: usdhc2grp-1 {
 269                                                 fsl,pins = <
 270                                                         MX6DL_PAD_SD2_CMD__SD2_CMD    0x17059
 271                                                         MX6DL_PAD_SD2_CLK__SD2_CLK    0x10059
 272                                                         MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
 273                                                         MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
 274                                                         MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
 275                                                         MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
 276                                                         MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
 277                                                         MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
 278                                                         MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
 279                                                         MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
 280                                                 >;
 281                                         };
 282
 283                                         pinctrl_usdhc2_2: usdhc2grp-2 {
 284                                                 fsl,pins = <
 285                                                         MX6DL_PAD_SD2_CMD__SD2_CMD    0x17059
 286                                                         MX6DL_PAD_SD2_CLK__SD2_CLK    0x10059
 287                                                         MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
 288                                                         MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
 289                                                         MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
 290                                                         MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
 291                                                 >;
 292                                         };
 293                                 };
 294
 295                                 usdhc3 {
 296                                         pinctrl_usdhc3_1: usdhc3grp-1 {
 297                                                 fsl,pins = <
 298                                                         MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
 299                                                         MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
 300                                                         MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 301                                                         MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 302                                                         MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 303                                                         MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 304                                                         MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
 305                                                         MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
 306                                                         MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
 307                                                         MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
 308                                                 >;
 309                                         };
 310
 311                                         pinctrl_usdhc3_2: usdhc3grp-2 {
 312                                                 fsl,pins = <
 313                                                         MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
 314                                                         MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
 315                                                         MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 316                                                         MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 317                                                         MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 318                                                         MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 319                                                 >;
 320                                         };
 321                                 };
 322
 323                                 usdhc4 {
 324                                         pinctrl_usdhc4_1: usdhc4grp-1 {
 325                                                 fsl,pins = <
 326                                                         MX6DL_PAD_SD4_CMD__SD4_CMD    0x17059
 327                                                         MX6DL_PAD_SD4_CLK__SD4_CLK    0x10059
 328                                                         MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x17059
 329                                                         MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x17059
 330                                                         MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x17059
 331                                                         MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x17059
 332                                                         MX6DL_PAD_SD4_DAT4__SD4_DATA4 0x17059
 333                                                         MX6DL_PAD_SD4_DAT5__SD4_DATA5 0x17059
 334                                                         MX6DL_PAD_SD4_DAT6__SD4_DATA6 0x17059
 335                                                         MX6DL_PAD_SD4_DAT7__SD4_DATA7 0x17059
 336                                                 >;
 337                                         };
 338
 339                                         pinctrl_usdhc4_2: usdhc4grp-2 {
 340                                                 fsl,pins = <
 341                                                         MX6DL_PAD_SD4_CMD__SD4_CMD    0x17059
 342                                                         MX6DL_PAD_SD4_CLK__SD4_CLK    0x10059
 343                                                         MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x17059
 344                                                         MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x17059
 345                                                         MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x17059
 346                                                         MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x17059
 347                                                 >;
 348                                         };
 349                                 };
 350
 351                                 weim {
 352                                         pinctrl_weim_cs0_1: weim_cs0grp-1 {
 353                                                 fsl,pins = <
 354                                                         MX6DL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
 355                                                 >;
 356                                         };
 357
 358                                         pinctrl_weim_nor_1: weim_norgrp-1 {
 359                                                 fsl,pins = <
 360                                                         MX6DL_PAD_EIM_OE__EIM_OE_B     0xb0b1
 361                                                         MX6DL_PAD_EIM_RW__EIM_RW       0xb0b1
 362                                                         MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
 363                                                         /* data */
 364                                                         MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
 365                                                         MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
 366                                                         MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
 367                                                         MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
 368                                                         MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
 369                                                         MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
 370                                                         MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
 371                                                         MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
 372                                                         MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
 373                                                         MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
 374                                                         MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
 375                                                         MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
 376                                                         MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
 377                                                         MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
 378                                                         MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
 379                                                         MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
 380                                                         /* address */
 381                                                         MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
 382                                                         MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
 383                                                         MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
 384                                                         MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
 385                                                         MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
 386                                                         MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
 387                                                         MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
 388                                                         MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
 389                                                         MX6DL_PAD_EIM_DA15__EIM_AD15  0xb0b1
 390                                                         MX6DL_PAD_EIM_DA14__EIM_AD14  0xb0b1
 391                                                         MX6DL_PAD_EIM_DA13__EIM_AD13  0xb0b1
 392                                                         MX6DL_PAD_EIM_DA12__EIM_AD12  0xb0b1
 393                                                         MX6DL_PAD_EIM_DA11__EIM_AD11  0xb0b1
 394                                                         MX6DL_PAD_EIM_DA10__EIM_AD10  0xb0b1
 395                                                         MX6DL_PAD_EIM_DA9__EIM_AD09   0xb0b1
 396                                                         MX6DL_PAD_EIM_DA8__EIM_AD08   0xb0b1
 397                                                         MX6DL_PAD_EIM_DA7__EIM_AD07   0xb0b1
 398                                                         MX6DL_PAD_EIM_DA6__EIM_AD06   0xb0b1
 399                                                         MX6DL_PAD_EIM_DA5__EIM_AD05   0xb0b1
 400                                                         MX6DL_PAD_EIM_DA4__EIM_AD04   0xb0b1
 401                                                         MX6DL_PAD_EIM_DA3__EIM_AD03   0xb0b1
 402                                                         MX6DL_PAD_EIM_DA2__EIM_AD02   0xb0b1
 403                                                         MX6DL_PAD_EIM_DA1__EIM_AD01   0xb0b1
 404                                                         MX6DL_PAD_EIM_DA0__EIM_AD00   0xb0b1
 405                                                 >;
 406                                         };
 407                                 };
 408                         };
 409
 410                         pxp: pxp@020f0000 {
 411                                 reg = <0x020f0000 0x4000>;
 412                                 interrupts = <0 98 0x04>;
 413                         };
 414
 415                         epdc: epdc@020f4000 {
 416                                 reg = <0x020f4000 0x4000>;
 417                                 interrupts = <0 97 0x04>;
 418                         };
 419
 420                         lcdif: lcdif@020f8000 {
 421                                 reg = <0x020f8000 0x4000>;
 422                                 interrupts = <0 39 0x04>;
 423                         };
 424                 };
 425
 426                 aips2: aips-bus@02100000 {
 427                         i2c4: i2c@021f8000 {
 428                                 #address-cells = <1>;
 429                                 #size-cells = <0>;
 430                                 compatible = "fsl,imx1-i2c";
 431                                 reg = <0x021f8000 0x4000>;
 432                                 interrupts = <0 35 0x04>;
 433                                 status = "disabled";
 434                         };
 435                 };
 436         };
 437 };
 438
 439 &ldb {
 440         clocks = <&clks 33>, <&clks 34>,
 441                  <&clks 39>, <&clks 40>,
 442                  <&clks 135>, <&clks 136>;
 443         clock-names = "di0_pll", "di1_pll",
 444                       "di0_sel", "di1_sel",
 445                       "di0", "di1";
 446
 447         lvds-channel@0 {
 448                 crtcs = <&ipu1 0>, <&ipu1 1>;
 449         };
 450
 451         lvds-channel@1 {
 452                 crtcs = <&ipu1 0>, <&ipu1 1>;
 453         };
 454 };