arch/arm/boot/dts/imx6dl.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include "imx6dl-pinfunc.h"
  13 #include "imx6qdl.dtsi"
  14
  15 / {
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         compatible = "arm,cortex-a9";
  22                         device_type = "cpu";
  23                         reg = <0>;
  24                         next-level-cache = <&L2>;
  25                         operating-points = <
  26                                 /* kHz    uV */
  27                                 996000  1275000
  28                                 792000  1175000
  29                                 396000  1075000
  30                         >;
  31                         fsl,soc-operating-points = <
  32                                 /* ARM kHz  SOC-PU uV */
  33                                 996000  1175000
  34                                 792000  1175000
  35                                 396000  1175000
  36                         >;
  37                         clock-latency = <61036>; /* two CLK32 periods */
  38                         clocks = <&clks 104>, <&clks 6>, <&clks 16>,
  39                                  <&clks 17>, <&clks 170>;
  40                         clock-names = "arm", "pll2_pfd2_396m", "step",
  41                                       "pll1_sw", "pll1_sys";
  42                         arm-supply = <&reg_arm>;
  43                         pu-supply = <&reg_pu>;
  44                         soc-supply = <&reg_soc>;
  45                 };
  46
  47                 cpu@1 {
  48                         compatible = "arm,cortex-a9";
  49                         device_type = "cpu";
  50                         reg = <1>;
  51                         next-level-cache = <&L2>;
  52                 };
  53         };
  54
  55         soc {
  56                 gpu@00130000 {
  57                         compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
  58                         reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
  59                               <0x0 0x0>;
  60                         reg-names = "iobase_3d", "iobase_2d",
  61                                     "phys_baseaddr";
  62                         interrupts = <0 9 0x04>, <0 10 0x04>;
  63                         interrupt-names = "irq_3d", "irq_2d";
  64                         clocks = <&clks 143>, <&clks 27>,
  65                                  <&clks 121>, <&clks 122>,
  66                                  <&clks 0>;
  67                         clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
  68                                       "gpu2d_clk", "gpu3d_clk",
  69                                       "gpu3d_shader_clk";
  70                         resets = <&src 0>, <&src 3>;
  71                         reset-names = "gpu3d", "gpu2d";
  72                 };
  73
  74                 ocram: sram@00900000 {
  75                         compatible = "mmio-sram";
  76                         reg = <0x00900000 0x20000>;
  77                         clocks = <&clks 142>;
  78                 };
  79
  80                 aips1: aips-bus@02000000 {
  81                         vpu@02040000 {
  82                                 iramsize = <0>;
  83                                 status = "okay";
  84                         };
  85
  86                         iomuxc: iomuxc@020e0000 {
  87                                 compatible = "fsl,imx6dl-iomuxc";
  88                         };
  89
  90                         pxp: pxp@020f0000 {
  91                                 reg = <0x020f0000 0x4000>;
  92                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
  93                         };
  94
  95                         epdc: epdc@020f4000 {
  96                                 reg = <0x020f4000 0x4000>;
  97                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
  98                         };
  99
 100                         lcdif: lcdif@020f8000 {
 101                                 reg = <0x020f8000 0x4000>;
 102                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 103                         };
 104                 };
 105
 106                 aips2: aips-bus@02100000 {
 107                         i2c4: i2c@021f8000 {
 108                                 #address-cells = <1>;
 109                                 #size-cells = <0>;
 110                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 111                                 reg = <0x021f8000 0x4000>;
 112                                 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 113                                 clocks = <&clks 116>;
 114                                 status = "disabled";
 115                         };
 116                 };
 117         };
 118
 119         display-subsystem {
 120                 compatible = "fsl,imx-display-subsystem";
 121                 ports = <&ipu1_di0>, <&ipu1_di1>;
 122         };
 123 };
 124
 125 &hdmi {
 126         compatible = "fsl,imx6dl-hdmi";
 127 };
 128
 129 &ldb {
 130         clocks = <&clks 33>, <&clks 34>,
 131                  <&clks 39>, <&clks 40>,
 132                  <&clks 135>, <&clks 136>;
 133         clock-names = "di0_pll", "di1_pll",
 134                       "di0_sel", "di1_sel",
 135                       "di0", "di1";
 136 };