3 * Copyright 2013 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include "imx6q-pinfunc.h"
13 #include "imx6qdl.dtsi"
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
37 fsl,soc-operating-points = <
38 /* ARM kHz SOC-PU uV */
45 clock-latency = <61036>; /* two CLK32 periods */
46 clocks = <&clks IMX6QDL_CLK_ARM>,
47 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
48 <&clks IMX6QDL_CLK_STEP>,
49 <&clks IMX6QDL_CLK_PLL1_SW>,
50 <&clks IMX6QDL_CLK_PLL1_SYS>;
51 clock-names = "arm", "pll2_pfd2_396m", "step",
52 "pll1_sw", "pll1_sys";
53 arm-supply = <®_arm>;
54 pu-supply = <®_pu>;
55 soc-supply = <®_soc>;
59 compatible = "arm,cortex-a9";
62 next-level-cache = <&L2>;
66 compatible = "arm,cortex-a9";
69 next-level-cache = <&L2>;
73 compatible = "arm,cortex-a9";
76 next-level-cache = <&L2>;
81 ocram: sram@00900000 {
82 compatible = "mmio-sram";
83 reg = <0x00900000 0x40000>;
84 clocks = <&clks IMX6QDL_CLK_OCRAM>;
87 aips-bus@02000000 { /* AIPS1 */
89 ecspi5: ecspi@02018000 {
92 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
93 reg = <0x02018000 0x4000>;
94 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&clks IMX6Q_CLK_ECSPI5>,
96 <&clks IMX6Q_CLK_ECSPI5>;
97 clock-names = "ipg", "per";
102 iomuxc: iomuxc@020e0000 {
103 compatible = "fsl,imx6q-iomuxc";
106 pinctrl_ipu2_1: ipu2grp-1 {
108 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
109 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
110 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
111 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
112 MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
113 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
114 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
115 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
116 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
117 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
118 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
119 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
120 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
121 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
122 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
123 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
124 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
125 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
126 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
127 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
128 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
129 MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
130 MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
131 MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
132 MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
133 MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
134 MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
135 MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
136 MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
143 sata: sata@02200000 {
144 compatible = "fsl,imx6q-ahci";
145 reg = <0x02200000 0x4000>;
146 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clks IMX6QDL_CLK_SATA>,
148 <&clks IMX6QDL_CLK_SATA_REF_100M>,
149 <&clks IMX6QDL_CLK_AHB>;
150 clock-names = "sata", "sata_ref", "ahb";
155 compatible = "fsl,imx6q-ipu";
156 reg = <0x02800000 0x400000>;
157 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
158 <0 7 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&clks IMX6QDL_CLK_IPU2>,
160 <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>,
161 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
162 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
165 "di0_sel", "di1_sel",
166 "ldb_di0", "ldb_di1";
174 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
176 clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,
177 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
178 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
179 <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
180 <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,
181 <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;
182 clock-names = "ldb_di0", "ldb_di1",
183 "di0_sel", "di1_sel",
184 "di2_sel", "di3_sel",
185 "ldb_di0_div_3_5", "ldb_di1_div_3_5",
186 "ldb_di0_div_7", "ldb_di1_div_7",
187 "ldb_di0_div_sel", "ldb_di1_div_sel";