arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/gpio/gpio.h>
  14
  15 / {
  16         aliases {
  17                 mxcfb0 = &mxcfb1;
  18                 mxcfb1 = &mxcfb2;
  19                 mxcfb2 = &mxcfb3;
  20                 mxcfb3 = &mxcfb4;
  21         };
  22
  23         memory {
  24                 reg = <0x10000000 0x80000000>;
  25         };
  26
  27         leds {
  28                 compatible = "gpio-leds";
  29                 pinctrl-names = "default";
  30                 pinctrl-0 = <&pinctrl_gpio_leds>;
  31
  32                 user {
  33                         label = "debug";
  34                         gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
  35                 };
  36         };
  37
  38         sound-spdif {
  39                 compatible = "fsl,imx-audio-spdif",
  40                            "fsl,imx-sabreauto-spdif";
  41                 model = "imx-spdif";
  42                 spdif-controller = <&spdif>;
  43                 spdif-in;
  44         };
  45
  46         backlight {
  47                 compatible = "pwm-backlight";
  48                 pwms = <&pwm3 0 5000000>;
  49                 brightness-levels = <0 4 8 16 32 64 128 255>;
  50                 default-brightness-level = <7>;
  51                 status = "okay";
  52         };
  53 };
  54
  55 &ecspi1 {
  56         fsl,spi-num-chipselects = <1>;
  57         cs-gpios = <&gpio3 19 0>;
  58         pinctrl-names = "default";
  59         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
  60         status = "disabled"; /* pin conflict with WEIM NOR */
  61
  62         flash: m25p80@0 {
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 compatible = "st,m25p32";
  66                 spi-max-frequency = <20000000>;
  67                 reg = <0>;
  68         };
  69
  70         mxcfb1: fb@0 {
  71                 compatible = "fsl,mxc_sdc_fb";
  72                 disp_dev = "ldb";
  73                 interface_pix_fmt = "RGB666";
  74                 mode_str ="LDB-XGA";
  75                 default_bpp = <16>;
  76                 int_clk = <0>;
  77                 late_init = <0>;
  78                 status = "disabled";
  79         };
  80
  81         mxcfb2: fb@1 {
  82                 compatible = "fsl,mxc_sdc_fb";
  83                 disp_dev = "ldb";
  84                 interface_pix_fmt = "RGB666";
  85                 mode_str ="LDB-XGA";
  86                 default_bpp = <16>;
  87                 int_clk = <0>;
  88                 late_init = <0>;
  89                 status = "disabled";
  90         };
  91
  92         mxcfb3: fb@2 {
  93                 compatible = "fsl,mxc_sdc_fb";
  94                 disp_dev = "lcd";
  95                 interface_pix_fmt = "RGB565";
  96                 mode_str ="CLAA-WVGA";
  97                 default_bpp = <16>;
  98                 int_clk = <0>;
  99                 late_init = <0>;
 100                 status = "disabled";
 101         };
 102
 103         mxcfb4: fb@3 {
 104                 compatible = "fsl,mxc_sdc_fb";
 105                 disp_dev = "ldb";
 106                 interface_pix_fmt = "RGB666";
 107                 mode_str ="LDB-XGA";
 108                 default_bpp = <16>;
 109                 int_clk = <0>;
 110                 late_init = <0>;
 111                 status = "disabled";
 112         };
 113
 114         lcd@0 {
 115                 compatible = "fsl,lcd";
 116                 ipu_id = <0>;
 117                 disp_id = <0>;
 118                 default_ifmt = "RGB565";
 119                 pinctrl-names = "default";
 120                 pinctrl-0 = <&pinctrl_ipu1_1>;
 121                 status = "okay";
 122         };
 123
 124         backlight {
 125                 compatible = "pwm-backlight";
 126                 pwms = <&pwm3 0 5000000>;
 127                 brightness-levels = <0 4 8 16 32 64 128 255>;
 128                 default-brightness-level = <7>;
 129         };
 130
 131 };
 132
 133 &ecspi1 {
 134         fsl,spi-num-chipselects = <1>;
 135         cs-gpios = <&gpio3 19 0>;
 136         pinctrl-names = "default";
 137         pinctrl-0 = <&pinctrl_ecspi1_1>;
 138         status = "disabled"; /* pin conflict with WEIM NOR */
 139
 140         flash: m25p80@0 {
 141                 #address-cells = <1>;
 142                 #size-cells = <1>;
 143                 compatible = "st,m25p32";
 144                 spi-max-frequency = <20000000>;
 145                 reg = <0>;
 146         };
 147 };
 148
 149 &fec {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_enet>;
 152         phy-mode = "rgmii";
 153         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
 154                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 155         status = "okay";
 156 };
 157
 158 &gpmi {
 159         pinctrl-names = "default";
 160         pinctrl-0 = <&pinctrl_gpmi_nand>;
 161         status = "okay";
 162 };
 163
 164 &i2c2 {
 165         clock-frequency = <100000>;
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&pinctrl_i2c2>;
 168         status = "okay";
 169
 170         pmic: pfuze100@08 {
 171                 compatible = "fsl,pfuze100";
 172                 reg = <0x08>;
 173
 174                 regulators {
 175                         sw1a_reg: sw1ab {
 176                                 regulator-min-microvolt = <300000>;
 177                                 regulator-max-microvolt = <1875000>;
 178                                 regulator-boot-on;
 179                                 regulator-always-on;
 180                                 regulator-ramp-delay = <6250>;
 181                         };
 182
 183                         sw1c_reg: sw1c {
 184                                 regulator-min-microvolt = <300000>;
 185                                 regulator-max-microvolt = <1875000>;
 186                                 regulator-boot-on;
 187                                 regulator-always-on;
 188                                 regulator-ramp-delay = <6250>;
 189                         };
 190
 191                         sw2_reg: sw2 {
 192                                 regulator-min-microvolt = <800000>;
 193                                 regulator-max-microvolt = <3300000>;
 194                                 regulator-boot-on;
 195                                 regulator-always-on;
 196                         };
 197
 198                         sw3a_reg: sw3a {
 199                                 regulator-min-microvolt = <400000>;
 200                                 regulator-max-microvolt = <1975000>;
 201                                 regulator-boot-on;
 202                                 regulator-always-on;
 203                         };
 204
 205                         sw3b_reg: sw3b {
 206                                 regulator-min-microvolt = <400000>;
 207                                 regulator-max-microvolt = <1975000>;
 208                                 regulator-boot-on;
 209                                 regulator-always-on;
 210                         };
 211
 212                         sw4_reg: sw4 {
 213                                 regulator-min-microvolt = <800000>;
 214                                 regulator-max-microvolt = <3300000>;
 215                         };
 216
 217                         swbst_reg: swbst {
 218                                 regulator-min-microvolt = <5000000>;
 219                                 regulator-max-microvolt = <5150000>;
 220                         };
 221
 222                         snvs_reg: vsnvs {
 223                                 regulator-min-microvolt = <1000000>;
 224                                 regulator-max-microvolt = <3000000>;
 225                                 regulator-boot-on;
 226                                 regulator-always-on;
 227                         };
 228
 229                         vref_reg: vrefddr {
 230                                 regulator-boot-on;
 231                                 regulator-always-on;
 232                         };
 233
 234                         vgen1_reg: vgen1 {
 235                                 regulator-min-microvolt = <800000>;
 236                                 regulator-max-microvolt = <1550000>;
 237                         };
 238
 239                         vgen2_reg: vgen2 {
 240                                 regulator-min-microvolt = <800000>;
 241                                 regulator-max-microvolt = <1550000>;
 242                         };
 243
 244                         vgen3_reg: vgen3 {
 245                                 regulator-min-microvolt = <1800000>;
 246                                 regulator-max-microvolt = <3300000>;
 247                         };
 248
 249                         vgen4_reg: vgen4 {
 250                                 regulator-min-microvolt = <1800000>;
 251                                 regulator-max-microvolt = <3300000>;
 252                                 regulator-always-on;
 253                         };
 254
 255                         vgen5_reg: vgen5 {
 256                                 regulator-min-microvolt = <1800000>;
 257                                 regulator-max-microvolt = <3300000>;
 258                                 regulator-always-on;
 259                         };
 260
 261                         vgen6_reg: vgen6 {
 262                                 regulator-min-microvolt = <1800000>;
 263                                 regulator-max-microvolt = <3300000>;
 264                                 regulator-always-on;
 265                         };
 266                 };
 267         };
 268 };
 269
 270 &iomuxc {
 271         pinctrl-names = "default";
 272         pinctrl-0 = <&pinctrl_hog>;
 273
 274         imx6qdl-sabreauto {
 275                 pinctrl_hog: hoggrp {
 276                         fsl,pins = <
 277                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 278                                 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
 279                                 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
 280                         >;
 281                 };
 282
 283                 pinctrl_ecspi1: ecspi1grp {
 284                         fsl,pins = <
 285                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 286                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 287                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 288                         >;
 289                 };
 290
 291                 pinctrl_ecspi1_cs: ecspi1cs {
 292                         fsl,pins = <
 293                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
 294                         >;
 295                 };
 296
 297                 pinctrl_enet: enetgrp {
 298                         fsl,pins = <
 299                                 MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
 300                                 MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
 301                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 302                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 303                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 304                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 305                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 306                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 307                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 308                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 309                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 310                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 311                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 312                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 313                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 314                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 315                         >;
 316                 };
 317
 318                 pinctrl_gpio_leds: gpioledsgrp {
 319                         fsl,pins = <
 320                                 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x80000000
 321                         >;
 322                 };
 323
 324                 pinctrl_gpmi_nand: gpminandgrp {
 325                         fsl,pins = <
 326                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 327                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 328                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 329                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 330                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 331                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 332                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 333                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 334                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 335                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 336                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 337                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 338                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 339                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 340                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 341                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 342                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 343                         >;
 344                 };
 345
 346                 pinctrl_i2c2: i2c2grp {
 347                         fsl,pins = <
 348                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL    0x4001b8b1
 349                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
 350                         >;
 351                 };
 352
 353                 pinctrl_pwm3: pwm1grp {
 354                         fsl,pins = <
 355                                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 356                         >;
 357                 };
 358
 359                 pinctrl_spdif: spdifgrp {
 360                         fsl,pins = <
 361                                 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
 362                         >;
 363                 };
 364
 365                 pinctrl_uart4: uart4grp {
 366                         fsl,pins = <
 367                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 368                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 369                         >;
 370                 };
 371
 372                 pinctrl_usdhc3: usdhc3grp {
 373                         fsl,pins = <
 374                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 375                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 376                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 377                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 378                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 379                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 380                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 381                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 382                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 383                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 384                         >;
 385                 };
 386
 387                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 388                         fsl,pins = <
 389                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 390                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 391                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 392                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 393                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 394                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 395                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 396                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 397                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 398                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 399                         >;
 400                 };
 401
 402                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 403                         fsl,pins = <
 404                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 405                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 406                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 407                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 408                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 409                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 410                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 411                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 412                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 413                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 414                         >;
 415                 };
 416
 417                 pinctrl_weim_cs0: weimcs0grp {
 418                         fsl,pins = <
 419                                 MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
 420                         >;
 421                 };
 422
 423                 pinctrl_weim_nor: weimnorgrp {
 424                         fsl,pins = <
 425                                 MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 426                                 MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 427                                 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B         0xb060
 428                                 MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
 429                                 MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
 430                                 MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
 431                                 MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
 432                                 MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
 433                                 MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
 434                                 MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
 435                                 MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
 436                                 MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
 437                                 MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
 438                                 MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
 439                                 MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
 440                                 MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
 441                                 MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
 442                                 MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
 443                                 MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
 444                                 MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
 445                                 MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
 446                                 MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
 447                                 MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
 448                                 MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
 449                                 MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
 450                                 MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
 451                                 MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
 452                                 MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 453                                 MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 454                                 MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 455                                 MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 456                                 MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 457                                 MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 458                                 MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 459                                 MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 460                                 MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 461                                 MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 462                                 MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 463                                 MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 464                                 MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 465                                 MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 466                                 MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 467                                 MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 468                         >;
 469                 };
 470         };
 471 };
 472
 473 &ldb {
 474         status = "okay";
 475
 476         lvds-channel@0 {
 477                 fsl,data-mapping = "spwg";
 478                 fsl,data-width = <18>;
 479                 status = "okay";
 480
 481                 display-timings {
 482                         native-mode = <&timing0>;
 483                         timing0: hsd100pxn1 {
 484                                 clock-frequency = <65000000>;
 485                                 hactive = <1024>;
 486                                 vactive = <768>;
 487                                 hback-porch = <220>;
 488                                 hfront-porch = <40>;
 489                                 vback-porch = <21>;
 490                                 vfront-porch = <7>;
 491                                 hsync-len = <60>;
 492                                 vsync-len = <10>;
 493                         };
 494                 };
 495         };
 496 };
 497
 498 &pwm3 {
 499         pinctrl-names = "default";
 500         pinctrl-0 = <&pinctrl_pwm3>;
 501         status = "okay";
 502 };
 503
 504 &spdif {
 505         pinctrl-names = "default";
 506         pinctrl-0 = <&pinctrl_spdif>;
 507         status = "okay";
 508 };
 509
 510 &gpmi {
 511         pinctrl-names = "default";
 512         pinctrl-0 = <&pinctrl_gpmi_nand_1>;
 513         status = "okay";
 514 };
 515
 516 &uart4 {
 517         pinctrl-names = "default";
 518         pinctrl-0 = <&pinctrl_uart4>;
 519         status = "okay";
 520 };
 521
 522 &usdhc3 {
 523         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 524         pinctrl-0 = <&pinctrl_usdhc3>;
 525         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 526         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 527         cd-gpios = <&gpio6 15 0>;
 528         wp-gpios = <&gpio1 13 0>;
 529         status = "okay";
 530 };
 531
 532 &weim {
 533         pinctrl-names = "default";
 534         pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
 535         #address-cells = <2>;
 536         #size-cells = <1>;
 537         ranges = <0 0 0x08000000 0x08000000>;
 538         status = "disabled"; /* pin conflict with SPI NOR */
 539
 540         nor@0,0 {
 541                 compatible = "cfi-flash";
 542                 reg = <0 0 0x02000000>;
 543                 #address-cells = <1>;
 544                 #size-cells = <1>;
 545                 bank-width = <2>;
 546                 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
 547                                 0x0000c000 0x1404a38e 0x00000000>;
 548         };
 549 };
 550
 551 &ldb {
 552         ipu_id = <1>;
 553         disp_id = <1>;
 554         ext_ref = <1>;
 555         mode = "sep0";
 556         sec_ipu_id = <1>;
 557         sec_disp_id = <0>;
 558         status = "okay";
 559 };
 560
 561 &pwm3 {
 562         pinctrl-names = "default";
 563         pinctrl-0 = <&pinctrl_pwm3_1>;
 564         status = "okay";
 565 };