arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 / {
  14         memory {
  15                 reg = <0x10000000 0x80000000>;
  16         };
  17 };
  18
  19 &ecspi1 {
  20         fsl,spi-num-chipselects = <1>;
  21         cs-gpios = <&gpio3 19 0>;
  22         pinctrl-names = "default";
  23         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
  24         status = "disabled"; /* pin conflict with WEIM NOR */
  25
  26         flash: m25p80@0 {
  27                 #address-cells = <1>;
  28                 #size-cells = <1>;
  29                 compatible = "st,m25p32";
  30                 spi-max-frequency = <20000000>;
  31                 reg = <0>;
  32         };
  33 };
  34
  35 &fec {
  36         pinctrl-names = "default";
  37         pinctrl-0 = <&pinctrl_enet>;
  38         phy-mode = "rgmii";
  39         status = "okay";
  40 };
  41
  42 &gpmi {
  43         pinctrl-names = "default";
  44         pinctrl-0 = <&pinctrl_gpmi_nand>;
  45         status = "okay";
  46 };
  47
  48 &iomuxc {
  49         pinctrl-names = "default";
  50         pinctrl-0 = <&pinctrl_hog>;
  51
  52         imx6qdl-sabreauto {
  53                 pinctrl_hog: hoggrp {
  54                         fsl,pins = <
  55                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
  56                                 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
  57                                 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
  58                         >;
  59                 };
  60
  61                 pinctrl_ecspi1: ecspi1grp {
  62                         fsl,pins = <
  63                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
  64                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
  65                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
  66                         >;
  67                 };
  68
  69                 pinctrl_ecspi1_cs: ecspi1cs {
  70                         fsl,pins = <
  71                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
  72                         >;
  73                 };
  74
  75                 pinctrl_enet: enetgrp {
  76                         fsl,pins = <
  77                                 MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
  78                                 MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
  79                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
  80                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
  81                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
  82                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
  83                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
  84                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
  85                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
  86                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
  87                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
  88                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
  89                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
  90                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
  91                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
  92                         >;
  93                 };
  94
  95                 pinctrl_gpmi_nand: gpminandgrp {
  96                         fsl,pins = <
  97                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
  98                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
  99                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 100                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 101                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 102                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 103                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 104                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 105                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 106                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 107                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 108                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 109                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 110                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 111                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 112                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 113                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 114                         >;
 115                 };
 116
 117                 pinctrl_uart4: uart4grp {
 118                         fsl,pins = <
 119                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 120                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 121                         >;
 122                 };
 123
 124                 pinctrl_usdhc3: usdhc3grp {
 125                         fsl,pins = <
 126                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 127                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 128                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 129                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 130                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 131                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 132                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 133                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 134                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 135                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 136                         >;
 137                 };
 138
 139                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 140                         fsl,pins = <
 141                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 142                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 143                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 144                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 145                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 146                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 147                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 148                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 149                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 150                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 151                         >;
 152                 };
 153
 154                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 155                         fsl,pins = <
 156                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 157                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 158                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 159                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 160                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 161                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 162                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 163                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 164                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 165                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 166                         >;
 167                 };
 168
 169                 pinctrl_weim_cs0: weimcs0grp {
 170                         fsl,pins = <
 171                                 MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
 172                         >;
 173                 };
 174
 175                 pinctrl_weim_nor: weimnorgrp {
 176                         fsl,pins = <
 177                                 MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 178                                 MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 179                                 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B         0xb060
 180                                 MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
 181                                 MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
 182                                 MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
 183                                 MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
 184                                 MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
 185                                 MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
 186                                 MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
 187                                 MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
 188                                 MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
 189                                 MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
 190                                 MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
 191                                 MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
 192                                 MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
 193                                 MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
 194                                 MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
 195                                 MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
 196                                 MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
 197                                 MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
 198                                 MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
 199                                 MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
 200                                 MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
 201                                 MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
 202                                 MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
 203                                 MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
 204                                 MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 205                                 MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 206                                 MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 207                                 MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 208                                 MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 209                                 MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 210                                 MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 211                                 MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 212                                 MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 213                                 MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 214                                 MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 215                                 MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 216                                 MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 217                                 MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 218                                 MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 219                                 MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 220                         >;
 221                 };
 222         };
 223 };
 224
 225 &uart4 {
 226         pinctrl-names = "default";
 227         pinctrl-0 = <&pinctrl_uart4>;
 228         status = "okay";
 229 };
 230
 231 &usdhc3 {
 232         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 233         pinctrl-0 = <&pinctrl_usdhc3>;
 234         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 235         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 236         cd-gpios = <&gpio6 15 0>;
 237         wp-gpios = <&gpio1 13 0>;
 238         status = "okay";
 239 };
 240
 241 &weim {
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
 244         #address-cells = <2>;
 245         #size-cells = <1>;
 246         ranges = <0 0 0x08000000 0x08000000>;
 247         status = "disabled"; /* pin conflict with SPI NOR */
 248
 249         nor@0,0 {
 250                 compatible = "cfi-flash";
 251                 reg = <0 0 0x02000000>;
 252                 #address-cells = <1>;
 253                 #size-cells = <1>;
 254                 bank-width = <2>;
 255                 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
 256                                 0x0000c000 0x1404a38e 0x00000000>;
 257         };
 258 };