2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <dt-bindings/gpio/gpio.h>
24 reg = <0x10000000 0x80000000>;
28 compatible = "gpio-leds";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_gpio_leds>;
34 gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
39 compatible = "fsl,imx-audio-spdif",
40 "fsl,imx-sabreauto-spdif";
42 spdif-controller = <&spdif>;
47 compatible = "pwm-backlight";
48 pwms = <&pwm3 0 5000000>;
49 brightness-levels = <0 4 8 16 32 64 128 255>;
50 default-brightness-level = <7>;
55 compatible = "fsl,mxc_sdc_fb";
57 interface_pix_fmt = "RGB666";
66 compatible = "fsl,mxc_sdc_fb";
68 interface_pix_fmt = "RGB666";
77 compatible = "fsl,mxc_sdc_fb";
79 interface_pix_fmt = "RGB565";
80 mode_str ="CLAA-WVGA";
88 compatible = "fsl,mxc_sdc_fb";
90 interface_pix_fmt = "RGB666";
99 compatible = "fsl,lcd";
102 default_ifmt = "RGB565";
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_ipu1_1>;
109 compatible = "fsl,imx6q-v4l2-capture";
117 compatible = "fsl,imx6q-v4l2-capture";
125 compatible = "fsl,mxc_v4l2_output";
131 fsl,spi-num-chipselects = <1>;
132 cs-gpios = <&gpio3 19 0>;
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_ecspi1_1>;
135 status = "disabled"; /* pin conflict with WEIM NOR */
138 #address-cells = <1>;
140 compatible = "st,m25p32";
141 spi-max-frequency = <20000000>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_enet>;
150 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
151 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_gpmi_nand>;
162 clock-frequency = <100000>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_i2c2>;
168 compatible = "fsl,pfuze100";
173 regulator-min-microvolt = <300000>;
174 regulator-max-microvolt = <1875000>;
177 regulator-ramp-delay = <6250>;
181 regulator-min-microvolt = <300000>;
182 regulator-max-microvolt = <1875000>;
185 regulator-ramp-delay = <6250>;
189 regulator-min-microvolt = <800000>;
190 regulator-max-microvolt = <3300000>;
196 regulator-min-microvolt = <400000>;
197 regulator-max-microvolt = <1975000>;
203 regulator-min-microvolt = <400000>;
204 regulator-max-microvolt = <1975000>;
210 regulator-min-microvolt = <800000>;
211 regulator-max-microvolt = <3300000>;
215 regulator-min-microvolt = <5000000>;
216 regulator-max-microvolt = <5150000>;
220 regulator-min-microvolt = <1000000>;
221 regulator-max-microvolt = <3000000>;
232 regulator-min-microvolt = <800000>;
233 regulator-max-microvolt = <1550000>;
237 regulator-min-microvolt = <800000>;
238 regulator-max-microvolt = <1550000>;
242 regulator-min-microvolt = <1800000>;
243 regulator-max-microvolt = <3300000>;
247 regulator-min-microvolt = <1800000>;
248 regulator-max-microvolt = <3300000>;
253 regulator-min-microvolt = <1800000>;
254 regulator-max-microvolt = <3300000>;
259 regulator-min-microvolt = <1800000>;
260 regulator-max-microvolt = <3300000>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_hog>;
272 pinctrl_hog: hoggrp {
274 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
275 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
276 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
280 pinctrl_ecspi1: ecspi1grp {
282 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
283 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
284 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
288 pinctrl_ecspi1_cs: ecspi1cs {
290 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
294 pinctrl_enet: enetgrp {
296 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
297 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
298 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
299 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
300 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
301 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
302 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
303 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
304 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
305 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
306 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
307 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
308 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
309 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
310 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
311 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
315 pinctrl_gpio_leds: gpioledsgrp {
317 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
321 pinctrl_gpmi_nand: gpminandgrp {
323 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
324 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
325 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
326 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
327 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
328 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
329 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
330 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
331 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
332 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
333 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
334 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
335 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
336 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
337 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
338 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
339 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
343 pinctrl_i2c2: i2c2grp {
345 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
346 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
350 pinctrl_pwm3: pwm1grp {
352 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
356 pinctrl_spdif: spdifgrp {
358 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
362 pinctrl_uart4: uart4grp {
364 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
365 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
369 pinctrl_usdhc3: usdhc3grp {
371 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
372 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
373 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
374 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
375 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
376 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
377 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
378 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
379 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
380 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
384 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
386 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
387 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
388 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
389 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
390 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
391 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
392 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
393 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
394 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
395 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
399 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
401 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
402 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
403 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
404 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
405 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
406 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
407 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
408 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
409 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
410 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
414 pinctrl_weim_cs0: weimcs0grp {
416 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
420 pinctrl_weim_nor: weimnorgrp {
422 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
423 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
424 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
425 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
426 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
427 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
428 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
429 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
430 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
431 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
432 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
433 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
434 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
435 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
436 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
437 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
438 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
439 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
440 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
441 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
442 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
443 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
444 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
445 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
446 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
447 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
448 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
449 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
450 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
451 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
452 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
453 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
454 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
455 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
456 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
457 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
458 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
459 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
460 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
461 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
462 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
463 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
464 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
474 fsl,data-mapping = "spwg";
475 fsl,data-width = <18>;
479 native-mode = <&timing0>;
480 timing0: hsd100pxn1 {
481 clock-frequency = <65000000>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_pwm3>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_spdif>;
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_gpmi_nand_1>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&pinctrl_uart4>;
520 pinctrl-names = "default", "state_100mhz", "state_200mhz";
521 pinctrl-0 = <&pinctrl_usdhc3>;
522 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
523 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
524 cd-gpios = <&gpio6 15 0>;
525 wp-gpios = <&gpio1 13 0>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
532 #address-cells = <2>;
534 ranges = <0 0 0x08000000 0x08000000>;
535 status = "disabled"; /* pin conflict with SPI NOR */
538 compatible = "cfi-flash";
539 reg = <0 0 0x02000000>;
540 #address-cells = <1>;
543 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
544 0x0000c000 0x1404a38e 0x00000000>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&pinctrl_pwm3_1>;