2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
22 reg = <0x10000000 0x40000000>;
26 compatible = "simple-bus";
30 reg_usb_otg_vbus: regulator@0 {
31 compatible = "regulator-fixed";
33 regulator-name = "usb_otg_vbus";
34 regulator-min-microvolt = <5000000>;
35 regulator-max-microvolt = <5000000>;
40 reg_usb_h1_vbus: regulator@1 {
41 compatible = "regulator-fixed";
43 regulator-name = "usb_h1_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
50 reg_audio: regulator@2 {
51 compatible = "regulator-fixed";
53 regulator-name = "wm8962-supply";
60 compatible = "gpio-keys";
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_gpio_keys>;
65 label = "Power Button";
66 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
68 linux,code = <KEY_POWER>;
73 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
75 linux,code = <KEY_VOLUMEUP>;
79 label = "Volume Down";
80 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
82 linux,code = <KEY_VOLUMEDOWN>;
87 compatible = "fsl,imx6q-sabresd-wm8962",
88 "fsl,imx-audio-wm8962";
89 model = "wm8962-audio";
90 ssi-controller = <&ssi2>;
91 audio-codec = <&codec>;
93 "Headphone Jack", "HPOUTL",
94 "Headphone Jack", "HPOUTR",
106 compatible = "pwm-backlight";
107 pwms = <&pwm1 0 5000000>;
108 brightness-levels = <0 4 8 16 32 64 128 255>;
109 default-brightness-level = <7>;
114 compatible = "gpio-leds";
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_gpio_leds>;
119 gpios = <&gpio1 2 0>;
120 default-state = "on";
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_audmux>;
132 fsl,spi-num-chipselects = <1>;
133 cs-gpios = <&gpio4 9 0>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_ecspi1>;
139 #address-cells = <1>;
141 compatible = "st,m25p32";
142 spi-max-frequency = <20000000>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_enet>;
151 phy-reset-gpios = <&gpio1 25 0>;
156 ddc-i2c-bus = <&i2c2>;
161 clock-frequency = <100000>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_i2c1>;
167 compatible = "wlf,wm8962";
169 clocks = <&clks 201>;
170 DCVDD-supply = <®_audio>;
171 DBVDD-supply = <®_audio>;
172 AVDD-supply = <®_audio>;
173 CPVDD-supply = <®_audio>;
174 MICVDD-supply = <®_audio>;
175 PLLVDD-supply = <®_audio>;
176 SPKVDD1-supply = <®_audio>;
177 SPKVDD2-supply = <®_audio>;
179 0x0000 /* 0:Default */
180 0x0000 /* 1:Default */
181 0x0013 /* 2:FN_DMICCLK */
182 0x0000 /* 3:Default */
183 0x8014 /* 4:FN_DMICCDAT */
184 0x0000 /* 5:Default */
190 clock-frequency = <100000>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_i2c2>;
196 compatible = "fsl,pfuze100";
201 regulator-min-microvolt = <300000>;
202 regulator-max-microvolt = <1875000>;
205 regulator-ramp-delay = <6250>;
209 regulator-min-microvolt = <300000>;
210 regulator-max-microvolt = <1875000>;
213 regulator-ramp-delay = <6250>;
217 regulator-min-microvolt = <800000>;
218 regulator-max-microvolt = <3300000>;
224 regulator-min-microvolt = <400000>;
225 regulator-max-microvolt = <1975000>;
231 regulator-min-microvolt = <400000>;
232 regulator-max-microvolt = <1975000>;
238 regulator-min-microvolt = <800000>;
239 regulator-max-microvolt = <3300000>;
243 regulator-min-microvolt = <5000000>;
244 regulator-max-microvolt = <5150000>;
248 regulator-min-microvolt = <1000000>;
249 regulator-max-microvolt = <3000000>;
260 regulator-min-microvolt = <800000>;
261 regulator-max-microvolt = <1550000>;
265 regulator-min-microvolt = <800000>;
266 regulator-max-microvolt = <1550000>;
270 regulator-min-microvolt = <1800000>;
271 regulator-max-microvolt = <3300000>;
275 regulator-min-microvolt = <1800000>;
276 regulator-max-microvolt = <3300000>;
281 regulator-min-microvolt = <1800000>;
282 regulator-max-microvolt = <3300000>;
287 regulator-min-microvolt = <1800000>;
288 regulator-max-microvolt = <3300000>;
296 clock-frequency = <100000>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_i2c3>;
302 compatible = "eeti,egalax_ts";
304 interrupt-parent = <&gpio6>;
306 wakeup-gpios = <&gpio6 7 0>;
311 clock-frequency = <100000>;
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_i2c1_2>;
317 compatible = "wlf,wm8962";
319 clocks = <&clks 169>;
320 DCVDD-supply = <®_audio>;
321 DBVDD-supply = <®_audio>;
322 AVDD-supply = <®_audio>;
323 CPVDD-supply = <®_audio>;
324 MICVDD-supply = <®_audio>;
325 PLLVDD-supply = <®_audio>;
326 SPKVDD1-supply = <®_audio>;
327 SPKVDD2-supply = <®_audio>;
329 0x0000 /* 0:Default */
330 0x0000 /* 1:Default */
331 0x0013 /* 2:FN_DMICCLK */
332 0x0000 /* 3:Default */
333 0x8014 /* 4:FN_DMICCDAT */
334 0x0000 /* 5:Default */
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_hog>;
344 pinctrl_hog: hoggrp {
346 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
347 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
348 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
349 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
350 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
351 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
352 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
353 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
354 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
358 pinctrl_audmux: audmuxgrp {
360 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
361 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
362 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
363 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
367 pinctrl_ecspi1: ecspi1grp {
369 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
370 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
371 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
375 pinctrl_enet: enetgrp {
377 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
378 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
379 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
380 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
381 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
382 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
383 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
384 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
385 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
386 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
387 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
388 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
389 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
390 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
391 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
392 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
396 pinctrl_gpio_keys: gpio_keysgrp {
398 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
399 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
400 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
404 pinctrl_i2c1: i2c1grp {
406 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
407 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
411 pinctrl_i2c2: i2c2grp {
413 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
414 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
418 pinctrl_i2c3: i2c3grp {
420 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
421 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
425 pinctrl_pcie: pciegrp {
427 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
431 pinctrl_pwm1: pwm1grp {
433 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
437 pinctrl_uart1: uart1grp {
439 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
440 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
444 pinctrl_usbotg: usbotggrp {
446 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
450 pinctrl_usdhc2: usdhc2grp {
452 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
453 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
454 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
455 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
456 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
457 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
458 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
459 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
460 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
461 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
465 pinctrl_usdhc3: usdhc3grp {
467 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
468 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
469 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
470 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
471 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
472 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
473 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
474 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
475 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
476 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
480 pinctrl_usdhc4: usdhc4grp {
482 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
483 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
484 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
485 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
486 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
487 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
488 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
489 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
490 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
491 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
497 pinctrl_gpio_leds: gpioledsgrp {
499 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
509 fsl,data-mapping = "spwg";
510 fsl,data-width = <18>;
514 native-mode = <&timing0>;
515 timing0: hsd100pxn1 {
516 clock-frequency = <65000000>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&pinctrl_pcie>;
533 reset-gpio = <&gpio7 12 0>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_pwm1>;
544 fsl,mode = "i2s-slave";
549 pinctrl-names = "default";
550 pinctrl-0 = <&pinctrl_uart1>;
555 vbus-supply = <®_usb_h1_vbus>;
560 vbus-supply = <®_usb_otg_vbus>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&pinctrl_usbotg>;
563 disable-over-current;
568 pinctrl-names = "default";
569 pinctrl-0 = <&pinctrl_usdhc2>;
571 cd-gpios = <&gpio2 2 0>;
572 wp-gpios = <&gpio2 3 0>;
577 pinctrl-names = "default";
578 pinctrl-0 = <&pinctrl_usdhc3>;
580 cd-gpios = <&gpio2 0 0>;
581 wp-gpios = <&gpio2 1 0>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&pinctrl_usdhc4>;