2 * Copyright 2013 Lothar Waßmann <LW@KARO-electronics.de>
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <dt-bindings/gpio/gpio.h>
19 lcdif_23bit_pins_a = &tx6_pinctrl_disp0_1;
20 lcdif_24bit_pins_a = &tx6_pinctrl_disp0_2;
28 bootargs = "init=/linuxrc console=ttymxc0,115200 root=/dev/mtdblock3 rootfstype=jffs2 ro debug panic=1";
32 reg = <0 0>; /* will be filled by U-Boot */
39 compatible = "fixed-clock";
42 clock-frequency = <27000000>;
47 compatible = "pwm-backlight";
48 pwms = <&pwm2 0 500000>;
49 power-supply = <®_3v3>;
51 * a poor man's way to create an inverse 1:1 relationship
52 * between the PWM value and the actual duty cycle
54 brightness-levels = <100
55 99 98 97 96 95 94 93 92 91 90
56 89 88 87 86 85 84 83 82 81 80
57 79 78 77 76 75 74 73 72 71 70
58 69 68 67 66 65 64 63 62 61 60
59 59 58 57 56 55 54 53 52 51 50
60 49 48 47 46 45 44 43 42 41 40
61 39 38 37 36 35 34 33 32 31 30
62 29 28 27 26 25 24 23 22 21 20
63 19 18 17 16 15 14 13 12 11 10
65 default-brightness-level = <50>;
69 compatible = "pwm-backlight";
70 pwms = <&pwm1 0 500000>;
71 power-supply = <®_3v3>;
73 * a poor man's way to create a 1:1 relationship between
74 * the PWM value and the actual duty cycle
76 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
77 10 11 12 13 14 15 16 17 18 19
78 20 21 22 23 24 25 26 27 28 29
79 30 31 32 33 34 35 36 37 38 39
80 40 41 42 43 44 45 46 47 48 49
81 50 51 52 53 54 55 56 57 58 59
82 60 61 62 63 64 65 66 67 68 69
83 70 71 72 73 74 75 76 77 78 79
84 80 81 82 83 84 85 86 87 88 89
85 90 91 92 93 94 95 96 97 98 99
87 default-brightness-level = <50>;
91 display: display@di0 {
92 compatible = "fsl,imx-parallel-display";
94 interface-pix-fmt = "rgb24";
95 pinctrl-names = "default";
96 pinctrl-0 = <&tx6_pinctrl_disp0_1>;
101 clock-frequency = <25200000>;
113 pixelclk-active = <0>;
117 clock-frequency = <25200000>;
129 pixelclk-active = <0>;
133 clock-frequency = <6413760>;
145 pixelclk-active = <0>;
149 clock-frequency = <9009000>;
161 pixelclk-active = <1>;
165 clock-frequency = <33264000>;
177 pixelclk-active = <0>;
180 ET0700 { /* same as ET0500 */
181 clock-frequency = <33264000>;
193 pixelclk-active = <0>;
197 clock-frequency = <6596040>;
209 pixelclk-active = <0>;
215 compatible = "gpio-keys";
218 label = "Power Button";
219 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
220 linux,code = <116>; /* KEY_POWER */
226 compatible = "gpio-leds";
230 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
231 linux,default-trigger = "heartbeat";
236 compatible = "simple-bus";
238 reg_3v3_etn: 3v3-etn {
239 compatible = "regulator-fixed";
240 regulator-name = "3V3_ETN";
241 regulator-min-microvolt = <3300000>;
242 regulator-max-microvolt = <3300000>;
243 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
248 compatible = "regulator-fixed";
249 regulator-name = "2V5";
250 regulator-min-microvolt = <2500000>;
251 regulator-max-microvolt = <2500000>;
256 compatible = "regulator-fixed";
257 regulator-name = "3V3";
258 regulator-min-microvolt = <3300000>;
259 regulator-max-microvolt = <3300000>;
263 reg_can_xcvr: can-xcvr {
264 compatible = "regulator-fixed";
265 regulator-name = "CAN XCVR";
266 regulator-min-microvolt = <3300000>;
267 regulator-max-microvolt = <3300000>;
268 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_tx6qdl_flexcan_xcvr>;
274 reg_lcd_pwr0: lcd-power@0 {
275 compatible = "regulator-fixed";
276 regulator-name = "LCD POWER";
277 regulator-min-microvolt = <3300000>;
278 regulator-max-microvolt = <3300000>;
279 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
284 reg_lcd_pwr1: lcd-power@1 {
285 compatible = "regulator-fixed";
286 regulator-name = "LCD POWER";
287 regulator-min-microvolt = <3300000>;
288 regulator-max-microvolt = <3300000>;
289 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
294 reg_lcd_reset: lcd-reset {
295 compatible = "regulator-fixed";
296 regulator-name = "LCD RESET";
297 regulator-min-microvolt = <3300000>;
298 regulator-max-microvolt = <3300000>;
299 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
300 startup-delay-us = <300000>;
306 reg_usbh1_vbus: usbh1_vbus {
307 compatible = "regulator-fixed";
308 regulator-name = "usbh1_vbus";
309 regulator-min-microvolt = <5000000>;
310 regulator-max-microvolt = <5000000>;
311 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
315 reg_usbotg_vbus: usbotg_vbus {
316 compatible = "regulator-fixed";
317 regulator-name = "usbotg_vbus";
318 regulator-min-microvolt = <5000000>;
319 regulator-max-microvolt = <5000000>;
320 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
326 compatible = "fsl,imx6qdl-tx6qdl-sgtl5000",
327 "fsl,imx-audio-sgtl5000";
328 model = "sgtl5000-audio";
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_audmux_5>;
331 ssi-controller = <&ssi1>;
332 audio-codec = <&sgtl5000>;
334 "MIC_IN", "Mic Jack",
335 "Mic Jack", "Mic Bias",
336 "Headphone Jack", "HP_OUT";
347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_flexcan1_3>;
349 xceiver-supply = <®_can_xcvr>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_flexcan2_1>;
357 xceiver-supply = <®_can_xcvr>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_enet_4>;
366 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
367 phy-supply = <®_3v3_etn>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_tx6_gpmi_nand>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_i2c1_1>;
381 clock-frequency = <400000>;
385 compatible = "dallas,ds1339";
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_i2c3_2>;
393 clock-frequency = <400000>;
396 touchscreen: tsc2007@48 {
397 compatible = "ti,tsc2007";
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_tsc2007_1>;
401 interrupt-parent = <&gpio3>;
403 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
404 ti,x-plate-ohms = <660>;
408 polytouch: edt-ft5x06@38 {
409 compatible = "edt,edt-ft5x06";
411 pinctrl-names = "default";
412 pinctrl-0 = <&pinctrl_edt_ft5x06_1>;
413 interrupt-parent = <&gpio6>;
415 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
416 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
419 sgtl5000: sgtl5000@0a {
420 compatible = "fsl,sgtl5000";
422 VDDA-supply = <®_2v5>;
423 VDDIO-supply = <®_3v3>;
429 pinctrl-names = "default";
430 pinctrl-0 = <&pinctrl_hog>;
433 tx6_pinctrl_disp0_1: disp0grp-1 {
435 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
436 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
437 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
438 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
439 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
440 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
441 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
442 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
443 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
444 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
445 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
446 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
447 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
448 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
449 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
450 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
451 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
452 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
453 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
454 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
455 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
456 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
457 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
458 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
459 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
460 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
461 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
462 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
466 tx6_pinctrl_disp0_2: disp0grp-2 {
468 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
469 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
470 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
471 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
472 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
473 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
474 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
475 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
476 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
477 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
478 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
479 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
480 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
481 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
482 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
483 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
484 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
485 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
486 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
487 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
488 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
489 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
490 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
491 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
492 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
493 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
494 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
495 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
501 pinctrl_tx6qdl_flexcan_xcvr: flexcan-xcvrgrp-1 {
503 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
509 pinctrl_hog: hoggrp {
511 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
512 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
513 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
514 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT
515 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x1b0b0 /* SD1 CD */
516 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x1b0b0 /* SD2 CD */
517 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
518 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
519 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
525 pinctrl_kpp: kppgrp {
527 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
528 MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
529 MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
530 MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
532 MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
533 MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
534 MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
535 MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
541 pinctrl_tx6_gpmi_nand: tx6-gpmi-nand {
543 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
544 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
545 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
546 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
547 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
548 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
549 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
550 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
551 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
552 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
553 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
554 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
555 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
556 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
557 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
563 pinctrl_tsc2007_1: tsc2007grp-1 {
565 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
569 pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 {
571 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
572 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
573 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
579 pinctrl_tx6_usbh1_vbus: tx6-usbh1-vbusgrp {
581 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
587 pinctrl_tx6_usbotg: tx6-usbotggrp {
589 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
593 pinctrl_tx6_usbotg_vbus: tx6-usbotg-vbusgrp {
595 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
602 pinctrl-names = "default";
603 pinctrl-0 = <&pinctrl_kpp>;
605 /* row/col 0,1 are mapped to KPP row/col 6,7 */
607 0x06060074 /* row 6, col 6, KEY_POWER */
608 0x06070052 /* row 6, col 7, KEY_KP0 */
609 0x0602004f /* row 6, col 2, KEY_KP1 */
610 0x06030050 /* row 6, col 3, KEY_KP2 */
611 0x07060051 /* row 7, col 6, KEY_KP3 */
612 0x0707004b /* row 7, col 7, KEY_KP4 */
613 0x0702004c /* row 7, col 2, KEY_KP5 */
614 0x0703004d /* row 7, col 3, KEY_KP6 */
615 0x02060047 /* row 2, col 6, KEY_KP7 */
616 0x02070048 /* row 2, col 7, KEY_KP8 */
617 0x02020049 /* row 2, col 2, KEY_KP9 */
624 lvds0: lvds-channel@0 {
625 fsl,data-mapping = "spwg";
626 fsl,data-width = <18>;
630 native-mode = <&lvds_timing0>;
631 lvds_timing0: hsd100pxn1 {
632 clock-frequency = <65000000>;
645 lvds1: lvds-channel@1 {
646 fsl,data-mapping = "spwg";
647 fsl,data-width = <18>;
651 native-mode = <&lvds_timing1>;
652 lvds_timing1: hsd100pxn1 {
653 clock-frequency = <65000000>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&pinctrl_pwm1_2>;
674 pinctrl-names = "default";
675 pinctrl-0 = <&pinctrl_pwm2_1>;
680 fsl,mode = "i2s-slave";
685 pinctrl-names = "default";
686 pinctrl-0 = <&pinctrl_uart1_2>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&pinctrl_uart2_3 &pinctrl_uart2_rtscts_3>;
697 pinctrl-names = "default";
698 pinctrl-0 = <&pinctrl_uart3_3 &pinctrl_uart3_rtscts_3>;
703 vbus-supply = <®_usbh1_vbus>;
704 pinctrl-names = "default";
705 pinctrl-0 = <&pinctrl_tx6_usbh1_vbus>;
707 disable-over-current;
712 vbus-supply = <®_usbotg_vbus>;
713 pinctrl-names = "default";
714 pinctrl-0 = <&pinctrl_tx6_usbotg &pinctrl_tx6_usbotg_vbus>;
715 dr_mode = "peripheral";
716 disable-over-current;
721 pinctrl-names = "default";
722 pinctrl-0 = <&pinctrl_usdhc1_2>;
723 cd-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
728 pinctrl-names = "default";
729 pinctrl-0 = <&pinctrl_usdhc2_2>;
730 cd-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;