arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         aliases {
  19                 ethernet0 = &fec;
  20                 can0 = &can1;
  21                 can1 = &can2;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 gpio6 = &gpio7;
  29                 i2c0 = &i2c1;
  30                 i2c1 = &i2c2;
  31                 i2c2 = &i2c3;
  32                 mmc0 = &usdhc1;
  33                 mmc1 = &usdhc2;
  34                 mmc2 = &usdhc3;
  35                 mmc3 = &usdhc4;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 serial4 = &uart5;
  41                 spi0 = &ecspi1;
  42                 spi1 = &ecspi2;
  43                 spi2 = &ecspi3;
  44                 spi3 = &ecspi4;
  45                 usbphy0 = &usbphy1;
  46                 usbphy1 = &usbphy2;
  47         };
  48
  49         intc: interrupt-controller@00a01000 {
  50                 compatible = "arm,cortex-a9-gic";
  51                 #interrupt-cells = <3>;
  52                 interrupt-controller;
  53                 reg = <0x00a01000 0x1000>,
  54                       <0x00a00100 0x100>;
  55         };
  56
  57         clocks {
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60
  61                 ckil {
  62                         compatible = "fsl,imx-ckil", "fixed-clock";
  63                         #clock-cells = <0>;
  64                         clock-frequency = <32768>;
  65                 };
  66
  67                 ckih1 {
  68                         compatible = "fsl,imx-ckih1", "fixed-clock";
  69                         #clock-cells = <0>;
  70                         clock-frequency = <0>;
  71                 };
  72
  73                 osc {
  74                         compatible = "fsl,imx-osc", "fixed-clock";
  75                         #clock-cells = <0>;
  76                         clock-frequency = <24000000>;
  77                 };
  78         };
  79
  80         soc {
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 compatible = "simple-bus";
  84                 interrupt-parent = <&intc>;
  85                 ranges;
  86
  87                 dma_apbh: dma-apbh@00110000 {
  88                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  89                         reg = <0x00110000 0x2000>;
  90                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  91                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  94                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  95                         #dma-cells = <1>;
  96                         dma-channels = <4>;
  97                         clocks = <&clks 106>;
  98                 };
  99
 100                 gpmi: gpmi-nand@00112000 {
 101                         compatible = "fsl,imx6q-gpmi-nand";
 102                         #address-cells = <1>;
 103                         #size-cells = <1>;
 104                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 105                         reg-names = "gpmi-nand", "bch";
 106                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 107                         interrupt-names = "bch";
 108                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
 109                                  <&clks 150>, <&clks 149>;
 110                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 111                                       "gpmi_bch_apb", "per1_bch";
 112                         dmas = <&dma_apbh 0>;
 113                         dma-names = "rx-tx";
 114                         status = "disabled";
 115                 };
 116
 117                 ocram: sram@00900000 {
 118                         compatible = "mmio-sram";
 119                         reg = <0x00900000 0x3f000>;
 120                         clocks = <&clks 142>;
 121                 };
 122
 123                 timer@00a00600 {
 124                         compatible = "arm,cortex-a9-twd-timer";
 125                         reg = <0x00a00600 0x20>;
 126                         interrupts = <1 13 0xf01>;
 127                         clocks = <&clks 15>;
 128                 };
 129
 130                 L2: l2-cache@00a02000 {
 131                         compatible = "arm,pl310-cache";
 132                         reg = <0x00a02000 0x1000>;
 133                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 134                         cache-unified;
 135                         cache-level = <2>;
 136                         arm,tag-latency = <4 2 3>;
 137                         arm,data-latency = <4 2 3>;
 138                 };
 139
 140                 pcie: pcie@0x01000000 {
 141                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 142                         reg = <0x01ffc000 0x4000>; /* DBI */
 143                         #address-cells = <3>;
 144                         #size-cells = <2>;
 145                         device_type = "pci";
 146                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 147                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 148                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 149                         num-lanes = <1>;
 150                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 151                         interrupt-names = "msi";
 152                         #interrupt-cells = <1>;
 153                         interrupt-map-mask = <0 0 0 0x7>;
 154                         interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 155                                         <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 156                                         <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 157                                         <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 158                         clocks = <&clks 144>, <&clks 206>, <&clks 189>;
 159                         clock-names = "pcie", "pcie_bus", "pcie_phy";
 160                         status = "disabled";
 161                 };
 162
 163                 pmu {
 164                         compatible = "arm,cortex-a9-pmu";
 165                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 166                 };
 167
 168                 aips-bus@02000000 { /* AIPS1 */
 169                         compatible = "fsl,aips-bus", "simple-bus";
 170                         #address-cells = <1>;
 171                         #size-cells = <1>;
 172                         reg = <0x02000000 0x100000>;
 173                         ranges;
 174
 175                         spba-bus@02000000 {
 176                                 compatible = "fsl,spba-bus", "simple-bus";
 177                                 #address-cells = <1>;
 178                                 #size-cells = <1>;
 179                                 reg = <0x02000000 0x40000>;
 180                                 ranges;
 181
 182                                 spdif: spdif@02004000 {
 183                                         compatible = "fsl,imx35-spdif";
 184                                         reg = <0x02004000 0x4000>;
 185                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 186                                         dmas = <&sdma 14 18 0>,
 187                                                <&sdma 15 18 0>;
 188                                         dma-names = "rx", "tx";
 189                                         clocks = <&clks 197>, <&clks 3>,
 190                                                  <&clks 197>, <&clks 107>,
 191                                                  <&clks 0>,   <&clks 118>,
 192                                                  <&clks 0>,  <&clks 139>,
 193                                                  <&clks 0>;
 194                                         clock-names = "core",  "rxtx0",
 195                                                       "rxtx1", "rxtx2",
 196                                                       "rxtx3", "rxtx4",
 197                                                       "rxtx5", "rxtx6",
 198                                                       "rxtx7";
 199                                         status = "disabled";
 200                                 };
 201
 202                                 ecspi1: ecspi@02008000 {
 203                                         #address-cells = <1>;
 204                                         #size-cells = <0>;
 205                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 206                                         reg = <0x02008000 0x4000>;
 207                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 208                                         clocks = <&clks 112>, <&clks 112>;
 209                                         clock-names = "ipg", "per";
 210                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 211                                         dma-names = "rx", "tx";
 212                                         status = "disabled";
 213                                 };
 214
 215                                 ecspi2: ecspi@0200c000 {
 216                                         #address-cells = <1>;
 217                                         #size-cells = <0>;
 218                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 219                                         reg = <0x0200c000 0x4000>;
 220                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 221                                         clocks = <&clks 113>, <&clks 113>;
 222                                         clock-names = "ipg", "per";
 223                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 224                                         dma-names = "rx", "tx";
 225                                         status = "disabled";
 226                                 };
 227
 228                                 ecspi3: ecspi@02010000 {
 229                                         #address-cells = <1>;
 230                                         #size-cells = <0>;
 231                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 232                                         reg = <0x02010000 0x4000>;
 233                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 234                                         clocks = <&clks 114>, <&clks 114>;
 235                                         clock-names = "ipg", "per";
 236                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 237                                         dma-names = "rx", "tx";
 238                                         status = "disabled";
 239                                 };
 240
 241                                 ecspi4: ecspi@02014000 {
 242                                         #address-cells = <1>;
 243                                         #size-cells = <0>;
 244                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 245                                         reg = <0x02014000 0x4000>;
 246                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 247                                         clocks = <&clks 115>, <&clks 115>;
 248                                         clock-names = "ipg", "per";
 249                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 250                                         dma-names = "rx", "tx";
 251                                         status = "disabled";
 252                                 };
 253
 254                                 uart1: serial@02020000 {
 255                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 256                                         reg = <0x02020000 0x4000>;
 257                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 258                                         clocks = <&clks 160>, <&clks 161>;
 259                                         clock-names = "ipg", "per";
 260                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 261                                         dma-names = "rx", "tx";
 262                                         status = "disabled";
 263                                 };
 264
 265                                 esai: esai@02024000 {
 266                                         reg = <0x02024000 0x4000>;
 267                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 268                                 };
 269
 270                                 ssi1: ssi@02028000 {
 271                                         compatible = "fsl,imx6q-ssi",
 272                                                         "fsl,imx51-ssi",
 273                                                         "fsl,imx21-ssi";
 274                                         reg = <0x02028000 0x4000>;
 275                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 276                                         clocks = <&clks 178>;
 277                                         dmas = <&sdma 37 1 0>,
 278                                                <&sdma 38 1 0>;
 279                                         dma-names = "rx", "tx";
 280                                         fsl,fifo-depth = <15>;
 281                                         fsl,ssi-dma-events = <38 37>;
 282                                         status = "disabled";
 283                                 };
 284
 285                                 ssi2: ssi@0202c000 {
 286                                         compatible = "fsl,imx6q-ssi",
 287                                                         "fsl,imx51-ssi",
 288                                                         "fsl,imx21-ssi";
 289                                         reg = <0x0202c000 0x4000>;
 290                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 291                                         clocks = <&clks 179>;
 292                                         dmas = <&sdma 41 1 0>,
 293                                                <&sdma 42 1 0>;
 294                                         dma-names = "rx", "tx";
 295                                         fsl,fifo-depth = <15>;
 296                                         fsl,ssi-dma-events = <42 41>;
 297                                         status = "disabled";
 298                                 };
 299
 300                                 ssi3: ssi@02030000 {
 301                                         compatible = "fsl,imx6q-ssi",
 302                                                         "fsl,imx51-ssi",
 303                                                         "fsl,imx21-ssi";
 304                                         reg = <0x02030000 0x4000>;
 305                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 306                                         clocks = <&clks 180>;
 307                                         dmas = <&sdma 45 1 0>,
 308                                                <&sdma 46 1 0>;
 309                                         dma-names = "rx", "tx";
 310                                         fsl,fifo-depth = <15>;
 311                                         fsl,ssi-dma-events = <46 45>;
 312                                         status = "disabled";
 313                                 };
 314
 315                                 asrc: asrc@02034000 {
 316                                         reg = <0x02034000 0x4000>;
 317                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 318                                 };
 319
 320                                 spba@0203c000 {
 321                                         reg = <0x0203c000 0x4000>;
 322                                 };
 323                         };
 324
 325                         vpu: vpu@02040000 {
 326                                 reg = <0x02040000 0x3c000>;
 327                                 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
 328                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
 329                         };
 330
 331                         aipstz@0207c000 { /* AIPSTZ1 */
 332                                 reg = <0x0207c000 0x4000>;
 333                         };
 334
 335                         pwm1: pwm@02080000 {
 336                                 #pwm-cells = <2>;
 337                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 338                                 reg = <0x02080000 0x4000>;
 339                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 340                                 clocks = <&clks 62>, <&clks 145>;
 341                                 clock-names = "ipg", "per";
 342                         };
 343
 344                         pwm2: pwm@02084000 {
 345                                 #pwm-cells = <2>;
 346                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 347                                 reg = <0x02084000 0x4000>;
 348                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 349                                 clocks = <&clks 62>, <&clks 146>;
 350                                 clock-names = "ipg", "per";
 351                         };
 352
 353                         pwm3: pwm@02088000 {
 354                                 #pwm-cells = <2>;
 355                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 356                                 reg = <0x02088000 0x4000>;
 357                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 358                                 clocks = <&clks 62>, <&clks 147>;
 359                                 clock-names = "ipg", "per";
 360                         };
 361
 362                         pwm4: pwm@0208c000 {
 363                                 #pwm-cells = <2>;
 364                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 365                                 reg = <0x0208c000 0x4000>;
 366                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 367                                 clocks = <&clks 62>, <&clks 148>;
 368                                 clock-names = "ipg", "per";
 369                         };
 370
 371                         can1: flexcan@02090000 {
 372                                 compatible = "fsl,imx6q-flexcan";
 373                                 reg = <0x02090000 0x4000>;
 374                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 375                                 clocks = <&clks 108>, <&clks 109>;
 376                                 clock-names = "ipg", "per";
 377                                 status = "disabled";
 378                         };
 379
 380                         can2: flexcan@02094000 {
 381                                 compatible = "fsl,imx6q-flexcan";
 382                                 reg = <0x02094000 0x4000>;
 383                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 384                                 clocks = <&clks 110>, <&clks 111>;
 385                                 clock-names = "ipg", "per";
 386                                 status = "disabled";
 387                         };
 388
 389                         gpt: gpt@02098000 {
 390                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 391                                 reg = <0x02098000 0x4000>;
 392                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 393                                 clocks = <&clks 119>, <&clks 120>;
 394                                 clock-names = "ipg", "per";
 395                         };
 396
 397                         gpio1: gpio@0209c000 {
 398                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 399                                 reg = <0x0209c000 0x4000>;
 400                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 401                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 402                                 gpio-controller;
 403                                 #gpio-cells = <2>;
 404                                 interrupt-controller;
 405                                 #interrupt-cells = <2>;
 406                         };
 407
 408                         gpio2: gpio@020a0000 {
 409                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 410                                 reg = <0x020a0000 0x4000>;
 411                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 412                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 413                                 gpio-controller;
 414                                 #gpio-cells = <2>;
 415                                 interrupt-controller;
 416                                 #interrupt-cells = <2>;
 417                         };
 418
 419                         gpio3: gpio@020a4000 {
 420                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 421                                 reg = <0x020a4000 0x4000>;
 422                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 423                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 424                                 gpio-controller;
 425                                 #gpio-cells = <2>;
 426                                 interrupt-controller;
 427                                 #interrupt-cells = <2>;
 428                         };
 429
 430                         gpio4: gpio@020a8000 {
 431                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 432                                 reg = <0x020a8000 0x4000>;
 433                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 434                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 435                                 gpio-controller;
 436                                 #gpio-cells = <2>;
 437                                 interrupt-controller;
 438                                 #interrupt-cells = <2>;
 439                         };
 440
 441                         gpio5: gpio@020ac000 {
 442                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 443                                 reg = <0x020ac000 0x4000>;
 444                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 445                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 446                                 gpio-controller;
 447                                 #gpio-cells = <2>;
 448                                 interrupt-controller;
 449                                 #interrupt-cells = <2>;
 450                         };
 451
 452                         gpio6: gpio@020b0000 {
 453                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 454                                 reg = <0x020b0000 0x4000>;
 455                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 456                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 457                                 gpio-controller;
 458                                 #gpio-cells = <2>;
 459                                 interrupt-controller;
 460                                 #interrupt-cells = <2>;
 461                         };
 462
 463                         gpio7: gpio@020b4000 {
 464                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 465                                 reg = <0x020b4000 0x4000>;
 466                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 467                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 468                                 gpio-controller;
 469                                 #gpio-cells = <2>;
 470                                 interrupt-controller;
 471                                 #interrupt-cells = <2>;
 472                         };
 473
 474                         kpp: kpp@020b8000 {
 475                                 reg = <0x020b8000 0x4000>;
 476                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 477                         };
 478
 479                         wdog1: wdog@020bc000 {
 480                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 481                                 reg = <0x020bc000 0x4000>;
 482                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 483                                 clocks = <&clks 0>;
 484                         };
 485
 486                         wdog2: wdog@020c0000 {
 487                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 488                                 reg = <0x020c0000 0x4000>;
 489                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 490                                 clocks = <&clks 0>;
 491                                 status = "disabled";
 492                         };
 493
 494                         clks: ccm@020c4000 {
 495                                 compatible = "fsl,imx6q-ccm";
 496                                 reg = <0x020c4000 0x4000>;
 497                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 498                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 499                                 #clock-cells = <1>;
 500                         };
 501
 502                         anatop: anatop@020c8000 {
 503                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 504                                 reg = <0x020c8000 0x1000>;
 505                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 506                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 507                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 508
 509                                 regulator-1p1@110 {
 510                                         compatible = "fsl,anatop-regulator";
 511                                         regulator-name = "vdd1p1";
 512                                         regulator-min-microvolt = <800000>;
 513                                         regulator-max-microvolt = <1375000>;
 514                                         regulator-always-on;
 515                                         anatop-reg-offset = <0x110>;
 516                                         anatop-vol-bit-shift = <8>;
 517                                         anatop-vol-bit-width = <5>;
 518                                         anatop-min-bit-val = <4>;
 519                                         anatop-min-voltage = <800000>;
 520                                         anatop-max-voltage = <1375000>;
 521                                 };
 522
 523                                 regulator-3p0@120 {
 524                                         compatible = "fsl,anatop-regulator";
 525                                         regulator-name = "vdd3p0";
 526                                         regulator-min-microvolt = <2800000>;
 527                                         regulator-max-microvolt = <3150000>;
 528                                         regulator-always-on;
 529                                         anatop-reg-offset = <0x120>;
 530                                         anatop-vol-bit-shift = <8>;
 531                                         anatop-vol-bit-width = <5>;
 532                                         anatop-min-bit-val = <0>;
 533                                         anatop-min-voltage = <2625000>;
 534                                         anatop-max-voltage = <3400000>;
 535                                 };
 536
 537                                 regulator-2p5@130 {
 538                                         compatible = "fsl,anatop-regulator";
 539                                         regulator-name = "vdd2p5";
 540                                         regulator-min-microvolt = <2000000>;
 541                                         regulator-max-microvolt = <2750000>;
 542                                         regulator-always-on;
 543                                         anatop-reg-offset = <0x130>;
 544                                         anatop-vol-bit-shift = <8>;
 545                                         anatop-vol-bit-width = <5>;
 546                                         anatop-min-bit-val = <0>;
 547                                         anatop-min-voltage = <2000000>;
 548                                         anatop-max-voltage = <2750000>;
 549                                 };
 550
 551                                 reg_arm: regulator-vddcore@140 {
 552                                         compatible = "fsl,anatop-regulator";
 553                                         regulator-name = "vddarm";
 554                                         regulator-min-microvolt = <725000>;
 555                                         regulator-max-microvolt = <1450000>;
 556                                         regulator-always-on;
 557                                         anatop-reg-offset = <0x140>;
 558                                         anatop-vol-bit-shift = <0>;
 559                                         anatop-vol-bit-width = <5>;
 560                                         anatop-delay-reg-offset = <0x170>;
 561                                         anatop-delay-bit-shift = <24>;
 562                                         anatop-delay-bit-width = <2>;
 563                                         anatop-min-bit-val = <1>;
 564                                         anatop-min-voltage = <725000>;
 565                                         anatop-max-voltage = <1450000>;
 566                                 };
 567
 568                                 reg_pu: regulator-vddpu@140 {
 569                                         compatible = "fsl,anatop-regulator";
 570                                         regulator-name = "vddpu";
 571                                         regulator-min-microvolt = <725000>;
 572                                         regulator-max-microvolt = <1450000>;
 573                                         regulator-always-on;
 574                                         anatop-reg-offset = <0x140>;
 575                                         anatop-vol-bit-shift = <9>;
 576                                         anatop-vol-bit-width = <5>;
 577                                         anatop-delay-reg-offset = <0x170>;
 578                                         anatop-delay-bit-shift = <26>;
 579                                         anatop-delay-bit-width = <2>;
 580                                         anatop-min-bit-val = <1>;
 581                                         anatop-min-voltage = <725000>;
 582                                         anatop-max-voltage = <1450000>;
 583                                 };
 584
 585                                 reg_soc: regulator-vddsoc@140 {
 586                                         compatible = "fsl,anatop-regulator";
 587                                         regulator-name = "vddsoc";
 588                                         regulator-min-microvolt = <725000>;
 589                                         regulator-max-microvolt = <1450000>;
 590                                         regulator-always-on;
 591                                         anatop-reg-offset = <0x140>;
 592                                         anatop-vol-bit-shift = <18>;
 593                                         anatop-vol-bit-width = <5>;
 594                                         anatop-delay-reg-offset = <0x170>;
 595                                         anatop-delay-bit-shift = <28>;
 596                                         anatop-delay-bit-width = <2>;
 597                                         anatop-min-bit-val = <1>;
 598                                         anatop-min-voltage = <725000>;
 599                                         anatop-max-voltage = <1450000>;
 600                                 };
 601                         };
 602
 603                         tempmon: tempmon {
 604                                 compatible = "fsl,imx6q-tempmon";
 605                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 606                                 fsl,tempmon = <&anatop>;
 607                                 fsl,tempmon-data = <&ocotp>;
 608                                 clocks = <&clks 172>;
 609                         };
 610
 611                         usbphy1: usbphy@020c9000 {
 612                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 613                                 reg = <0x020c9000 0x1000>;
 614                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 615                                 clocks = <&clks 182>;
 616                                 fsl,anatop = <&anatop>;
 617                         };
 618
 619                         usbphy2: usbphy@020ca000 {
 620                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 621                                 reg = <0x020ca000 0x1000>;
 622                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 623                                 clocks = <&clks 183>;
 624                                 fsl,anatop = <&anatop>;
 625                         };
 626
 627                         snvs@020cc000 {
 628                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 629                                 #address-cells = <1>;
 630                                 #size-cells = <1>;
 631                                 ranges = <0 0x020cc000 0x4000>;
 632
 633                                 snvs-rtc-lp@34 {
 634                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 635                                         reg = <0x34 0x58>;
 636                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 637                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 638                                 };
 639                         };
 640
 641                         epit1: epit@020d0000 { /* EPIT1 */
 642                                 reg = <0x020d0000 0x4000>;
 643                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 644                         };
 645
 646                         epit2: epit@020d4000 { /* EPIT2 */
 647                                 reg = <0x020d4000 0x4000>;
 648                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 649                         };
 650
 651                         src: src@020d8000 {
 652                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 653                                 reg = <0x020d8000 0x4000>;
 654                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 655                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 656                                 #reset-cells = <1>;
 657                         };
 658
 659                         gpc: gpc@020dc000 {
 660                                 compatible = "fsl,imx6q-gpc";
 661                                 reg = <0x020dc000 0x4000>;
 662                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 663                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 664                         };
 665
 666                         gpr: iomuxc-gpr@020e0000 {
 667                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 668                                 reg = <0x020e0000 0x38>;
 669                         };
 670
 671                         iomuxc: iomuxc@020e0000 {
 672                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 673                                 reg = <0x020e0000 0x4000>;
 674                         };
 675
 676                         ldb: ldb@020e0008 {
 677                                 #address-cells = <1>;
 678                                 #size-cells = <0>;
 679                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 680                                 gpr = <&gpr>;
 681                                 status = "disabled";
 682
 683                                 lvds-channel@0 {
 684                                         #address-cells = <1>;
 685                                         #size-cells = <0>;
 686                                         reg = <0>;
 687                                         status = "disabled";
 688
 689                                         port@0 {
 690                                                 reg = <0>;
 691
 692                                                 lvds0_mux_0: endpoint {
 693                                                         remote-endpoint = <&ipu1_di0_lvds0>;
 694                                                 };
 695                                         };
 696
 697                                         port@1 {
 698                                                 reg = <1>;
 699
 700                                                 lvds0_mux_1: endpoint {
 701                                                         remote-endpoint = <&ipu1_di1_lvds0>;
 702                                                 };
 703                                         };
 704                                 };
 705
 706                                 lvds-channel@1 {
 707                                         #address-cells = <1>;
 708                                         #size-cells = <0>;
 709                                         reg = <1>;
 710                                         status = "disabled";
 711
 712                                         port@0 {
 713                                                 reg = <0>;
 714
 715                                                 lvds1_mux_0: endpoint {
 716                                                         remote-endpoint = <&ipu1_di0_lvds1>;
 717                                                 };
 718                                         };
 719
 720                                         port@1 {
 721                                                 reg = <1>;
 722
 723                                                 lvds1_mux_1: endpoint {
 724                                                         remote-endpoint = <&ipu1_di1_lvds1>;
 725                                                 };
 726                                         };
 727                                 };
 728                         };
 729
 730                         hdmi: hdmi@0120000 {
 731                                 #address-cells = <1>;
 732                                 #size-cells = <0>;
 733                                 reg = <0x00120000 0x9000>;
 734                                 interrupts = <0 115 0x04>;
 735                                 gpr = <&gpr>;
 736                                 clocks = <&clks 123>, <&clks 124>;
 737                                 clock-names = "iahb", "isfr";
 738                                 status = "disabled";
 739
 740                                 port@0 {
 741                                         reg = <0>;
 742
 743                                         hdmi_mux_0: endpoint {
 744                                                 remote-endpoint = <&ipu1_di0_hdmi>;
 745                                         };
 746                                 };
 747
 748                                 port@1 {
 749                                         reg = <1>;
 750
 751                                         hdmi_mux_1: endpoint {
 752                                                 remote-endpoint = <&ipu1_di1_hdmi>;
 753                                         };
 754                                 };
 755                         };
 756
 757                         dcic1: dcic@020e4000 {
 758                                 reg = <0x020e4000 0x4000>;
 759                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 760                         };
 761
 762                         dcic2: dcic@020e8000 {
 763                                 reg = <0x020e8000 0x4000>;
 764                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 765                         };
 766
 767                         sdma: sdma@020ec000 {
 768                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 769                                 reg = <0x020ec000 0x4000>;
 770                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 771                                 clocks = <&clks 155>, <&clks 155>;
 772                                 clock-names = "ipg", "ahb";
 773                                 #dma-cells = <3>;
 774                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 775                         };
 776                 };
 777
 778                 aips-bus@02100000 { /* AIPS2 */
 779                         compatible = "fsl,aips-bus", "simple-bus";
 780                         #address-cells = <1>;
 781                         #size-cells = <1>;
 782                         reg = <0x02100000 0x100000>;
 783                         ranges;
 784
 785                         caam@02100000 {
 786                                 reg = <0x02100000 0x40000>;
 787                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 788                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 789                         };
 790
 791                         aipstz@0217c000 { /* AIPSTZ2 */
 792                                 reg = <0x0217c000 0x4000>;
 793                         };
 794
 795                         usbotg: usb@02184000 {
 796                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 797                                 reg = <0x02184000 0x200>;
 798                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 799                                 clocks = <&clks 162>;
 800                                 fsl,usbphy = <&usbphy1>;
 801                                 fsl,usbmisc = <&usbmisc 0>;
 802                                 status = "disabled";
 803                         };
 804
 805                         usbh1: usb@02184200 {
 806                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 807                                 reg = <0x02184200 0x200>;
 808                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 809                                 clocks = <&clks 162>;
 810                                 fsl,usbphy = <&usbphy2>;
 811                                 fsl,usbmisc = <&usbmisc 1>;
 812                                 status = "disabled";
 813                         };
 814
 815                         usbh2: usb@02184400 {
 816                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 817                                 reg = <0x02184400 0x200>;
 818                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 819                                 clocks = <&clks 162>;
 820                                 fsl,usbmisc = <&usbmisc 2>;
 821                                 status = "disabled";
 822                         };
 823
 824                         usbh3: usb@02184600 {
 825                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 826                                 reg = <0x02184600 0x200>;
 827                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 828                                 clocks = <&clks 162>;
 829                                 fsl,usbmisc = <&usbmisc 3>;
 830                                 status = "disabled";
 831                         };
 832
 833                         usbmisc: usbmisc@02184800 {
 834                                 #index-cells = <1>;
 835                                 compatible = "fsl,imx6q-usbmisc";
 836                                 reg = <0x02184800 0x200>;
 837                                 clocks = <&clks 162>;
 838                         };
 839
 840                         fec: ethernet@02188000 {
 841                                 compatible = "fsl,imx6q-fec";
 842                                 reg = <0x02188000 0x4000>;
 843                                 interrupts-extended =
 844                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 845                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 846                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
 847                                 clock-names = "ipg", "ahb", "ptp";
 848                                 status = "disabled";
 849                         };
 850
 851                         mlb@0218c000 {
 852                                 reg = <0x0218c000 0x4000>;
 853                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 854                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 855                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 856                         };
 857
 858                         usdhc1: usdhc@02190000 {
 859                                 compatible = "fsl,imx6q-usdhc";
 860                                 reg = <0x02190000 0x4000>;
 861                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 862                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
 863                                 clock-names = "ipg", "ahb", "per";
 864                                 bus-width = <4>;
 865                                 status = "disabled";
 866                         };
 867
 868                         usdhc2: usdhc@02194000 {
 869                                 compatible = "fsl,imx6q-usdhc";
 870                                 reg = <0x02194000 0x4000>;
 871                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 872                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
 873                                 clock-names = "ipg", "ahb", "per";
 874                                 bus-width = <4>;
 875                                 status = "disabled";
 876                         };
 877
 878                         usdhc3: usdhc@02198000 {
 879                                 compatible = "fsl,imx6q-usdhc";
 880                                 reg = <0x02198000 0x4000>;
 881                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 882                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
 883                                 clock-names = "ipg", "ahb", "per";
 884                                 bus-width = <4>;
 885                                 status = "disabled";
 886                         };
 887
 888                         usdhc4: usdhc@0219c000 {
 889                                 compatible = "fsl,imx6q-usdhc";
 890                                 reg = <0x0219c000 0x4000>;
 891                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 892                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
 893                                 clock-names = "ipg", "ahb", "per";
 894                                 bus-width = <4>;
 895                                 status = "disabled";
 896                         };
 897
 898                         i2c1: i2c@021a0000 {
 899                                 #address-cells = <1>;
 900                                 #size-cells = <0>;
 901                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 902                                 reg = <0x021a0000 0x4000>;
 903                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 904                                 clocks = <&clks 125>;
 905                                 status = "disabled";
 906                         };
 907
 908                         i2c2: i2c@021a4000 {
 909                                 #address-cells = <1>;
 910                                 #size-cells = <0>;
 911                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 912                                 reg = <0x021a4000 0x4000>;
 913                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 914                                 clocks = <&clks 126>;
 915                                 status = "disabled";
 916                         };
 917
 918                         i2c3: i2c@021a8000 {
 919                                 #address-cells = <1>;
 920                                 #size-cells = <0>;
 921                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 922                                 reg = <0x021a8000 0x4000>;
 923                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 924                                 clocks = <&clks 127>;
 925                                 status = "disabled";
 926                         };
 927
 928                         romcp@021ac000 {
 929                                 reg = <0x021ac000 0x4000>;
 930                         };
 931
 932                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 933                                 compatible = "fsl,imx6q-mmdc";
 934                                 reg = <0x021b0000 0x4000>;
 935                         };
 936
 937                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 938                                 reg = <0x021b4000 0x4000>;
 939                         };
 940
 941                         weim: weim@021b8000 {
 942                                 compatible = "fsl,imx6q-weim";
 943                                 reg = <0x021b8000 0x4000>;
 944                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 945                                 clocks = <&clks 196>;
 946                         };
 947
 948                         ocotp: ocotp@021bc000 {
 949                                 compatible = "fsl,imx6q-ocotp", "syscon";
 950                                 reg = <0x021bc000 0x4000>;
 951                         };
 952
 953                         tzasc@021d0000 { /* TZASC1 */
 954                                 reg = <0x021d0000 0x4000>;
 955                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 956                         };
 957
 958                         tzasc@021d4000 { /* TZASC2 */
 959                                 reg = <0x021d4000 0x4000>;
 960                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 961                         };
 962
 963                         audmux: audmux@021d8000 {
 964                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 965                                 reg = <0x021d8000 0x4000>;
 966                                 status = "disabled";
 967                         };
 968
 969                         mipi_csi: mipi@021dc000 {
 970                                 reg = <0x021dc000 0x4000>;
 971                         };
 972
 973                         mipi_dsi: mipi@021e0000 {
 974                                 #address-cells = <1>;
 975                                 #size-cells = <0>;
 976                                 reg = <0x021e0000 0x4000>;
 977                                 status = "disabled";
 978
 979                                 port@0 {
 980                                         reg = <0>;
 981
 982                                         mipi_mux_0: endpoint {
 983                                                 remote-endpoint = <&ipu1_di0_mipi>;
 984                                         };
 985                                 };
 986
 987                                 port@1 {
 988                                         reg = <1>;
 989
 990                                         mipi_mux_1: endpoint {
 991                                                 remote-endpoint = <&ipu1_di1_mipi>;
 992                                         };
 993                                 };
 994                         };
 995
 996                         vdoa@021e4000 {
 997                                 reg = <0x021e4000 0x4000>;
 998                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 999                         };
1000
1001                         uart2: serial@021e8000 {
1002                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1003                                 reg = <0x021e8000 0x4000>;
1004                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1005                                 clocks = <&clks 160>, <&clks 161>;
1006                                 clock-names = "ipg", "per";
1007                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1008                                 dma-names = "rx", "tx";
1009                                 status = "disabled";
1010                         };
1011
1012                         uart3: serial@021ec000 {
1013                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1014                                 reg = <0x021ec000 0x4000>;
1015                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1016                                 clocks = <&clks 160>, <&clks 161>;
1017                                 clock-names = "ipg", "per";
1018                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1019                                 dma-names = "rx", "tx";
1020                                 status = "disabled";
1021                         };
1022
1023                         uart4: serial@021f0000 {
1024                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1025                                 reg = <0x021f0000 0x4000>;
1026                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1027                                 clocks = <&clks 160>, <&clks 161>;
1028                                 clock-names = "ipg", "per";
1029                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1030                                 dma-names = "rx", "tx";
1031                                 status = "disabled";
1032                         };
1033
1034                         uart5: serial@021f4000 {
1035                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1036                                 reg = <0x021f4000 0x4000>;
1037                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1038                                 clocks = <&clks 160>, <&clks 161>;
1039                                 clock-names = "ipg", "per";
1040                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1041                                 dma-names = "rx", "tx";
1042                                 status = "disabled";
1043                         };
1044                 };
1045
1046                 ipu1: ipu@02400000 {
1047                         #address-cells = <1>;
1048                         #size-cells = <0>;
1049                         compatible = "fsl,imx6q-ipu";
1050                         reg = <0x02400000 0x400000>;
1051                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1052                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1053                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1054                         clock-names = "bus", "di0", "di1";
1055                         resets = <&src 2>;
1056
1057                         ipu1_di0: port@2 {
1058                                 #address-cells = <1>;
1059                                 #size-cells = <0>;
1060                                 reg = <2>;
1061
1062                                 ipu1_di0_disp0: endpoint@0 {
1063                                 };
1064
1065                                 ipu1_di0_hdmi: endpoint@1 {
1066                                         remote-endpoint = <&hdmi_mux_0>;
1067                                 };
1068
1069                                 ipu1_di0_mipi: endpoint@2 {
1070                                         remote-endpoint = <&mipi_mux_0>;
1071                                 };
1072
1073                                 ipu1_di0_lvds0: endpoint@3 {
1074                                         remote-endpoint = <&lvds0_mux_0>;
1075                                 };
1076
1077                                 ipu1_di0_lvds1: endpoint@4 {
1078                                         remote-endpoint = <&lvds1_mux_0>;
1079                                 };
1080                         };
1081
1082                         ipu1_di1: port@3 {
1083                                 #address-cells = <1>;
1084                                 #size-cells = <0>;
1085                                 reg = <3>;
1086
1087                                 ipu1_di0_disp1: endpoint@0 {
1088                                 };
1089
1090                                 ipu1_di1_hdmi: endpoint@1 {
1091                                         remote-endpoint = <&hdmi_mux_1>;
1092                                 };
1093
1094                                 ipu1_di1_mipi: endpoint@2 {
1095                                         remote-endpoint = <&mipi_mux_1>;
1096                                 };
1097
1098                                 ipu1_di1_lvds0: endpoint@3 {
1099                                         remote-endpoint = <&lvds0_mux_1>;
1100                                 };
1101
1102                                 ipu1_di1_lvds1: endpoint@4 {
1103                                         remote-endpoint = <&lvds1_mux_1>;
1104                                 };
1105                         };
1106                 };
1107         };
1108 };