2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
38 intc: interrupt-controller@00a01000 {
39 compatible = "arm,cortex-a9-gic";
40 #interrupt-cells = <3>;
44 reg = <0x00a01000 0x1000>,
53 compatible = "fsl,imx-ckil", "fixed-clock";
54 clock-frequency = <32768>;
58 compatible = "fsl,imx-ckih1", "fixed-clock";
59 clock-frequency = <0>;
63 compatible = "fsl,imx-osc", "fixed-clock";
64 clock-frequency = <24000000>;
71 compatible = "simple-bus";
72 interrupt-parent = <&intc>;
75 dma_apbh: dma-apbh@00110000 {
76 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
77 reg = <0x00110000 0x2000>;
78 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
79 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
85 gpmi: gpmi-nand@00112000 {
86 compatible = "fsl,imx6q-gpmi-nand";
89 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
90 reg-names = "gpmi-nand", "bch";
91 interrupts = <0 15 0x04>;
92 interrupt-names = "bch";
93 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
94 <&clks 150>, <&clks 149>;
95 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
96 "gpmi_bch_apb", "per1_bch";
103 compatible = "arm,cortex-a9-twd-timer";
104 reg = <0x00a00600 0x20>;
105 interrupts = <1 13 0xf01>;
109 L2: l2-cache@00a02000 {
110 compatible = "arm,pl310-cache";
111 reg = <0x00a02000 0x1000>;
112 interrupts = <0 92 0x04>;
115 arm,tag-latency = <4 2 3>;
116 arm,data-latency = <4 2 3>;
119 pcie: pcie@0x01000000 {
120 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
121 reg = <0x01ffc000 0x4000>; /* DBI */
122 #address-cells = <3>;
125 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
126 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
127 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
129 interrupts = <0 123 0x04>;
130 clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
131 clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
136 compatible = "arm,cortex-a9-pmu";
137 interrupts = <0 94 0x04>;
140 aips-bus@02000000 { /* AIPS1 */
141 compatible = "fsl,aips-bus", "simple-bus";
142 #address-cells = <1>;
144 reg = <0x02000000 0x100000>;
148 compatible = "fsl,spba-bus", "simple-bus";
149 #address-cells = <1>;
151 reg = <0x02000000 0x40000>;
154 spdif: spdif@02004000 {
155 compatible = "fsl,imx35-spdif";
156 reg = <0x02004000 0x4000>;
157 interrupts = <0 52 0x04>;
158 dmas = <&sdma 14 18 0>,
160 dma-names = "rx", "tx";
161 clocks = <&clks 197>, <&clks 3>,
162 <&clks 197>, <&clks 107>,
163 <&clks 0>, <&clks 118>,
164 <&clks 62>, <&clks 139>,
166 clock-names = "core", "rxtx0",
174 ecspi1: ecspi@02008000 {
175 #address-cells = <1>;
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
178 reg = <0x02008000 0x4000>;
179 interrupts = <0 31 0x04>;
180 clocks = <&clks 112>, <&clks 112>;
181 clock-names = "ipg", "per";
185 ecspi2: ecspi@0200c000 {
186 #address-cells = <1>;
188 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
189 reg = <0x0200c000 0x4000>;
190 interrupts = <0 32 0x04>;
191 clocks = <&clks 113>, <&clks 113>;
192 clock-names = "ipg", "per";
196 ecspi3: ecspi@02010000 {
197 #address-cells = <1>;
199 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
200 reg = <0x02010000 0x4000>;
201 interrupts = <0 33 0x04>;
202 clocks = <&clks 114>, <&clks 114>;
203 clock-names = "ipg", "per";
207 ecspi4: ecspi@02014000 {
208 #address-cells = <1>;
210 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
211 reg = <0x02014000 0x4000>;
212 interrupts = <0 34 0x04>;
213 clocks = <&clks 115>, <&clks 115>;
214 clock-names = "ipg", "per";
218 uart1: serial@02020000 {
219 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
220 reg = <0x02020000 0x4000>;
221 interrupts = <0 26 0x04>;
222 clocks = <&clks 160>, <&clks 161>;
223 clock-names = "ipg", "per";
224 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
225 dma-names = "rx", "tx";
229 esai: esai@02024000 {
230 reg = <0x02024000 0x4000>;
231 interrupts = <0 51 0x04>;
235 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
236 reg = <0x02028000 0x4000>;
237 interrupts = <0 46 0x04>;
238 clocks = <&clks 178>;
239 dmas = <&sdma 37 1 0>,
241 dma-names = "rx", "tx";
242 fsl,fifo-depth = <15>;
243 fsl,ssi-dma-events = <38 37>;
248 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
249 reg = <0x0202c000 0x4000>;
250 interrupts = <0 47 0x04>;
251 clocks = <&clks 179>;
252 dmas = <&sdma 41 1 0>,
254 dma-names = "rx", "tx";
255 fsl,fifo-depth = <15>;
256 fsl,ssi-dma-events = <42 41>;
261 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
262 reg = <0x02030000 0x4000>;
263 interrupts = <0 48 0x04>;
264 clocks = <&clks 180>;
265 dmas = <&sdma 45 1 0>,
267 dma-names = "rx", "tx";
268 fsl,fifo-depth = <15>;
269 fsl,ssi-dma-events = <46 45>;
273 asrc: asrc@02034000 {
274 reg = <0x02034000 0x4000>;
275 interrupts = <0 50 0x04>;
279 reg = <0x0203c000 0x4000>;
284 reg = <0x02040000 0x3c000>;
285 interrupts = <0 3 0x04 0 12 0x04>;
288 aipstz@0207c000 { /* AIPSTZ1 */
289 reg = <0x0207c000 0x4000>;
294 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
295 reg = <0x02080000 0x4000>;
296 interrupts = <0 83 0x04>;
297 clocks = <&clks 62>, <&clks 145>;
298 clock-names = "ipg", "per";
303 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
304 reg = <0x02084000 0x4000>;
305 interrupts = <0 84 0x04>;
306 clocks = <&clks 62>, <&clks 146>;
307 clock-names = "ipg", "per";
312 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
313 reg = <0x02088000 0x4000>;
314 interrupts = <0 85 0x04>;
315 clocks = <&clks 62>, <&clks 147>;
316 clock-names = "ipg", "per";
321 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
322 reg = <0x0208c000 0x4000>;
323 interrupts = <0 86 0x04>;
324 clocks = <&clks 62>, <&clks 148>;
325 clock-names = "ipg", "per";
328 can1: flexcan@02090000 {
329 compatible = "fsl,imx6q-flexcan";
330 reg = <0x02090000 0x4000>;
331 interrupts = <0 110 0x04>;
332 clocks = <&clks 108>, <&clks 109>;
333 clock-names = "ipg", "per";
337 can2: flexcan@02094000 {
338 compatible = "fsl,imx6q-flexcan";
339 reg = <0x02094000 0x4000>;
340 interrupts = <0 111 0x04>;
341 clocks = <&clks 110>, <&clks 111>;
342 clock-names = "ipg", "per";
347 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
348 reg = <0x02098000 0x4000>;
349 interrupts = <0 55 0x04>;
350 clocks = <&clks 119>, <&clks 120>;
351 clock-names = "ipg", "per";
354 gpio1: gpio@0209c000 {
355 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
356 reg = <0x0209c000 0x4000>;
357 interrupts = <0 66 0x04 0 67 0x04>;
360 interrupt-controller;
361 #interrupt-cells = <2>;
364 gpio2: gpio@020a0000 {
365 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
366 reg = <0x020a0000 0x4000>;
367 interrupts = <0 68 0x04 0 69 0x04>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
374 gpio3: gpio@020a4000 {
375 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
376 reg = <0x020a4000 0x4000>;
377 interrupts = <0 70 0x04 0 71 0x04>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
384 gpio4: gpio@020a8000 {
385 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
386 reg = <0x020a8000 0x4000>;
387 interrupts = <0 72 0x04 0 73 0x04>;
390 interrupt-controller;
391 #interrupt-cells = <2>;
394 gpio5: gpio@020ac000 {
395 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
396 reg = <0x020ac000 0x4000>;
397 interrupts = <0 74 0x04 0 75 0x04>;
400 interrupt-controller;
401 #interrupt-cells = <2>;
404 gpio6: gpio@020b0000 {
405 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
406 reg = <0x020b0000 0x4000>;
407 interrupts = <0 76 0x04 0 77 0x04>;
410 interrupt-controller;
411 #interrupt-cells = <2>;
414 gpio7: gpio@020b4000 {
415 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
416 reg = <0x020b4000 0x4000>;
417 interrupts = <0 78 0x04 0 79 0x04>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
425 reg = <0x020b8000 0x4000>;
426 interrupts = <0 82 0x04>;
429 wdog1: wdog@020bc000 {
430 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
431 reg = <0x020bc000 0x4000>;
432 interrupts = <0 80 0x04>;
436 wdog2: wdog@020c0000 {
437 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
438 reg = <0x020c0000 0x4000>;
439 interrupts = <0 81 0x04>;
445 compatible = "fsl,imx6q-ccm";
446 reg = <0x020c4000 0x4000>;
447 interrupts = <0 87 0x04 0 88 0x04>;
451 anatop: anatop@020c8000 {
452 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
453 reg = <0x020c8000 0x1000>;
454 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
457 compatible = "fsl,anatop-regulator";
458 regulator-name = "vdd1p1";
459 regulator-min-microvolt = <800000>;
460 regulator-max-microvolt = <1375000>;
462 anatop-reg-offset = <0x110>;
463 anatop-vol-bit-shift = <8>;
464 anatop-vol-bit-width = <5>;
465 anatop-min-bit-val = <4>;
466 anatop-min-voltage = <800000>;
467 anatop-max-voltage = <1375000>;
471 compatible = "fsl,anatop-regulator";
472 regulator-name = "vdd3p0";
473 regulator-min-microvolt = <2800000>;
474 regulator-max-microvolt = <3150000>;
476 anatop-reg-offset = <0x120>;
477 anatop-vol-bit-shift = <8>;
478 anatop-vol-bit-width = <5>;
479 anatop-min-bit-val = <0>;
480 anatop-min-voltage = <2625000>;
481 anatop-max-voltage = <3400000>;
485 compatible = "fsl,anatop-regulator";
486 regulator-name = "vdd2p5";
487 regulator-min-microvolt = <2000000>;
488 regulator-max-microvolt = <2750000>;
490 anatop-reg-offset = <0x130>;
491 anatop-vol-bit-shift = <8>;
492 anatop-vol-bit-width = <5>;
493 anatop-min-bit-val = <0>;
494 anatop-min-voltage = <2000000>;
495 anatop-max-voltage = <2750000>;
498 reg_arm: regulator-vddcore@140 {
499 compatible = "fsl,anatop-regulator";
500 regulator-name = "cpu";
501 regulator-min-microvolt = <725000>;
502 regulator-max-microvolt = <1450000>;
504 anatop-reg-offset = <0x140>;
505 anatop-vol-bit-shift = <0>;
506 anatop-vol-bit-width = <5>;
507 anatop-delay-reg-offset = <0x170>;
508 anatop-delay-bit-shift = <24>;
509 anatop-delay-bit-width = <2>;
510 anatop-min-bit-val = <1>;
511 anatop-min-voltage = <725000>;
512 anatop-max-voltage = <1450000>;
515 reg_pu: regulator-vddpu@140 {
516 compatible = "fsl,anatop-regulator";
517 regulator-name = "vddpu";
518 regulator-min-microvolt = <725000>;
519 regulator-max-microvolt = <1450000>;
521 anatop-reg-offset = <0x140>;
522 anatop-vol-bit-shift = <9>;
523 anatop-vol-bit-width = <5>;
524 anatop-delay-reg-offset = <0x170>;
525 anatop-delay-bit-shift = <26>;
526 anatop-delay-bit-width = <2>;
527 anatop-min-bit-val = <1>;
528 anatop-min-voltage = <725000>;
529 anatop-max-voltage = <1450000>;
532 reg_soc: regulator-vddsoc@140 {
533 compatible = "fsl,anatop-regulator";
534 regulator-name = "vddsoc";
535 regulator-min-microvolt = <725000>;
536 regulator-max-microvolt = <1450000>;
538 anatop-reg-offset = <0x140>;
539 anatop-vol-bit-shift = <18>;
540 anatop-vol-bit-width = <5>;
541 anatop-delay-reg-offset = <0x170>;
542 anatop-delay-bit-shift = <28>;
543 anatop-delay-bit-width = <2>;
544 anatop-min-bit-val = <1>;
545 anatop-min-voltage = <725000>;
546 anatop-max-voltage = <1450000>;
551 compatible = "fsl,imx6q-tempmon";
552 interrupts = <0 49 0x04>;
553 fsl,tempmon = <&anatop>;
554 fsl,tempmon-data = <&ocotp>;
557 usbphy1: usbphy@020c9000 {
558 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
559 reg = <0x020c9000 0x1000>;
560 interrupts = <0 44 0x04>;
561 clocks = <&clks 182>;
564 usbphy2: usbphy@020ca000 {
565 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
566 reg = <0x020ca000 0x1000>;
567 interrupts = <0 45 0x04>;
568 clocks = <&clks 183>;
572 compatible = "fsl,sec-v4.0-mon", "simple-bus";
573 #address-cells = <1>;
575 ranges = <0 0x020cc000 0x4000>;
578 compatible = "fsl,sec-v4.0-mon-rtc-lp";
580 interrupts = <0 19 0x04 0 20 0x04>;
584 epit1: epit@020d0000 { /* EPIT1 */
585 reg = <0x020d0000 0x4000>;
586 interrupts = <0 56 0x04>;
589 epit2: epit@020d4000 { /* EPIT2 */
590 reg = <0x020d4000 0x4000>;
591 interrupts = <0 57 0x04>;
595 compatible = "fsl,imx6q-src", "fsl,imx51-src";
596 reg = <0x020d8000 0x4000>;
597 interrupts = <0 91 0x04 0 96 0x04>;
602 compatible = "fsl,imx6q-gpc";
603 reg = <0x020dc000 0x4000>;
604 interrupts = <0 89 0x04 0 90 0x04>;
607 gpr: iomuxc-gpr@020e0000 {
608 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
609 reg = <0x020e0000 0x38>;
612 iomuxc: iomuxc@020e0000 {
613 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
614 reg = <0x020e0000 0x4000>;
617 pinctrl_audmux_1: audmux-1 {
619 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
620 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
621 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
622 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
626 pinctrl_audmux_2: audmux-2 {
628 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
629 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
630 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
631 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
635 pinctrl_audmux_3: audmux-3 {
637 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000
638 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
639 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
643 pinctrl_audmux_4: audmux-4 {
645 MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x80000000
646 MX6QDL_PAD_EIM_D25__AUD5_RXC 0x80000000
647 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
651 pinctrl_audmux_5: audmux-5 {
653 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x80000000
654 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x80000000
655 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x80000000
656 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x80000000
662 pinctrl_ecspi1_1: ecspi1grp-1 {
664 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
665 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
666 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
670 pinctrl_ecspi1_2: ecspi1grp-2 {
672 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
673 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
674 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
680 pinctrl_ecspi3_1: ecspi3grp-1 {
682 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
683 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
684 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
690 pinctrl_enet_1: enetgrp-1 {
692 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
693 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
694 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
695 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
696 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
697 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
698 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
699 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
700 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
701 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
702 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
703 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
704 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
705 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
706 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
707 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
711 pinctrl_enet_2: enetgrp-2 {
713 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
714 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
715 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
716 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
717 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
718 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
719 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
720 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
721 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
722 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
723 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
724 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
725 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
726 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
727 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
731 pinctrl_enet_3: enetgrp-3 {
733 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
734 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
735 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
736 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
737 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
738 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
739 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
740 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
741 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
742 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
743 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
744 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
745 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
746 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
747 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
748 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
752 pinctrl_enet_4: enetgrp-4 {
754 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
755 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
756 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
757 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
758 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
759 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
760 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
761 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
762 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
768 pinctrl_esai_1: esaigrp-1 {
770 MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
771 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
772 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
773 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
774 MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
775 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
776 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
777 MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
778 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
782 pinctrl_esai_2: esaigrp-2 {
784 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
785 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
786 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
787 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
788 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
789 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
790 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
791 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
792 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
793 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
799 pinctrl_flexcan1_1: flexcan1grp-1 {
801 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
802 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
806 pinctrl_flexcan1_2: flexcan1grp-2 {
808 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
809 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
813 pinctrl_flexcan1_3: flexcan1grp-3 {
815 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
816 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000
822 pinctrl_flexcan2_1: flexcan2grp-1 {
824 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
825 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
831 pinctrl_gpmi_nand_1: gpmi-nand-1 {
833 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
834 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
835 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
836 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
837 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
838 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
839 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
840 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
841 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
842 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
843 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
844 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
845 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
846 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
847 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
848 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
849 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
854 pinctrl_gpmi_nand_2: gpmi-nand-2 {
856 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
857 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
858 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
859 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
860 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
861 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
862 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
863 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
864 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
865 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
866 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
867 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
868 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
869 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
870 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
871 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
877 pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
879 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
880 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
884 pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
886 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
887 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
891 pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
893 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
894 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
900 pinctrl_hdmi_cec_1: hdmicecgrp-1 {
902 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
906 pinctrl_hdmi_cec_2: hdmicecgrp-2 {
908 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
914 pinctrl_i2c1_1: i2c1grp-1 {
916 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
917 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
921 pinctrl_i2c1_2: i2c1grp-2 {
923 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
924 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
930 pinctrl_i2c2_1: i2c2grp-1 {
932 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
933 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
937 pinctrl_i2c2_2: i2c2grp-2 {
939 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
940 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
944 pinctrl_i2c2_3: i2c2grp-3 {
946 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
947 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
953 pinctrl_i2c3_1: i2c3grp-1 {
955 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
956 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
960 pinctrl_i2c3_2: i2c3grp-2 {
962 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
963 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
967 pinctrl_i2c3_3: i2c3grp-3 {
969 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
970 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
974 pinctrl_i2c3_4: i2c3grp-4 {
976 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
977 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
983 pinctrl_ipu1_1: ipu1grp-1 {
985 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
986 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
987 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
988 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
989 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
990 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
991 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
992 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
993 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
994 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
995 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
996 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
997 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
998 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
999 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
1000 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
1001 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
1002 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
1003 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
1004 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
1005 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
1006 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
1007 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
1008 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
1009 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
1010 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
1011 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
1012 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
1013 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
1017 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
1019 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
1020 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
1021 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
1022 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
1023 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
1024 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
1025 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
1026 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
1027 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
1028 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
1029 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
1030 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
1034 pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
1036 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
1037 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
1038 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
1039 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
1040 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
1041 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
1042 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
1043 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
1044 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
1045 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
1046 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
1047 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
1048 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
1049 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
1050 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
1051 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
1052 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
1053 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
1054 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
1060 pinctrl_mlb_1: mlbgrp-1 {
1062 MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
1063 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
1064 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
1068 pinctrl_mlb_2: mlbgrp-2 {
1070 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
1071 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
1072 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
1078 pinctrl_pwm1_1: pwm1grp-1 {
1080 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
1084 pinctrl_pwm1_2: pwm1grp-2 {
1086 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
1092 pinctrl_pwm2_1: pwm2grp-1 {
1094 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
1100 pinctrl_pwm3_1: pwm3grp-1 {
1102 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
1108 pinctrl_spdif_1: spdifgrp-1 {
1110 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
1114 pinctrl_spdif_2: spdifgrp-2 {
1116 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
1117 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1121 pinctrl_spdif_3: spdifgrp-3 {
1123 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
1129 pinctrl_uart1_1: uart1grp-1 {
1131 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1132 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1136 pinctrl_uart1_2: uart1grp-2 {
1138 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
1139 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
1145 pinctrl_uart2_1: uart2grp-1 {
1147 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
1148 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
1152 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
1154 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
1155 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
1156 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
1157 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
1161 pinctrl_uart2_3: uart2grp-3 {
1163 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
1164 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
1168 pinctrl_uart2_rtscts_3: uart2rtscts-3 {
1170 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
1171 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
1177 pinctrl_uart3_1: uart3grp-1 {
1179 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
1180 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
1181 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
1182 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1186 pinctrl_uart3_2: uart3grp-2 {
1188 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1189 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1190 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
1191 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1195 pinctrl_uart3_3: uart3grp-3 {
1197 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1198 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1202 pinctrl_uart3_rtscts_3: uart3rtscts-3 {
1204 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
1205 MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
1211 pinctrl_uart4_1: uart4grp-1 {
1213 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1214 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1220 pinctrl_uart5_1: uart5grp-1 {
1222 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
1223 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
1229 pinctrl_usbotg_1: usbotggrp-1 {
1231 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
1235 pinctrl_usbotg_2: usbotggrp-2 {
1237 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1243 pinctrl_usbh1_1: usbh1grp-1 {
1245 MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x40013030
1246 MX6QDL_PAD_EIM_D30__USB_H1_OC 0x40013030
1252 pinctrl_usbh2_1: usbh2grp-1 {
1254 MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
1255 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
1259 pinctrl_usbh2_2: usbh2grp-2 {
1261 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
1267 pinctrl_usbh3_1: usbh3grp-1 {
1269 MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
1270 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
1274 pinctrl_usbh3_2: usbh3grp-2 {
1276 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
1282 pinctrl_usdhc1_1: usdhc1grp-1 {
1284 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1285 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1286 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1287 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1288 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1289 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1290 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
1291 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
1292 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
1293 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
1297 pinctrl_usdhc1_2: usdhc1grp-2 {
1299 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1300 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1301 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1302 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1303 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1304 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1310 pinctrl_usdhc2_1: usdhc2grp-1 {
1312 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1313 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1314 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1315 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1316 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1317 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1318 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
1319 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
1320 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
1321 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
1325 pinctrl_usdhc2_2: usdhc2grp-2 {
1327 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1328 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1329 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1330 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1331 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1332 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1338 pinctrl_usdhc3_1: usdhc3grp-1 {
1340 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1341 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1342 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1343 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1344 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1345 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1346 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1347 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1348 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1349 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1353 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */
1355 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
1356 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
1357 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
1358 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
1359 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
1360 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
1361 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
1362 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
1363 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
1364 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
1368 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */
1370 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
1371 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
1372 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
1373 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
1374 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
1375 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
1376 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
1377 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
1378 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
1379 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
1383 pinctrl_usdhc3_2: usdhc3grp-2 {
1385 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1386 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1387 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1388 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1389 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1390 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1396 pinctrl_usdhc4_1: usdhc4grp-1 {
1398 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1399 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1400 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1401 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1402 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1403 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1404 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1405 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1406 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1407 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1411 pinctrl_usdhc4_2: usdhc4grp-2 {
1413 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1414 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1415 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1416 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1417 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1418 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1424 pinctrl_weim_cs0_1: weim_cs0grp-1 {
1426 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
1430 pinctrl_weim_nor_1: weim_norgrp-1 {
1432 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
1433 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
1434 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1436 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1437 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1438 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1439 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1440 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1441 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1442 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1443 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1444 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1445 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1446 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1447 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1448 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1449 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1450 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1451 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1453 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1454 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1455 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1456 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1457 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1458 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1459 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1460 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1461 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
1462 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
1463 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
1464 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
1465 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
1466 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
1467 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
1468 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
1469 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
1470 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
1471 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
1472 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
1473 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
1474 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
1475 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
1476 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
1483 #address-cells = <1>;
1485 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
1487 status = "disabled";
1491 status = "disabled";
1496 status = "disabled";
1500 dcic1: dcic@020e4000 {
1501 reg = <0x020e4000 0x4000>;
1502 interrupts = <0 124 0x04>;
1505 dcic2: dcic@020e8000 {
1506 reg = <0x020e8000 0x4000>;
1507 interrupts = <0 125 0x04>;
1510 sdma: sdma@020ec000 {
1511 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
1512 reg = <0x020ec000 0x4000>;
1513 interrupts = <0 2 0x04>;
1514 clocks = <&clks 155>, <&clks 155>;
1515 clock-names = "ipg", "ahb";
1517 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
1521 aips-bus@02100000 { /* AIPS2 */
1522 compatible = "fsl,aips-bus", "simple-bus";
1523 #address-cells = <1>;
1525 reg = <0x02100000 0x100000>;
1529 reg = <0x02100000 0x40000>;
1530 interrupts = <0 105 0x04 0 106 0x04>;
1533 aipstz@0217c000 { /* AIPSTZ2 */
1534 reg = <0x0217c000 0x4000>;
1537 usbotg: usb@02184000 {
1538 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1539 reg = <0x02184000 0x200>;
1540 interrupts = <0 43 0x04>;
1541 clocks = <&clks 162>;
1542 fsl,usbphy = <&usbphy1>;
1543 fsl,usbmisc = <&usbmisc 0>;
1544 status = "disabled";
1547 usbh1: usb@02184200 {
1548 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1549 reg = <0x02184200 0x200>;
1550 interrupts = <0 40 0x04>;
1551 clocks = <&clks 162>;
1552 fsl,usbphy = <&usbphy2>;
1553 fsl,usbmisc = <&usbmisc 1>;
1554 status = "disabled";
1557 usbh2: usb@02184400 {
1558 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1559 reg = <0x02184400 0x200>;
1560 interrupts = <0 41 0x04>;
1561 clocks = <&clks 162>;
1562 fsl,usbmisc = <&usbmisc 2>;
1563 status = "disabled";
1566 usbh3: usb@02184600 {
1567 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1568 reg = <0x02184600 0x200>;
1569 interrupts = <0 42 0x04>;
1570 clocks = <&clks 162>;
1571 fsl,usbmisc = <&usbmisc 3>;
1572 status = "disabled";
1575 usbmisc: usbmisc@02184800 {
1577 compatible = "fsl,imx6q-usbmisc";
1578 reg = <0x02184800 0x200>;
1579 clocks = <&clks 162>;
1582 fec: ethernet@02188000 {
1583 compatible = "fsl,imx6q-fec";
1584 reg = <0x02188000 0x4000>;
1585 interrupts = <0 118 0x04 0 119 0x04>;
1586 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
1587 clock-names = "ipg", "ahb", "ptp";
1588 status = "disabled";
1592 reg = <0x0218c000 0x4000>;
1593 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
1596 usdhc1: usdhc@02190000 {
1597 compatible = "fsl,imx6q-usdhc";
1598 reg = <0x02190000 0x4000>;
1599 interrupts = <0 22 0x04>;
1600 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
1601 clock-names = "ipg", "ahb", "per";
1603 status = "disabled";
1606 usdhc2: usdhc@02194000 {
1607 compatible = "fsl,imx6q-usdhc";
1608 reg = <0x02194000 0x4000>;
1609 interrupts = <0 23 0x04>;
1610 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
1611 clock-names = "ipg", "ahb", "per";
1613 status = "disabled";
1616 usdhc3: usdhc@02198000 {
1617 compatible = "fsl,imx6q-usdhc";
1618 reg = <0x02198000 0x4000>;
1619 interrupts = <0 24 0x04>;
1620 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
1621 clock-names = "ipg", "ahb", "per";
1623 status = "disabled";
1626 usdhc4: usdhc@0219c000 {
1627 compatible = "fsl,imx6q-usdhc";
1628 reg = <0x0219c000 0x4000>;
1629 interrupts = <0 25 0x04>;
1630 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
1631 clock-names = "ipg", "ahb", "per";
1633 status = "disabled";
1636 i2c1: i2c@021a0000 {
1637 #address-cells = <1>;
1639 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1640 reg = <0x021a0000 0x4000>;
1641 interrupts = <0 36 0x04>;
1642 clocks = <&clks 125>;
1643 status = "disabled";
1646 i2c2: i2c@021a4000 {
1647 #address-cells = <1>;
1649 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1650 reg = <0x021a4000 0x4000>;
1651 interrupts = <0 37 0x04>;
1652 clocks = <&clks 126>;
1653 status = "disabled";
1656 i2c3: i2c@021a8000 {
1657 #address-cells = <1>;
1659 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1660 reg = <0x021a8000 0x4000>;
1661 interrupts = <0 38 0x04>;
1662 clocks = <&clks 127>;
1663 status = "disabled";
1667 reg = <0x021ac000 0x4000>;
1670 mmdc0: mmdc@021b0000 { /* MMDC0 */
1671 compatible = "fsl,imx6q-mmdc";
1672 reg = <0x021b0000 0x4000>;
1675 mmdc1: mmdc@021b4000 { /* MMDC1 */
1676 reg = <0x021b4000 0x4000>;
1679 weim: weim@021b8000 {
1680 compatible = "fsl,imx6q-weim";
1681 reg = <0x021b8000 0x4000>;
1682 interrupts = <0 14 0x04>;
1683 clocks = <&clks 196>;
1686 ocotp: ocotp@021bc000 {
1687 compatible = "fsl,imx6q-ocotp", "syscon";
1688 reg = <0x021bc000 0x4000>;
1691 tzasc@021d0000 { /* TZASC1 */
1692 reg = <0x021d0000 0x4000>;
1693 interrupts = <0 108 0x04>;
1696 tzasc@021d4000 { /* TZASC2 */
1697 reg = <0x021d4000 0x4000>;
1698 interrupts = <0 109 0x04>;
1701 audmux: audmux@021d8000 {
1702 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1703 reg = <0x021d8000 0x4000>;
1704 status = "disabled";
1707 mipi@021dc000 { /* MIPI-CSI */
1708 reg = <0x021dc000 0x4000>;
1711 mipi@021e0000 { /* MIPI-DSI */
1712 reg = <0x021e0000 0x4000>;
1716 reg = <0x021e4000 0x4000>;
1717 interrupts = <0 18 0x04>;
1720 uart2: serial@021e8000 {
1721 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1722 reg = <0x021e8000 0x4000>;
1723 interrupts = <0 27 0x04>;
1724 clocks = <&clks 160>, <&clks 161>;
1725 clock-names = "ipg", "per";
1726 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1727 dma-names = "rx", "tx";
1728 status = "disabled";
1731 uart3: serial@021ec000 {
1732 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1733 reg = <0x021ec000 0x4000>;
1734 interrupts = <0 28 0x04>;
1735 clocks = <&clks 160>, <&clks 161>;
1736 clock-names = "ipg", "per";
1737 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1738 dma-names = "rx", "tx";
1739 status = "disabled";
1742 uart4: serial@021f0000 {
1743 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1744 reg = <0x021f0000 0x4000>;
1745 interrupts = <0 29 0x04>;
1746 clocks = <&clks 160>, <&clks 161>;
1747 clock-names = "ipg", "per";
1748 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1749 dma-names = "rx", "tx";
1750 status = "disabled";
1753 uart5: serial@021f4000 {
1754 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1755 reg = <0x021f4000 0x4000>;
1756 interrupts = <0 30 0x04>;
1757 clocks = <&clks 160>, <&clks 161>;
1758 clock-names = "ipg", "per";
1759 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1760 dma-names = "rx", "tx";
1761 status = "disabled";
1765 ipu1: ipu@02400000 {
1767 compatible = "fsl,imx6q-ipu";
1768 reg = <0x02400000 0x400000>;
1769 interrupts = <0 6 0x4 0 5 0x4>;
1770 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1771 clock-names = "bus", "di0", "di1";