arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/clock/imx6qdl-clock.h>
  14
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         aliases {
  19                 gpio0 = &gpio1;
  20                 gpio1 = &gpio2;
  21                 gpio2 = &gpio3;
  22                 gpio3 = &gpio4;
  23                 gpio4 = &gpio5;
  24                 gpio5 = &gpio6;
  25                 gpio6 = &gpio7;
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 i2c2 = &i2c3;
  29                 ipu0 = &ipu1;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 spi0 = &ecspi1;
  36                 spi1 = &ecspi2;
  37                 spi2 = &ecspi3;
  38                 spi3 = &ecspi4;
  39                 usbphy0 = &usbphy1;
  40                 usbphy1 = &usbphy2;
  41         };
  42
  43         intc: interrupt-controller@00a01000 {
  44                 compatible = "arm,cortex-a9-gic";
  45                 #interrupt-cells = <3>;
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 interrupt-controller;
  49                 reg = <0x00a01000 0x1000>,
  50                       <0x00a00100 0x100>;
  51         };
  52
  53         clocks {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 ckil {
  58                         compatible = "fsl,imx-ckil", "fixed-clock";
  59                         clock-frequency = <32768>;
  60                 };
  61
  62                 ckih1 {
  63                         compatible = "fsl,imx-ckih1", "fixed-clock";
  64                         clock-frequency = <0>;
  65                 };
  66
  67                 osc {
  68                         compatible = "fsl,imx-osc", "fixed-clock";
  69                         clock-frequency = <24000000>;
  70                 };
  71         };
  72
  73         soc {
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 compatible = "simple-bus";
  77                 interrupt-parent = <&intc>;
  78                 ranges;
  79
  80                 dma_apbh: dma-apbh@00110000 {
  81                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  82                         reg = <0x00110000 0x2000>;
  83                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  84                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  85                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  86                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  87                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  88                         #dma-cells = <1>;
  89                         dma-channels = <4>;
  90                         clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
  91                 };
  92
  93                 gpmi: gpmi-nand@00112000 {
  94                         compatible = "fsl,imx6q-gpmi-nand";
  95                         #address-cells = <1>;
  96                         #size-cells = <1>;
  97                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
  98                         reg-names = "gpmi-nand", "bch";
  99                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 100                         interrupt-names = "bch";
 101                         clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
 102                                  <&clks IMX6QDL_CLK_GPMI_APB>,
 103                                  <&clks IMX6QDL_CLK_GPMI_BCH>,
 104                                  <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
 105                                  <&clks IMX6QDL_CLK_PER1_BCH>;
 106                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 107                                       "gpmi_bch_apb", "per1_bch";
 108                         dmas = <&dma_apbh 0>;
 109                         dma-names = "rx-tx";
 110                         status = "disabled";
 111                 };
 112
 113                 timer@00a00600 {
 114                         compatible = "arm,cortex-a9-twd-timer";
 115                         reg = <0x00a00600 0x20>;
 116                         interrupts = <1 13 0xf01>;
 117                         clocks = <&clks IMX6QDL_CLK_TWD>;
 118                 };
 119
 120                 L2: l2-cache@00a02000 {
 121                         compatible = "arm,pl310-cache";
 122                         reg = <0x00a02000 0x1000>;
 123                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 124                         cache-unified;
 125                         cache-level = <2>;
 126                         arm,tag-latency = <4 2 3>;
 127                         arm,data-latency = <4 2 3>;
 128                 };
 129
 130                 pcie: pcie@0x01000000 {
 131                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 132                         reg = <0x01ffc000 0x4000>; /* DBI */
 133                         #address-cells = <3>;
 134                         #size-cells = <2>;
 135                         device_type = "pci";
 136                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 137                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 138                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 139                         num-lanes = <1>;
 140                         interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
 141                         clocks = <&clks IMX6QDL_CLK_PCIE_REF_125M>, <&clks IMX6QDL_CLK_SATA_REF_100M>,
 142                                  <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_AXI>;
 143                         clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
 144                         status = "disabled";
 145                 };
 146
 147                 pmu {
 148                         compatible = "arm,cortex-a9-pmu";
 149                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 150                 };
 151
 152                 aips-bus@02000000 { /* AIPS1 */
 153                         compatible = "fsl,aips-bus", "simple-bus";
 154                         #address-cells = <1>;
 155                         #size-cells = <1>;
 156                         reg = <0x02000000 0x100000>;
 157                         ranges;
 158
 159                         spba-bus@02000000 {
 160                                 compatible = "fsl,spba-bus", "simple-bus";
 161                                 #address-cells = <1>;
 162                                 #size-cells = <1>;
 163                                 reg = <0x02000000 0x40000>;
 164                                 ranges;
 165
 166                                 spdif: spdif@02004000 {
 167                                         compatible = "fsl,imx35-spdif";
 168                                         reg = <0x02004000 0x4000>;
 169                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 170                                         dmas = <&sdma 14 18 0>,
 171                                                <&sdma 15 18 0>;
 172                                         dma-names = "rx", "tx";
 173                                         clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
 174                                                  <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
 175                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI>,
 176                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_MLB>,
 177                                                  <&clks IMX6QDL_CLK_DUMMY>;
 178                                         clock-names = "core",  "rxtx0",
 179                                                       "rxtx1", "rxtx2",
 180                                                       "rxtx3", "rxtx4",
 181                                                       "rxtx5", "rxtx6",
 182                                                       "rxtx7";
 183                                         status = "disabled";
 184                                 };
 185
 186                                 ecspi1: ecspi@02008000 {
 187                                         #address-cells = <1>;
 188                                         #size-cells = <0>;
 189                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 190                                         reg = <0x02008000 0x4000>;
 191                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 192                                         clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 193                                                  <&clks IMX6QDL_CLK_ECSPI1>;
 194                                         clock-names = "ipg", "per";
 195                                         status = "disabled";
 196                                 };
 197
 198                                 ecspi2: ecspi@0200c000 {
 199                                         #address-cells = <1>;
 200                                         #size-cells = <0>;
 201                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 202                                         reg = <0x0200c000 0x4000>;
 203                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 204                                         clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 205                                                  <&clks IMX6QDL_CLK_ECSPI2>;
 206                                         clock-names = "ipg", "per";
 207                                         status = "disabled";
 208                                 };
 209
 210                                 ecspi3: ecspi@02010000 {
 211                                         #address-cells = <1>;
 212                                         #size-cells = <0>;
 213                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 214                                         reg = <0x02010000 0x4000>;
 215                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 216                                         clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 217                                                  <&clks IMX6QDL_CLK_ECSPI3>;
 218                                         clock-names = "ipg", "per";
 219                                         status = "disabled";
 220                                 };
 221
 222                                 ecspi4: ecspi@02014000 {
 223                                         #address-cells = <1>;
 224                                         #size-cells = <0>;
 225                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 226                                         reg = <0x02014000 0x4000>;
 227                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 228                                         clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 229                                                  <&clks IMX6QDL_CLK_ECSPI4>;
 230                                         clock-names = "ipg", "per";
 231                                         status = "disabled";
 232                                 };
 233
 234                                 uart1: serial@02020000 {
 235                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 236                                         reg = <0x02020000 0x4000>;
 237                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 238                                         clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 239                                                  <&clks IMX6QDL_CLK_UART_SERIAL>;
 240                                         clock-names = "ipg", "per";
 241                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 242                                         dma-names = "rx", "tx";
 243                                         status = "disabled";
 244                                 };
 245
 246                                 esai: esai@02024000 {
 247                                         reg = <0x02024000 0x4000>;
 248                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 249                                 };
 250
 251                                 ssi1: ssi@02028000 {
 252                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 253                                         reg = <0x02028000 0x4000>;
 254                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 255                                         clocks = <&clks IMX6QDL_CLK_SSI1_IPG>;
 256                                         dmas = <&sdma 37 1 0>,
 257                                                <&sdma 38 1 0>;
 258                                         dma-names = "rx", "tx";
 259                                         fsl,fifo-depth = <15>;
 260                                         fsl,ssi-dma-events = <38 37>;
 261                                         status = "disabled";
 262                                 };
 263
 264                                 ssi2: ssi@0202c000 {
 265                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 266                                         reg = <0x0202c000 0x4000>;
 267                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 268                                         clocks = <&clks IMX6QDL_CLK_SSI2_IPG>;
 269                                         dmas = <&sdma 41 1 0>,
 270                                                <&sdma 42 1 0>;
 271                                         dma-names = "rx", "tx";
 272                                         fsl,fifo-depth = <15>;
 273                                         fsl,ssi-dma-events = <42 41>;
 274                                         status = "disabled";
 275                                 };
 276
 277                                 ssi3: ssi@02030000 {
 278                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 279                                         reg = <0x02030000 0x4000>;
 280                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 281                                         clocks = <&clks IMX6QDL_CLK_SSI3_IPG>;
 282                                         dmas = <&sdma 45 1 0>,
 283                                                <&sdma 46 1 0>;
 284                                         dma-names = "rx", "tx";
 285                                         fsl,fifo-depth = <15>;
 286                                         fsl,ssi-dma-events = <46 45>;
 287                                         status = "disabled";
 288                                 };
 289
 290                                 asrc: asrc@02034000 {
 291                                         reg = <0x02034000 0x4000>;
 292                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 293                                 };
 294
 295                                 spba@0203c000 {
 296                                         reg = <0x0203c000 0x4000>;
 297                                 };
 298                         };
 299
 300                         vpu: vpu@02040000 {
 301                                 reg = <0x02040000 0x3c000>;
 302                                 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
 303                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
 304                         };
 305
 306                         aipstz@0207c000 { /* AIPSTZ1 */
 307                                 reg = <0x0207c000 0x4000>;
 308                         };
 309
 310                         pwm1: pwm@02080000 {
 311                                 #pwm-cells = <2>;
 312                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 313                                 reg = <0x02080000 0x4000>;
 314                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 315                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 316                                          <&clks IMX6QDL_CLK_PWM1>;
 317                                 clock-names = "ipg", "per";
 318                         };
 319
 320                         pwm2: pwm@02084000 {
 321                                 #pwm-cells = <2>;
 322                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 323                                 reg = <0x02084000 0x4000>;
 324                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 325                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 326                                          <&clks IMX6QDL_CLK_PWM2>;
 327                                 clock-names = "ipg", "per";
 328                         };
 329
 330                         pwm3: pwm@02088000 {
 331                                 #pwm-cells = <2>;
 332                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 333                                 reg = <0x02088000 0x4000>;
 334                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 335                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 336                                          <&clks IMX6QDL_CLK_PWM3>;
 337                                 clock-names = "ipg", "per";
 338                         };
 339
 340                         pwm4: pwm@0208c000 {
 341                                 #pwm-cells = <2>;
 342                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 343                                 reg = <0x0208c000 0x4000>;
 344                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 345                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 346                                          <&clks IMX6QDL_CLK_PWM4>;
 347                                 clock-names = "ipg", "per";
 348                         };
 349
 350                         can1: flexcan@02090000 {
 351                                 compatible = "fsl,imx6q-flexcan";
 352                                 reg = <0x02090000 0x4000>;
 353                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 354                                 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
 355                                          <&clks IMX6QDL_CLK_CAN1_SERIAL>;
 356                                 clock-names = "ipg", "per";
 357                                 status = "disabled";
 358                         };
 359
 360                         can2: flexcan@02094000 {
 361                                 compatible = "fsl,imx6q-flexcan";
 362                                 reg = <0x02094000 0x4000>;
 363                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 364                                 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
 365                                          <&clks IMX6QDL_CLK_CAN2_SERIAL>;
 366                                 clock-names = "ipg", "per";
 367                                 status = "disabled";
 368                         };
 369
 370                         gpt: gpt@02098000 {
 371                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 372                                 reg = <0x02098000 0x4000>;
 373                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 374                                 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
 375                                          <&clks IMX6QDL_CLK_GPT_IPG_PER>;
 376                                 clock-names = "ipg", "per";
 377                         };
 378
 379                         gpio1: gpio@0209c000 {
 380                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 381                                 reg = <0x0209c000 0x4000>;
 382                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 383                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 384                                 gpio-controller;
 385                                 #gpio-cells = <2>;
 386                                 interrupt-controller;
 387                                 #interrupt-cells = <2>;
 388                         };
 389
 390                         gpio2: gpio@020a0000 {
 391                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 392                                 reg = <0x020a0000 0x4000>;
 393                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 394                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 395                                 gpio-controller;
 396                                 #gpio-cells = <2>;
 397                                 interrupt-controller;
 398                                 #interrupt-cells = <2>;
 399                         };
 400
 401                         gpio3: gpio@020a4000 {
 402                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 403                                 reg = <0x020a4000 0x4000>;
 404                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 405                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 406                                 gpio-controller;
 407                                 #gpio-cells = <2>;
 408                                 interrupt-controller;
 409                                 #interrupt-cells = <2>;
 410                         };
 411
 412                         gpio4: gpio@020a8000 {
 413                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 414                                 reg = <0x020a8000 0x4000>;
 415                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 416                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 417                                 gpio-controller;
 418                                 #gpio-cells = <2>;
 419                                 interrupt-controller;
 420                                 #interrupt-cells = <2>;
 421                         };
 422
 423                         gpio5: gpio@020ac000 {
 424                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 425                                 reg = <0x020ac000 0x4000>;
 426                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 427                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 428                                 gpio-controller;
 429                                 #gpio-cells = <2>;
 430                                 interrupt-controller;
 431                                 #interrupt-cells = <2>;
 432                         };
 433
 434                         gpio6: gpio@020b0000 {
 435                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 436                                 reg = <0x020b0000 0x4000>;
 437                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 438                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 439                                 gpio-controller;
 440                                 #gpio-cells = <2>;
 441                                 interrupt-controller;
 442                                 #interrupt-cells = <2>;
 443                         };
 444
 445                         gpio7: gpio@020b4000 {
 446                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 447                                 reg = <0x020b4000 0x4000>;
 448                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 449                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 450                                 gpio-controller;
 451                                 #gpio-cells = <2>;
 452                                 interrupt-controller;
 453                                 #interrupt-cells = <2>;
 454                         };
 455
 456                         kpp: kpp@020b8000 {
 457                                 reg = <0x020b8000 0x4000>;
 458                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 459                         };
 460
 461                         wdog1: wdog@020bc000 {
 462                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 463                                 reg = <0x020bc000 0x4000>;
 464                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 465                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 466                         };
 467
 468                         wdog2: wdog@020c0000 {
 469                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 470                                 reg = <0x020c0000 0x4000>;
 471                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 472                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 473                                 status = "disabled";
 474                         };
 475
 476                         clks: ccm@020c4000 {
 477                                 compatible = "fsl,imx6q-ccm";
 478                                 reg = <0x020c4000 0x4000>;
 479                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 480                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 481                                 #clock-cells = <1>;
 482                         };
 483
 484                         anatop: anatop@020c8000 {
 485                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 486                                 reg = <0x020c8000 0x1000>;
 487                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 488                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 489                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 490
 491                                 regulator-1p1@110 {
 492                                         compatible = "fsl,anatop-regulator";
 493                                         regulator-name = "vdd1p1";
 494                                         regulator-min-microvolt = <800000>;
 495                                         regulator-max-microvolt = <1375000>;
 496                                         regulator-always-on;
 497                                         anatop-reg-offset = <0x110>;
 498                                         anatop-vol-bit-shift = <8>;
 499                                         anatop-vol-bit-width = <5>;
 500                                         anatop-min-bit-val = <4>;
 501                                         anatop-min-voltage = <800000>;
 502                                         anatop-max-voltage = <1375000>;
 503                                 };
 504
 505                                 regulator-3p0@120 {
 506                                         compatible = "fsl,anatop-regulator";
 507                                         regulator-name = "vdd3p0";
 508                                         regulator-min-microvolt = <2800000>;
 509                                         regulator-max-microvolt = <3150000>;
 510                                         regulator-always-on;
 511                                         anatop-reg-offset = <0x120>;
 512                                         anatop-vol-bit-shift = <8>;
 513                                         anatop-vol-bit-width = <5>;
 514                                         anatop-min-bit-val = <0>;
 515                                         anatop-min-voltage = <2625000>;
 516                                         anatop-max-voltage = <3400000>;
 517                                 };
 518
 519                                 regulator-2p5@130 {
 520                                         compatible = "fsl,anatop-regulator";
 521                                         regulator-name = "vdd2p5";
 522                                         regulator-min-microvolt = <2000000>;
 523                                         regulator-max-microvolt = <2750000>;
 524                                         regulator-always-on;
 525                                         anatop-reg-offset = <0x130>;
 526                                         anatop-vol-bit-shift = <8>;
 527                                         anatop-vol-bit-width = <5>;
 528                                         anatop-min-bit-val = <0>;
 529                                         anatop-min-voltage = <2000000>;
 530                                         anatop-max-voltage = <2750000>;
 531                                 };
 532
 533                                 reg_arm: regulator-vddcore@140 {
 534                                         compatible = "fsl,anatop-regulator";
 535                                         regulator-name = "vddarm";
 536                                         regulator-min-microvolt = <725000>;
 537                                         regulator-max-microvolt = <1450000>;
 538                                         regulator-always-on;
 539                                         anatop-reg-offset = <0x140>;
 540                                         anatop-vol-bit-shift = <0>;
 541                                         anatop-vol-bit-width = <5>;
 542                                         anatop-delay-reg-offset = <0x170>;
 543                                         anatop-delay-bit-shift = <24>;
 544                                         anatop-delay-bit-width = <2>;
 545                                         anatop-min-bit-val = <1>;
 546                                         anatop-min-voltage = <725000>;
 547                                         anatop-max-voltage = <1450000>;
 548                                 };
 549
 550                                 reg_pu: regulator-vddpu@140 {
 551                                         compatible = "fsl,anatop-regulator";
 552                                         regulator-name = "vddpu";
 553                                         regulator-min-microvolt = <725000>;
 554                                         regulator-max-microvolt = <1450000>;
 555                                         regulator-always-on;
 556                                         anatop-reg-offset = <0x140>;
 557                                         anatop-vol-bit-shift = <9>;
 558                                         anatop-vol-bit-width = <5>;
 559                                         anatop-delay-reg-offset = <0x170>;
 560                                         anatop-delay-bit-shift = <26>;
 561                                         anatop-delay-bit-width = <2>;
 562                                         anatop-min-bit-val = <1>;
 563                                         anatop-min-voltage = <725000>;
 564                                         anatop-max-voltage = <1450000>;
 565                                 };
 566
 567                                 reg_soc: regulator-vddsoc@140 {
 568                                         compatible = "fsl,anatop-regulator";
 569                                         regulator-name = "vddsoc";
 570                                         regulator-min-microvolt = <725000>;
 571                                         regulator-max-microvolt = <1450000>;
 572                                         regulator-always-on;
 573                                         anatop-reg-offset = <0x140>;
 574                                         anatop-vol-bit-shift = <18>;
 575                                         anatop-vol-bit-width = <5>;
 576                                         anatop-delay-reg-offset = <0x170>;
 577                                         anatop-delay-bit-shift = <28>;
 578                                         anatop-delay-bit-width = <2>;
 579                                         anatop-min-bit-val = <1>;
 580                                         anatop-min-voltage = <725000>;
 581                                         anatop-max-voltage = <1450000>;
 582                                 };
 583                         };
 584
 585                         tempmon: tempmon {
 586                                 compatible = "fsl,imx6q-tempmon";
 587                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 588                                 fsl,tempmon = <&anatop>;
 589                                 fsl,tempmon-data = <&ocotp>;
 590                                 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 591                         };
 592
 593                         usbphy1: usbphy@020c9000 {
 594                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 595                                 reg = <0x020c9000 0x1000>;
 596                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 597                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 598                                 fsl,anatop = <&anatop>;
 599                         };
 600
 601                         usbphy2: usbphy@020ca000 {
 602                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 603                                 reg = <0x020ca000 0x1000>;
 604                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 605                                 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
 606                                 fsl,anatop = <&anatop>;
 607                         };
 608
 609                         snvs@020cc000 {
 610                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 611                                 #address-cells = <1>;
 612                                 #size-cells = <1>;
 613                                 ranges = <0 0x020cc000 0x4000>;
 614
 615                                 snvs-rtc-lp@34 {
 616                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 617                                         reg = <0x34 0x58>;
 618                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 619                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 620                                 };
 621                         };
 622
 623                         epit1: epit@020d0000 { /* EPIT1 */
 624                                 reg = <0x020d0000 0x4000>;
 625                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 626                         };
 627
 628                         epit2: epit@020d4000 { /* EPIT2 */
 629                                 reg = <0x020d4000 0x4000>;
 630                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 631                         };
 632
 633                         src: src@020d8000 {
 634                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 635                                 reg = <0x020d8000 0x4000>;
 636                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 637                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 638                                 #reset-cells = <1>;
 639                         };
 640
 641                         gpc: gpc@020dc000 {
 642                                 compatible = "fsl,imx6q-gpc";
 643                                 reg = <0x020dc000 0x4000>;
 644                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 645                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 646                         };
 647
 648                         gpr: iomuxc-gpr@020e0000 {
 649                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 650                                 reg = <0x020e0000 0x38>;
 651                         };
 652
 653                         iomuxc: iomuxc@020e0000 {
 654                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 655                                 reg = <0x020e0000 0x4000>;
 656                         };
 657
 658                         ldb: ldb@020e0008 {
 659                                 #address-cells = <1>;
 660                                 #size-cells = <0>;
 661                                 gpr = <&gpr>;
 662                                 status = "disabled";
 663
 664                                 lvds-channel@0 {
 665                                         reg = <0>;
 666                                         status = "disabled";
 667                                 };
 668
 669                                 lvds-channel@1 {
 670                                         reg = <1>;
 671                                         status = "disabled";
 672                                 };
 673                         };
 674
 675                         dcic1: dcic@020e4000 {
 676                                 reg = <0x020e4000 0x4000>;
 677                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 678                         };
 679
 680                         dcic2: dcic@020e8000 {
 681                                 reg = <0x020e8000 0x4000>;
 682                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 683                         };
 684
 685                         sdma: sdma@020ec000 {
 686                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 687                                 reg = <0x020ec000 0x4000>;
 688                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 689                                 clocks = <&clks IMX6QDL_CLK_SDMA>,
 690                                          <&clks IMX6QDL_CLK_SDMA>;
 691                                 clock-names = "ipg", "ahb";
 692                                 #dma-cells = <3>;
 693                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 694                         };
 695                 };
 696
 697                 aips-bus@02100000 { /* AIPS2 */
 698                         compatible = "fsl,aips-bus", "simple-bus";
 699                         #address-cells = <1>;
 700                         #size-cells = <1>;
 701                         reg = <0x02100000 0x100000>;
 702                         ranges;
 703
 704                         caam@02100000 {
 705                                 reg = <0x02100000 0x40000>;
 706                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 707                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 708                         };
 709
 710                         aipstz@0217c000 { /* AIPSTZ2 */
 711                                 reg = <0x0217c000 0x4000>;
 712                         };
 713
 714                         usbotg: usb@02184000 {
 715                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 716                                 reg = <0x02184000 0x200>;
 717                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 718                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 719                                 fsl,usbphy = <&usbphy1>;
 720                                 fsl,usbmisc = <&usbmisc 0>;
 721                                 status = "disabled";
 722                         };
 723
 724                         usbh1: usb@02184200 {
 725                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 726                                 reg = <0x02184200 0x200>;
 727                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 728                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 729                                 fsl,usbphy = <&usbphy2>;
 730                                 fsl,usbmisc = <&usbmisc 1>;
 731                                 status = "disabled";
 732                         };
 733
 734                         usbh2: usb@02184400 {
 735                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 736                                 reg = <0x02184400 0x200>;
 737                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 738                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 739                                 fsl,usbmisc = <&usbmisc 2>;
 740                                 status = "disabled";
 741                         };
 742
 743                         usbh3: usb@02184600 {
 744                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 745                                 reg = <0x02184600 0x200>;
 746                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 747                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 748                                 fsl,usbmisc = <&usbmisc 3>;
 749                                 status = "disabled";
 750                         };
 751
 752                         usbmisc: usbmisc@02184800 {
 753                                 #index-cells = <1>;
 754                                 compatible = "fsl,imx6q-usbmisc";
 755                                 reg = <0x02184800 0x200>;
 756                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 757                         };
 758
 759                         fec: ethernet@02188000 {
 760                                 compatible = "fsl,imx6q-fec";
 761                                 reg = <0x02188000 0x4000>;
 762                                 interrupts-extended =
 763                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 764                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 765                                 clocks = <&clks IMX6QDL_CLK_ENET>,
 766                                          <&clks IMX6QDL_CLK_ENET>,
 767                                          <&clks IMX6QDL_CLK_ENET_REF>;
 768                                 clock-names = "ipg", "ahb", "ptp";
 769                                 status = "disabled";
 770                         };
 771
 772                         mlb@0218c000 {
 773                                 reg = <0x0218c000 0x4000>;
 774                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 775                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 776                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 777                         };
 778
 779                         usdhc1: usdhc@02190000 {
 780                                 compatible = "fsl,imx6q-usdhc";
 781                                 reg = <0x02190000 0x4000>;
 782                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 783                                 clocks = <&clks IMX6QDL_CLK_USDHC1>,
 784                                          <&clks IMX6QDL_CLK_USDHC1>,
 785                                          <&clks IMX6QDL_CLK_USDHC1>;
 786                                 clock-names = "ipg", "ahb", "per";
 787                                 bus-width = <4>;
 788                                 status = "disabled";
 789                         };
 790
 791                         usdhc2: usdhc@02194000 {
 792                                 compatible = "fsl,imx6q-usdhc";
 793                                 reg = <0x02194000 0x4000>;
 794                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 795                                 clocks = <&clks IMX6QDL_CLK_USDHC2>,
 796                                          <&clks IMX6QDL_CLK_USDHC2>,
 797                                          <&clks IMX6QDL_CLK_USDHC2>;
 798                                 clock-names = "ipg", "ahb", "per";
 799                                 bus-width = <4>;
 800                                 status = "disabled";
 801                         };
 802
 803                         usdhc3: usdhc@02198000 {
 804                                 compatible = "fsl,imx6q-usdhc";
 805                                 reg = <0x02198000 0x4000>;
 806                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 807                                 clocks = <&clks IMX6QDL_CLK_USDHC3>,
 808                                          <&clks IMX6QDL_CLK_USDHC3>,
 809                                          <&clks IMX6QDL_CLK_USDHC3>;
 810                                 clock-names = "ipg", "ahb", "per";
 811                                 bus-width = <4>;
 812                                 status = "disabled";
 813                         };
 814
 815                         usdhc4: usdhc@0219c000 {
 816                                 compatible = "fsl,imx6q-usdhc";
 817                                 reg = <0x0219c000 0x4000>;
 818                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 819                                 clocks = <&clks IMX6QDL_CLK_USDHC4>,
 820                                          <&clks IMX6QDL_CLK_USDHC4>,
 821                                          <&clks IMX6QDL_CLK_USDHC4>;
 822                                 clock-names = "ipg", "ahb", "per";
 823                                 bus-width = <4>;
 824                                 status = "disabled";
 825                         };
 826
 827                         i2c1: i2c@021a0000 {
 828                                 #address-cells = <1>;
 829                                 #size-cells = <0>;
 830                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 831                                 reg = <0x021a0000 0x4000>;
 832                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 833                                 clocks = <&clks IMX6QDL_CLK_I2C1>;
 834                                 status = "disabled";
 835                         };
 836
 837                         i2c2: i2c@021a4000 {
 838                                 #address-cells = <1>;
 839                                 #size-cells = <0>;
 840                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 841                                 reg = <0x021a4000 0x4000>;
 842                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 843                                 clocks = <&clks IMX6QDL_CLK_I2C2>;
 844                                 status = "disabled";
 845                         };
 846
 847                         i2c3: i2c@021a8000 {
 848                                 #address-cells = <1>;
 849                                 #size-cells = <0>;
 850                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 851                                 reg = <0x021a8000 0x4000>;
 852                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 853                                 clocks = <&clks IMX6QDL_CLK_I2C3>;
 854                                 status = "disabled";
 855                         };
 856
 857                         romcp@021ac000 {
 858                                 reg = <0x021ac000 0x4000>;
 859                         };
 860
 861                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 862                                 compatible = "fsl,imx6q-mmdc";
 863                                 reg = <0x021b0000 0x4000>;
 864                         };
 865
 866                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 867                                 reg = <0x021b4000 0x4000>;
 868                         };
 869
 870                         weim: weim@021b8000 {
 871                                 compatible = "fsl,imx6q-weim";
 872                                 reg = <0x021b8000 0x4000>;
 873                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 874                                 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
 875                         };
 876
 877                         ocotp: ocotp@021bc000 {
 878                                 compatible = "fsl,imx6q-ocotp", "syscon";
 879                                 reg = <0x021bc000 0x4000>;
 880                         };
 881
 882                         tzasc@021d0000 { /* TZASC1 */
 883                                 reg = <0x021d0000 0x4000>;
 884                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 885                         };
 886
 887                         tzasc@021d4000 { /* TZASC2 */
 888                                 reg = <0x021d4000 0x4000>;
 889                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 890                         };
 891
 892                         audmux: audmux@021d8000 {
 893                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 894                                 reg = <0x021d8000 0x4000>;
 895                                 status = "disabled";
 896                         };
 897
 898                         mipi@021dc000 { /* MIPI-CSI */
 899                                 reg = <0x021dc000 0x4000>;
 900                         };
 901
 902                         mipi@021e0000 { /* MIPI-DSI */
 903                                 reg = <0x021e0000 0x4000>;
 904                         };
 905
 906                         vdoa@021e4000 {
 907                                 reg = <0x021e4000 0x4000>;
 908                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 909                         };
 910
 911                         uart2: serial@021e8000 {
 912                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 913                                 reg = <0x021e8000 0x4000>;
 914                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 915                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 916                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
 917                                 clock-names = "ipg", "per";
 918                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 919                                 dma-names = "rx", "tx";
 920                                 status = "disabled";
 921                         };
 922
 923                         uart3: serial@021ec000 {
 924                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 925                                 reg = <0x021ec000 0x4000>;
 926                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 927                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 928                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
 929                                 clock-names = "ipg", "per";
 930                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 931                                 dma-names = "rx", "tx";
 932                                 status = "disabled";
 933                         };
 934
 935                         uart4: serial@021f0000 {
 936                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 937                                 reg = <0x021f0000 0x4000>;
 938                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 939                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 940                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
 941                                 clock-names = "ipg", "per";
 942                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 943                                 dma-names = "rx", "tx";
 944                                 status = "disabled";
 945                         };
 946
 947                         uart5: serial@021f4000 {
 948                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 949                                 reg = <0x021f4000 0x4000>;
 950                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 951                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 952                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
 953                                 clock-names = "ipg", "per";
 954                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 955                                 dma-names = "rx", "tx";
 956                                 status = "disabled";
 957                         };
 958                 };
 959
 960                 ipu1: ipu@02400000 {
 961                         compatible = "fsl,imx6q-ipu";
 962                         reg = <0x02400000 0x400000>;
 963                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
 964                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
 965                         clocks = <&clks IMX6QDL_CLK_IPU1>,
 966                                  <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
 967                                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 968                                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI0>;
 969                         clock-names = "bus",
 970                                       "di0", "di1",
 971                                       "di0_sel", "di1_sel",
 972                                       "ldb_di0", "ldb_di1";
 973                         resets = <&src 2>;
 974                         bypass_reset = <0>;
 975                 };
 976         };
 977 };