arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         aliases {
  19                 ethernet0 = &fec;
  20                 can0 = &can1;
  21                 can1 = &can2;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 gpio6 = &gpio7;
  29                 i2c0 = &i2c1;
  30                 i2c1 = &i2c2;
  31                 i2c2 = &i2c3;
  32                 mmc0 = &usdhc1;
  33                 mmc1 = &usdhc2;
  34                 mmc2 = &usdhc3;
  35                 mmc3 = &usdhc4;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 serial4 = &uart5;
  41                 spi0 = &ecspi1;
  42                 spi1 = &ecspi2;
  43                 spi2 = &ecspi3;
  44                 spi3 = &ecspi4;
  45                 usbphy0 = &usbphy1;
  46                 usbphy1 = &usbphy2;
  47         };
  48
  49         intc: interrupt-controller@00a01000 {
  50                 compatible = "arm,cortex-a9-gic";
  51                 #interrupt-cells = <3>;
  52                 interrupt-controller;
  53                 reg = <0x00a01000 0x1000>,
  54                       <0x00a00100 0x100>;
  55         };
  56
  57         clocks {
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60
  61                 ckil {
  62                         compatible = "fsl,imx-ckil", "fixed-clock";
  63                         #clock-cells = <0>;
  64                         clock-frequency = <32768>;
  65                 };
  66
  67                 ckih1 {
  68                         compatible = "fsl,imx-ckih1", "fixed-clock";
  69                         #clock-cells = <0>;
  70                         clock-frequency = <0>;
  71                 };
  72
  73                 osc {
  74                         compatible = "fsl,imx-osc", "fixed-clock";
  75                         #clock-cells = <0>;
  76                         clock-frequency = <24000000>;
  77                 };
  78         };
  79
  80         soc {
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 compatible = "simple-bus";
  84                 interrupt-parent = <&intc>;
  85                 ranges;
  86
  87                 dma_apbh: dma-apbh@00110000 {
  88                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  89                         reg = <0x00110000 0x2000>;
  90                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  91                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  94                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  95                         #dma-cells = <1>;
  96                         dma-channels = <4>;
  97                         clocks = <&clks 106>;
  98                 };
  99
 100                 gpmi: gpmi-nand@00112000 {
 101                         compatible = "fsl,imx6q-gpmi-nand";
 102                         #address-cells = <1>;
 103                         #size-cells = <1>;
 104                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 105                         reg-names = "gpmi-nand", "bch";
 106                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 107                         interrupt-names = "bch";
 108                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
 109                                  <&clks 150>, <&clks 149>;
 110                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 111                                       "gpmi_bch_apb", "per1_bch";
 112                         dmas = <&dma_apbh 0>;
 113                         dma-names = "rx-tx";
 114                         status = "disabled";
 115                 };
 116
 117                 timer@00a00600 {
 118                         compatible = "arm,cortex-a9-twd-timer";
 119                         reg = <0x00a00600 0x20>;
 120                         interrupts = <1 13 0xf01>;
 121                         clocks = <&clks 15>;
 122                 };
 123
 124                 L2: l2-cache@00a02000 {
 125                         compatible = "arm,pl310-cache";
 126                         reg = <0x00a02000 0x1000>;
 127                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 128                         cache-unified;
 129                         cache-level = <2>;
 130                         arm,tag-latency = <4 2 3>;
 131                         arm,data-latency = <4 2 3>;
 132                 };
 133
 134                 pcie: pcie@0x01000000 {
 135                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 136                         reg = <0x01ffc000 0x4000>; /* DBI */
 137                         #address-cells = <3>;
 138                         #size-cells = <2>;
 139                         device_type = "pci";
 140                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 141                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 142                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 143                         num-lanes = <1>;
 144                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 145                         interrupt-names = "msi";
 146                         #interrupt-cells = <1>;
 147                         interrupt-map-mask = <0 0 0 0x7>;
 148                         interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 149                                         <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 150                                         <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 151                                         <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 152                         clocks = <&clks 144>, <&clks 206>, <&clks 189>;
 153                         clock-names = "pcie", "pcie_bus", "pcie_phy";
 154                         status = "disabled";
 155                 };
 156
 157                 pmu {
 158                         compatible = "arm,cortex-a9-pmu";
 159                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 160                 };
 161
 162                 aips-bus@02000000 { /* AIPS1 */
 163                         compatible = "fsl,aips-bus", "simple-bus";
 164                         #address-cells = <1>;
 165                         #size-cells = <1>;
 166                         reg = <0x02000000 0x100000>;
 167                         ranges;
 168
 169                         spba-bus@02000000 {
 170                                 compatible = "fsl,spba-bus", "simple-bus";
 171                                 #address-cells = <1>;
 172                                 #size-cells = <1>;
 173                                 reg = <0x02000000 0x40000>;
 174                                 ranges;
 175
 176                                 spdif: spdif@02004000 {
 177                                         compatible = "fsl,imx35-spdif";
 178                                         reg = <0x02004000 0x4000>;
 179                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 180                                         dmas = <&sdma 14 18 0>,
 181                                                <&sdma 15 18 0>;
 182                                         dma-names = "rx", "tx";
 183                                         clocks = <&clks 197>, <&clks 3>,
 184                                                  <&clks 197>, <&clks 107>,
 185                                                  <&clks 0>,   <&clks 118>,
 186                                                  <&clks 0>,  <&clks 139>,
 187                                                  <&clks 0>;
 188                                         clock-names = "core",  "rxtx0",
 189                                                       "rxtx1", "rxtx2",
 190                                                       "rxtx3", "rxtx4",
 191                                                       "rxtx5", "rxtx6",
 192                                                       "rxtx7";
 193                                         status = "disabled";
 194                                 };
 195
 196                                 ecspi1: ecspi@02008000 {
 197                                         #address-cells = <1>;
 198                                         #size-cells = <0>;
 199                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 200                                         reg = <0x02008000 0x4000>;
 201                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 202                                         clocks = <&clks 112>, <&clks 112>;
 203                                         clock-names = "ipg", "per";
 204                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 205                                         dma-names = "rx", "tx";
 206                                         status = "disabled";
 207                                 };
 208
 209                                 ecspi2: ecspi@0200c000 {
 210                                         #address-cells = <1>;
 211                                         #size-cells = <0>;
 212                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 213                                         reg = <0x0200c000 0x4000>;
 214                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 215                                         clocks = <&clks 113>, <&clks 113>;
 216                                         clock-names = "ipg", "per";
 217                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 218                                         dma-names = "rx", "tx";
 219                                         status = "disabled";
 220                                 };
 221
 222                                 ecspi3: ecspi@02010000 {
 223                                         #address-cells = <1>;
 224                                         #size-cells = <0>;
 225                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 226                                         reg = <0x02010000 0x4000>;
 227                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 228                                         clocks = <&clks 114>, <&clks 114>;
 229                                         clock-names = "ipg", "per";
 230                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 231                                         dma-names = "rx", "tx";
 232                                         status = "disabled";
 233                                 };
 234
 235                                 ecspi4: ecspi@02014000 {
 236                                         #address-cells = <1>;
 237                                         #size-cells = <0>;
 238                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 239                                         reg = <0x02014000 0x4000>;
 240                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 241                                         clocks = <&clks 115>, <&clks 115>;
 242                                         clock-names = "ipg", "per";
 243                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 244                                         dma-names = "rx", "tx";
 245                                         status = "disabled";
 246                                 };
 247
 248                                 uart1: serial@02020000 {
 249                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 250                                         reg = <0x02020000 0x4000>;
 251                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 252                                         clocks = <&clks 160>, <&clks 161>;
 253                                         clock-names = "ipg", "per";
 254                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 255                                         dma-names = "rx", "tx";
 256                                         status = "disabled";
 257                                 };
 258
 259                                 esai: esai@02024000 {
 260                                         reg = <0x02024000 0x4000>;
 261                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 262                                 };
 263
 264                                 ssi1: ssi@02028000 {
 265                                         compatible = "fsl,imx6q-ssi",
 266                                                         "fsl,imx51-ssi",
 267                                                         "fsl,imx21-ssi";
 268                                         reg = <0x02028000 0x4000>;
 269                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 270                                         clocks = <&clks 178>;
 271                                         dmas = <&sdma 37 1 0>,
 272                                                <&sdma 38 1 0>;
 273                                         dma-names = "rx", "tx";
 274                                         fsl,fifo-depth = <15>;
 275                                         fsl,ssi-dma-events = <38 37>;
 276                                         status = "disabled";
 277                                 };
 278
 279                                 ssi2: ssi@0202c000 {
 280                                         compatible = "fsl,imx6q-ssi",
 281                                                         "fsl,imx51-ssi",
 282                                                         "fsl,imx21-ssi";
 283                                         reg = <0x0202c000 0x4000>;
 284                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 285                                         clocks = <&clks 179>;
 286                                         dmas = <&sdma 41 1 0>,
 287                                                <&sdma 42 1 0>;
 288                                         dma-names = "rx", "tx";
 289                                         fsl,fifo-depth = <15>;
 290                                         fsl,ssi-dma-events = <42 41>;
 291                                         status = "disabled";
 292                                 };
 293
 294                                 ssi3: ssi@02030000 {
 295                                         compatible = "fsl,imx6q-ssi",
 296                                                         "fsl,imx51-ssi",
 297                                                         "fsl,imx21-ssi";
 298                                         reg = <0x02030000 0x4000>;
 299                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 300                                         clocks = <&clks 180>;
 301                                         dmas = <&sdma 45 1 0>,
 302                                                <&sdma 46 1 0>;
 303                                         dma-names = "rx", "tx";
 304                                         fsl,fifo-depth = <15>;
 305                                         fsl,ssi-dma-events = <46 45>;
 306                                         status = "disabled";
 307                                 };
 308
 309                                 asrc: asrc@02034000 {
 310                                         compatible = "fsl,imx6q-asrc";
 311                                         reg = <0x02034000 0x4000>;
 312                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 313                                         clocks = <&clks 107>;
 314                                         clock-names = "core";
 315                                         dmas = <&sdma 17 20 0>, <&sdma 18 20 0>, <&sdma 19 20 0>,
 316                                              <&sdma 20 20 0>, <&sdma 21 20 0>, <&sdma 22 20 0>;
 317                                         dma-names = "rxa", "rxb", "rxc",
 318                                                 "txa", "txb", "txc";
 319                                         fsl,clk-map-version = <2>;
 320                                         fsl,clk-channel-bits = <4>;
 321                                         status = "okay";
 322                                 };
 323
 324                                 spba@0203c000 {
 325                                         reg = <0x0203c000 0x4000>;
 326                                 };
 327                         };
 328
 329                         vpu: vpu@02040000 {
 330                                 compatible = "fsl,imx6-vpu";
 331                                 reg = <0x02040000 0x3c000>;
 332                                 reg-names = "vpu_regs";
 333                                 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
 334                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
 335                                 clocks = <&clks 168>, <&clks 140>, <&clks 142>;
 336                                 clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
 337                                 iramsize = <0x21000>;
 338                                 iram = <&ocram>;
 339                                 resets = <&src 1>;
 340                                 status = "disabled";
 341                         };
 342
 343                         aipstz@0207c000 { /* AIPSTZ1 */
 344                                 reg = <0x0207c000 0x4000>;
 345                         };
 346
 347                         pwm1: pwm@02080000 {
 348                                 #pwm-cells = <2>;
 349                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 350                                 reg = <0x02080000 0x4000>;
 351                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 352                                 clocks = <&clks 62>, <&clks 145>;
 353                                 clock-names = "ipg", "per";
 354                         };
 355
 356                         pwm2: pwm@02084000 {
 357                                 #pwm-cells = <2>;
 358                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 359                                 reg = <0x02084000 0x4000>;
 360                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 361                                 clocks = <&clks 62>, <&clks 146>;
 362                                 clock-names = "ipg", "per";
 363                         };
 364
 365                         pwm3: pwm@02088000 {
 366                                 #pwm-cells = <2>;
 367                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 368                                 reg = <0x02088000 0x4000>;
 369                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 370                                 clocks = <&clks 62>, <&clks 147>;
 371                                 clock-names = "ipg", "per";
 372                         };
 373
 374                         pwm4: pwm@0208c000 {
 375                                 #pwm-cells = <2>;
 376                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 377                                 reg = <0x0208c000 0x4000>;
 378                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 379                                 clocks = <&clks 62>, <&clks 148>;
 380                                 clock-names = "ipg", "per";
 381                         };
 382
 383                         can1: flexcan@02090000 {
 384                                 compatible = "fsl,imx6q-flexcan";
 385                                 reg = <0x02090000 0x4000>;
 386                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 387                                 clocks = <&clks 108>, <&clks 109>;
 388                                 clock-names = "ipg", "per";
 389                                 status = "disabled";
 390                         };
 391
 392                         can2: flexcan@02094000 {
 393                                 compatible = "fsl,imx6q-flexcan";
 394                                 reg = <0x02094000 0x4000>;
 395                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 396                                 clocks = <&clks 110>, <&clks 111>;
 397                                 clock-names = "ipg", "per";
 398                                 status = "disabled";
 399                         };
 400
 401                         gpt: gpt@02098000 {
 402                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 403                                 reg = <0x02098000 0x4000>;
 404                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 405                                 clocks = <&clks 119>, <&clks 120>;
 406                                 clock-names = "ipg", "per";
 407                         };
 408
 409                         gpio1: gpio@0209c000 {
 410                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 411                                 reg = <0x0209c000 0x4000>;
 412                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 413                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 414                                 gpio-controller;
 415                                 #gpio-cells = <2>;
 416                                 interrupt-controller;
 417                                 #interrupt-cells = <2>;
 418                         };
 419
 420                         gpio2: gpio@020a0000 {
 421                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 422                                 reg = <0x020a0000 0x4000>;
 423                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 424                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 425                                 gpio-controller;
 426                                 #gpio-cells = <2>;
 427                                 interrupt-controller;
 428                                 #interrupt-cells = <2>;
 429                         };
 430
 431                         gpio3: gpio@020a4000 {
 432                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 433                                 reg = <0x020a4000 0x4000>;
 434                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 435                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 436                                 gpio-controller;
 437                                 #gpio-cells = <2>;
 438                                 interrupt-controller;
 439                                 #interrupt-cells = <2>;
 440                         };
 441
 442                         gpio4: gpio@020a8000 {
 443                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 444                                 reg = <0x020a8000 0x4000>;
 445                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 446                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 447                                 gpio-controller;
 448                                 #gpio-cells = <2>;
 449                                 interrupt-controller;
 450                                 #interrupt-cells = <2>;
 451                         };
 452
 453                         gpio5: gpio@020ac000 {
 454                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 455                                 reg = <0x020ac000 0x4000>;
 456                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 457                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 458                                 gpio-controller;
 459                                 #gpio-cells = <2>;
 460                                 interrupt-controller;
 461                                 #interrupt-cells = <2>;
 462                         };
 463
 464                         gpio6: gpio@020b0000 {
 465                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 466                                 reg = <0x020b0000 0x4000>;
 467                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 468                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 469                                 gpio-controller;
 470                                 #gpio-cells = <2>;
 471                                 interrupt-controller;
 472                                 #interrupt-cells = <2>;
 473                         };
 474
 475                         gpio7: gpio@020b4000 {
 476                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 477                                 reg = <0x020b4000 0x4000>;
 478                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 479                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 480                                 gpio-controller;
 481                                 #gpio-cells = <2>;
 482                                 interrupt-controller;
 483                                 #interrupt-cells = <2>;
 484                         };
 485
 486                         kpp: kpp@020b8000 {
 487                                 reg = <0x020b8000 0x4000>;
 488                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 489                         };
 490
 491                         wdog1: wdog@020bc000 {
 492                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 493                                 reg = <0x020bc000 0x4000>;
 494                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 495                                 clocks = <&clks 0>;
 496                         };
 497
 498                         wdog2: wdog@020c0000 {
 499                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 500                                 reg = <0x020c0000 0x4000>;
 501                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 502                                 clocks = <&clks 0>;
 503                                 status = "disabled";
 504                         };
 505
 506                         clks: ccm@020c4000 {
 507                                 compatible = "fsl,imx6q-ccm";
 508                                 reg = <0x020c4000 0x4000>;
 509                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 510                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 511                                 #clock-cells = <1>;
 512                         };
 513
 514                         anatop: anatop@020c8000 {
 515                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 516                                 reg = <0x020c8000 0x1000>;
 517                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 518                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 519                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 520
 521                                 regulator-1p1@110 {
 522                                         compatible = "fsl,anatop-regulator";
 523                                         regulator-name = "vdd1p1";
 524                                         regulator-min-microvolt = <800000>;
 525                                         regulator-max-microvolt = <1375000>;
 526                                         regulator-always-on;
 527                                         anatop-reg-offset = <0x110>;
 528                                         anatop-vol-bit-shift = <8>;
 529                                         anatop-vol-bit-width = <5>;
 530                                         anatop-min-bit-val = <4>;
 531                                         anatop-min-voltage = <800000>;
 532                                         anatop-max-voltage = <1375000>;
 533                                 };
 534
 535                                 regulator-3p0@120 {
 536                                         compatible = "fsl,anatop-regulator";
 537                                         regulator-name = "vdd3p0";
 538                                         regulator-min-microvolt = <2800000>;
 539                                         regulator-max-microvolt = <3150000>;
 540                                         regulator-always-on;
 541                                         anatop-reg-offset = <0x120>;
 542                                         anatop-vol-bit-shift = <8>;
 543                                         anatop-vol-bit-width = <5>;
 544                                         anatop-min-bit-val = <0>;
 545                                         anatop-min-voltage = <2625000>;
 546                                         anatop-max-voltage = <3400000>;
 547                                 };
 548
 549                                 regulator-2p5@130 {
 550                                         compatible = "fsl,anatop-regulator";
 551                                         regulator-name = "vdd2p5";
 552                                         regulator-min-microvolt = <2000000>;
 553                                         regulator-max-microvolt = <2750000>;
 554                                         regulator-always-on;
 555                                         anatop-reg-offset = <0x130>;
 556                                         anatop-vol-bit-shift = <8>;
 557                                         anatop-vol-bit-width = <5>;
 558                                         anatop-min-bit-val = <0>;
 559                                         anatop-min-voltage = <2000000>;
 560                                         anatop-max-voltage = <2750000>;
 561                                 };
 562
 563                                 reg_arm: regulator-vddcore@140 {
 564                                         compatible = "fsl,anatop-regulator";
 565                                         regulator-name = "vddarm";
 566                                         regulator-min-microvolt = <725000>;
 567                                         regulator-max-microvolt = <1450000>;
 568                                         regulator-always-on;
 569                                         anatop-reg-offset = <0x140>;
 570                                         anatop-vol-bit-shift = <0>;
 571                                         anatop-vol-bit-width = <5>;
 572                                         anatop-delay-reg-offset = <0x170>;
 573                                         anatop-delay-bit-shift = <24>;
 574                                         anatop-delay-bit-width = <2>;
 575                                         anatop-min-bit-val = <1>;
 576                                         anatop-min-voltage = <725000>;
 577                                         anatop-max-voltage = <1450000>;
 578                                 };
 579
 580                                 reg_pu: regulator-vddpu@140 {
 581                                         compatible = "fsl,anatop-regulator";
 582                                         regulator-name = "vddpu";
 583                                         regulator-min-microvolt = <725000>;
 584                                         regulator-max-microvolt = <1450000>;
 585                                         anatop-reg-offset = <0x140>;
 586                                         anatop-vol-bit-shift = <9>;
 587                                         anatop-vol-bit-width = <5>;
 588                                         anatop-delay-reg-offset = <0x170>;
 589                                         anatop-delay-bit-shift = <26>;
 590                                         anatop-delay-bit-width = <2>;
 591                                         anatop-min-bit-val = <1>;
 592                                         anatop-min-voltage = <725000>;
 593                                         anatop-max-voltage = <1450000>;
 594                                 };
 595
 596                                 reg_soc: regulator-vddsoc@140 {
 597                                         compatible = "fsl,anatop-regulator";
 598                                         regulator-name = "vddsoc";
 599                                         regulator-min-microvolt = <725000>;
 600                                         regulator-max-microvolt = <1450000>;
 601                                         regulator-always-on;
 602                                         anatop-reg-offset = <0x140>;
 603                                         anatop-vol-bit-shift = <18>;
 604                                         anatop-vol-bit-width = <5>;
 605                                         anatop-delay-reg-offset = <0x170>;
 606                                         anatop-delay-bit-shift = <28>;
 607                                         anatop-delay-bit-width = <2>;
 608                                         anatop-min-bit-val = <1>;
 609                                         anatop-min-voltage = <725000>;
 610                                         anatop-max-voltage = <1450000>;
 611                                 };
 612                         };
 613
 614                         tempmon: tempmon {
 615                                 compatible = "fsl,imx6q-tempmon";
 616                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 617                                 fsl,tempmon = <&anatop>;
 618                                 fsl,tempmon-data = <&ocotp>;
 619                                 clocks = <&clks 172>;
 620                         };
 621
 622                         usbphy1: usbphy@020c9000 {
 623                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 624                                 reg = <0x020c9000 0x1000>;
 625                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 626                                 clocks = <&clks 182>;
 627                                 fsl,anatop = <&anatop>;
 628                         };
 629
 630                         usbphy2: usbphy@020ca000 {
 631                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 632                                 reg = <0x020ca000 0x1000>;
 633                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 634                                 clocks = <&clks 183>;
 635                                 fsl,anatop = <&anatop>;
 636                         };
 637
 638                         snvs@020cc000 {
 639                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 640                                 #address-cells = <1>;
 641                                 #size-cells = <1>;
 642                                 ranges = <0 0x020cc000 0x4000>;
 643
 644                                 snvs-rtc-lp@34 {
 645                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 646                                         reg = <0x34 0x58>;
 647                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 648                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 649                                 };
 650                         };
 651
 652                         epit1: epit@020d0000 { /* EPIT1 */
 653                                 reg = <0x020d0000 0x4000>;
 654                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 655                         };
 656
 657                         epit2: epit@020d4000 { /* EPIT2 */
 658                                 reg = <0x020d4000 0x4000>;
 659                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 660                         };
 661
 662                         src: src@020d8000 {
 663                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 664                                 reg = <0x020d8000 0x4000>;
 665                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 666                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 667                                 #reset-cells = <1>;
 668                         };
 669
 670                         gpc: gpc@020dc000 {
 671                                 compatible = "fsl,imx6q-gpc";
 672                                 reg = <0x020dc000 0x4000>;
 673                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 674                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 675                         };
 676
 677                         gpr: iomuxc-gpr@020e0000 {
 678                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 679                                 reg = <0x020e0000 0x38>;
 680                         };
 681
 682                         iomuxc: iomuxc@020e0000 {
 683                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 684                                 reg = <0x020e0000 0x4000>;
 685                         };
 686
 687                         ldb: ldb@020e0008 {
 688                                 #address-cells = <1>;
 689                                 #size-cells = <0>;
 690                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 691                                 gpr = <&gpr>;
 692                                 status = "disabled";
 693
 694                                 lvds-channel@0 {
 695                                         #address-cells = <1>;
 696                                         #size-cells = <0>;
 697                                         reg = <0>;
 698                                         status = "disabled";
 699
 700                                         port@0 {
 701                                                 reg = <0>;
 702
 703                                                 lvds0_mux_0: endpoint {
 704                                                         remote-endpoint = <&ipu1_di0_lvds0>;
 705                                                 };
 706                                         };
 707
 708                                         port@1 {
 709                                                 reg = <1>;
 710
 711                                                 lvds0_mux_1: endpoint {
 712                                                         remote-endpoint = <&ipu1_di1_lvds0>;
 713                                                 };
 714                                         };
 715                                 };
 716
 717                                 lvds-channel@1 {
 718                                         #address-cells = <1>;
 719                                         #size-cells = <0>;
 720                                         reg = <1>;
 721                                         status = "disabled";
 722
 723                                         port@0 {
 724                                                 reg = <0>;
 725
 726                                                 lvds1_mux_0: endpoint {
 727                                                         remote-endpoint = <&ipu1_di0_lvds1>;
 728                                                 };
 729                                         };
 730
 731                                         port@1 {
 732                                                 reg = <1>;
 733
 734                                                 lvds1_mux_1: endpoint {
 735                                                         remote-endpoint = <&ipu1_di1_lvds1>;
 736                                                 };
 737                                         };
 738                                 };
 739                         };
 740
 741                         hdmi: hdmi@0120000 {
 742                                 #address-cells = <1>;
 743                                 #size-cells = <0>;
 744                                 reg = <0x00120000 0x9000>;
 745                                 interrupts = <0 115 0x04>;
 746                                 gpr = <&gpr>;
 747                                 clocks = <&clks 123>, <&clks 124>;
 748                                 clock-names = "iahb", "isfr";
 749                                 status = "disabled";
 750
 751                                 port@0 {
 752                                         reg = <0>;
 753
 754                                         hdmi_mux_0: endpoint {
 755                                                 remote-endpoint = <&ipu1_di0_hdmi>;
 756                                         };
 757                                 };
 758
 759                                 port@1 {
 760                                         reg = <1>;
 761
 762                                         hdmi_mux_1: endpoint {
 763                                                 remote-endpoint = <&ipu1_di1_hdmi>;
 764                                         };
 765                                 };
 766                         };
 767
 768                         dcic1: dcic@020e4000 {
 769                                 reg = <0x020e4000 0x4000>;
 770                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 771                         };
 772
 773                         dcic2: dcic@020e8000 {
 774                                 reg = <0x020e8000 0x4000>;
 775                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 776                         };
 777
 778                         sdma: sdma@020ec000 {
 779                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 780                                 reg = <0x020ec000 0x4000>;
 781                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 782                                 clocks = <&clks 155>, <&clks 155>;
 783                                 clock-names = "ipg", "ahb";
 784                                 #dma-cells = <3>;
 785                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 786                         };
 787                 };
 788
 789                 aips-bus@02100000 { /* AIPS2 */
 790                         compatible = "fsl,aips-bus", "simple-bus";
 791                         #address-cells = <1>;
 792                         #size-cells = <1>;
 793                         reg = <0x02100000 0x100000>;
 794                         ranges;
 795
 796                         caam@02100000 {
 797                                 reg = <0x02100000 0x40000>;
 798                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 799                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 800                         };
 801
 802                         aipstz@0217c000 { /* AIPSTZ2 */
 803                                 reg = <0x0217c000 0x4000>;
 804                         };
 805
 806                         usbotg: usb@02184000 {
 807                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 808                                 reg = <0x02184000 0x200>;
 809                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 810                                 clocks = <&clks 162>;
 811                                 fsl,usbphy = <&usbphy1>;
 812                                 fsl,usbmisc = <&usbmisc 0>;
 813                                 status = "disabled";
 814                         };
 815
 816                         usbh1: usb@02184200 {
 817                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 818                                 reg = <0x02184200 0x200>;
 819                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 820                                 clocks = <&clks 162>;
 821                                 fsl,usbphy = <&usbphy2>;
 822                                 fsl,usbmisc = <&usbmisc 1>;
 823                                 status = "disabled";
 824                         };
 825
 826                         usbh2: usb@02184400 {
 827                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 828                                 reg = <0x02184400 0x200>;
 829                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 830                                 clocks = <&clks 162>;
 831                                 fsl,usbmisc = <&usbmisc 2>;
 832                                 status = "disabled";
 833                         };
 834
 835                         usbh3: usb@02184600 {
 836                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 837                                 reg = <0x02184600 0x200>;
 838                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 839                                 clocks = <&clks 162>;
 840                                 fsl,usbmisc = <&usbmisc 3>;
 841                                 status = "disabled";
 842                         };
 843
 844                         usbmisc: usbmisc@02184800 {
 845                                 #index-cells = <1>;
 846                                 compatible = "fsl,imx6q-usbmisc";
 847                                 reg = <0x02184800 0x200>;
 848                                 clocks = <&clks 162>;
 849                         };
 850
 851                         fec: ethernet@02188000 {
 852                                 compatible = "fsl,imx6q-fec";
 853                                 reg = <0x02188000 0x4000>;
 854                                 interrupts-extended =
 855                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 856                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 857                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
 858                                 clock-names = "ipg", "ahb", "ptp";
 859                                 status = "disabled";
 860                         };
 861
 862                         mlb@0218c000 {
 863                                 reg = <0x0218c000 0x4000>;
 864                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 865                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 866                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 867                         };
 868
 869                         usdhc1: usdhc@02190000 {
 870                                 compatible = "fsl,imx6q-usdhc";
 871                                 reg = <0x02190000 0x4000>;
 872                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 873                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
 874                                 clock-names = "ipg", "ahb", "per";
 875                                 bus-width = <4>;
 876                                 status = "disabled";
 877                         };
 878
 879                         usdhc2: usdhc@02194000 {
 880                                 compatible = "fsl,imx6q-usdhc";
 881                                 reg = <0x02194000 0x4000>;
 882                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 883                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
 884                                 clock-names = "ipg", "ahb", "per";
 885                                 bus-width = <4>;
 886                                 status = "disabled";
 887                         };
 888
 889                         usdhc3: usdhc@02198000 {
 890                                 compatible = "fsl,imx6q-usdhc";
 891                                 reg = <0x02198000 0x4000>;
 892                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 893                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
 894                                 clock-names = "ipg", "ahb", "per";
 895                                 bus-width = <4>;
 896                                 status = "disabled";
 897                         };
 898
 899                         usdhc4: usdhc@0219c000 {
 900                                 compatible = "fsl,imx6q-usdhc";
 901                                 reg = <0x0219c000 0x4000>;
 902                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 903                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
 904                                 clock-names = "ipg", "ahb", "per";
 905                                 bus-width = <4>;
 906                                 status = "disabled";
 907                         };
 908
 909                         i2c1: i2c@021a0000 {
 910                                 #address-cells = <1>;
 911                                 #size-cells = <0>;
 912                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 913                                 reg = <0x021a0000 0x4000>;
 914                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 915                                 clocks = <&clks 125>;
 916                                 status = "disabled";
 917                         };
 918
 919                         i2c2: i2c@021a4000 {
 920                                 #address-cells = <1>;
 921                                 #size-cells = <0>;
 922                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 923                                 reg = <0x021a4000 0x4000>;
 924                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 925                                 clocks = <&clks 126>;
 926                                 status = "disabled";
 927                         };
 928
 929                         i2c3: i2c@021a8000 {
 930                                 #address-cells = <1>;
 931                                 #size-cells = <0>;
 932                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 933                                 reg = <0x021a8000 0x4000>;
 934                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 935                                 clocks = <&clks 127>;
 936                                 status = "disabled";
 937                         };
 938
 939                         romcp@021ac000 {
 940                                 reg = <0x021ac000 0x4000>;
 941                         };
 942
 943                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 944                                 compatible = "fsl,imx6q-mmdc";
 945                                 reg = <0x021b0000 0x4000>;
 946                         };
 947
 948                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 949                                 reg = <0x021b4000 0x4000>;
 950                         };
 951
 952                         weim: weim@021b8000 {
 953                                 compatible = "fsl,imx6q-weim";
 954                                 reg = <0x021b8000 0x4000>;
 955                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 956                                 clocks = <&clks 196>;
 957                         };
 958
 959                         ocotp: ocotp@021bc000 {
 960                                 compatible = "fsl,imx6q-ocotp", "syscon";
 961                                 reg = <0x021bc000 0x4000>;
 962                         };
 963
 964                         tzasc@021d0000 { /* TZASC1 */
 965                                 reg = <0x021d0000 0x4000>;
 966                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 967                         };
 968
 969                         tzasc@021d4000 { /* TZASC2 */
 970                                 reg = <0x021d4000 0x4000>;
 971                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 972                         };
 973
 974                         audmux: audmux@021d8000 {
 975                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 976                                 reg = <0x021d8000 0x4000>;
 977                                 status = "disabled";
 978                         };
 979
 980                         mipi_csi: mipi@021dc000 {
 981                                 reg = <0x021dc000 0x4000>;
 982                         };
 983
 984                         mipi_dsi: mipi@021e0000 {
 985                                 #address-cells = <1>;
 986                                 #size-cells = <0>;
 987                                 reg = <0x021e0000 0x4000>;
 988                                 status = "disabled";
 989
 990                                 port@0 {
 991                                         reg = <0>;
 992
 993                                         mipi_mux_0: endpoint {
 994                                                 remote-endpoint = <&ipu1_di0_mipi>;
 995                                         };
 996                                 };
 997
 998                                 port@1 {
 999                                         reg = <1>;
1000
1001                                         mipi_mux_1: endpoint {
1002                                                 remote-endpoint = <&ipu1_di1_mipi>;
1003                                         };
1004                                 };
1005                         };
1006
1007                         vdoa@021e4000 {
1008                                 reg = <0x021e4000 0x4000>;
1009                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1010                         };
1011
1012                         uart2: serial@021e8000 {
1013                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1014                                 reg = <0x021e8000 0x4000>;
1015                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1016                                 clocks = <&clks 160>, <&clks 161>;
1017                                 clock-names = "ipg", "per";
1018                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1019                                 dma-names = "rx", "tx";
1020                                 status = "disabled";
1021                         };
1022
1023                         uart3: serial@021ec000 {
1024                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1025                                 reg = <0x021ec000 0x4000>;
1026                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1027                                 clocks = <&clks 160>, <&clks 161>;
1028                                 clock-names = "ipg", "per";
1029                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1030                                 dma-names = "rx", "tx";
1031                                 status = "disabled";
1032                         };
1033
1034                         uart4: serial@021f0000 {
1035                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1036                                 reg = <0x021f0000 0x4000>;
1037                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1038                                 clocks = <&clks 160>, <&clks 161>;
1039                                 clock-names = "ipg", "per";
1040                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1041                                 dma-names = "rx", "tx";
1042                                 status = "disabled";
1043                         };
1044
1045                         uart5: serial@021f4000 {
1046                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1047                                 reg = <0x021f4000 0x4000>;
1048                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1049                                 clocks = <&clks 160>, <&clks 161>;
1050                                 clock-names = "ipg", "per";
1051                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1052                                 dma-names = "rx", "tx";
1053                                 status = "disabled";
1054                         };
1055                 };
1056
1057                 ipu1: ipu@02400000 {
1058                         #address-cells = <1>;
1059                         #size-cells = <0>;
1060                         compatible = "fsl,imx6q-ipu";
1061                         reg = <0x02400000 0x400000>;
1062                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1063                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1064                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1065                         clock-names = "bus", "di0", "di1";
1066                         resets = <&src 2>;
1067
1068                         ipu1_di0: port@2 {
1069                                 #address-cells = <1>;
1070                                 #size-cells = <0>;
1071                                 reg = <2>;
1072
1073                                 ipu1_di0_disp0: endpoint@0 {
1074                                 };
1075
1076                                 ipu1_di0_hdmi: endpoint@1 {
1077                                         remote-endpoint = <&hdmi_mux_0>;
1078                                 };
1079
1080                                 ipu1_di0_mipi: endpoint@2 {
1081                                         remote-endpoint = <&mipi_mux_0>;
1082                                 };
1083
1084                                 ipu1_di0_lvds0: endpoint@3 {
1085                                         remote-endpoint = <&lvds0_mux_0>;
1086                                 };
1087
1088                                 ipu1_di0_lvds1: endpoint@4 {
1089                                         remote-endpoint = <&lvds1_mux_0>;
1090                                 };
1091                         };
1092
1093                         ipu1_di1: port@3 {
1094                                 #address-cells = <1>;
1095                                 #size-cells = <0>;
1096                                 reg = <3>;
1097
1098                                 ipu1_di0_disp1: endpoint@0 {
1099                                 };
1100
1101                                 ipu1_di1_hdmi: endpoint@1 {
1102                                         remote-endpoint = <&hdmi_mux_1>;
1103                                 };
1104
1105                                 ipu1_di1_mipi: endpoint@2 {
1106                                         remote-endpoint = <&mipi_mux_1>;
1107                                 };
1108
1109                                 ipu1_di1_lvds0: endpoint@3 {
1110                                         remote-endpoint = <&lvds0_mux_1>;
1111                                 };
1112
1113                                 ipu1_di1_lvds1: endpoint@4 {
1114                                         remote-endpoint = <&lvds1_mux_1>;
1115                                 };
1116                         };
1117                 };
1118         };
1119 };