2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
38 intc: interrupt-controller@00a01000 {
39 compatible = "arm,cortex-a9-gic";
40 #interrupt-cells = <3>;
44 reg = <0x00a01000 0x1000>,
53 compatible = "fsl,imx-ckil", "fixed-clock";
54 clock-frequency = <32768>;
58 compatible = "fsl,imx-ckih1", "fixed-clock";
59 clock-frequency = <0>;
63 compatible = "fsl,imx-osc", "fixed-clock";
64 clock-frequency = <24000000>;
71 compatible = "simple-bus";
72 interrupt-parent = <&intc>;
75 dma_apbh: dma-apbh@00110000 {
76 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
77 reg = <0x00110000 0x2000>;
78 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
79 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
85 gpmi: gpmi-nand@00112000 {
86 compatible = "fsl,imx6q-gpmi-nand";
89 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
90 reg-names = "gpmi-nand", "bch";
91 interrupts = <0 15 0x04>;
92 interrupt-names = "bch";
93 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
94 <&clks 150>, <&clks 149>;
95 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
96 "gpmi_bch_apb", "per1_bch";
102 ocram: sram@00900000 {
103 compatible = "mmio-sram";
104 reg = <0x00900000 0x3f000>;
105 clocks = <&clks 142>;
109 compatible = "arm,cortex-a9-twd-timer";
110 reg = <0x00a00600 0x20>;
111 interrupts = <1 13 0xf01>;
115 L2: l2-cache@00a02000 {
116 compatible = "arm,pl310-cache";
117 reg = <0x00a02000 0x1000>;
118 interrupts = <0 92 0x04>;
121 arm,tag-latency = <4 2 3>;
122 arm,data-latency = <4 2 3>;
126 compatible = "arm,cortex-a9-pmu";
127 interrupts = <0 94 0x04>;
130 aips-bus@02000000 { /* AIPS1 */
131 compatible = "fsl,aips-bus", "simple-bus";
132 #address-cells = <1>;
134 reg = <0x02000000 0x100000>;
138 compatible = "fsl,spba-bus", "simple-bus";
139 #address-cells = <1>;
141 reg = <0x02000000 0x40000>;
144 spdif: spdif@02004000 {
145 reg = <0x02004000 0x4000>;
146 interrupts = <0 52 0x04>;
149 ecspi1: ecspi@02008000 {
150 #address-cells = <1>;
152 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
153 reg = <0x02008000 0x4000>;
154 interrupts = <0 31 0x04>;
155 clocks = <&clks 112>, <&clks 112>;
156 clock-names = "ipg", "per";
160 ecspi2: ecspi@0200c000 {
161 #address-cells = <1>;
163 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
164 reg = <0x0200c000 0x4000>;
165 interrupts = <0 32 0x04>;
166 clocks = <&clks 113>, <&clks 113>;
167 clock-names = "ipg", "per";
171 ecspi3: ecspi@02010000 {
172 #address-cells = <1>;
174 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
175 reg = <0x02010000 0x4000>;
176 interrupts = <0 33 0x04>;
177 clocks = <&clks 114>, <&clks 114>;
178 clock-names = "ipg", "per";
182 ecspi4: ecspi@02014000 {
183 #address-cells = <1>;
185 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
186 reg = <0x02014000 0x4000>;
187 interrupts = <0 34 0x04>;
188 clocks = <&clks 115>, <&clks 115>;
189 clock-names = "ipg", "per";
193 uart1: serial@02020000 {
194 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
195 reg = <0x02020000 0x4000>;
196 interrupts = <0 26 0x04>;
197 clocks = <&clks 160>, <&clks 161>;
198 clock-names = "ipg", "per";
199 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
200 dma-names = "rx", "tx";
204 esai: esai@02024000 {
205 reg = <0x02024000 0x4000>;
206 interrupts = <0 51 0x04>;
210 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
211 reg = <0x02028000 0x4000>;
212 interrupts = <0 46 0x04>;
213 clocks = <&clks 178>;
214 fsl,fifo-depth = <15>;
215 fsl,ssi-dma-events = <38 37>;
220 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
221 reg = <0x0202c000 0x4000>;
222 interrupts = <0 47 0x04>;
223 clocks = <&clks 179>;
224 fsl,fifo-depth = <15>;
225 fsl,ssi-dma-events = <42 41>;
230 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
231 reg = <0x02030000 0x4000>;
232 interrupts = <0 48 0x04>;
233 clocks = <&clks 180>;
234 fsl,fifo-depth = <15>;
235 fsl,ssi-dma-events = <46 45>;
239 asrc: asrc@02034000 {
240 reg = <0x02034000 0x4000>;
241 interrupts = <0 50 0x04>;
245 reg = <0x0203c000 0x4000>;
250 reg = <0x02040000 0x3c000>;
251 interrupts = <0 3 0x04 0 12 0x04>;
254 aipstz@0207c000 { /* AIPSTZ1 */
255 reg = <0x0207c000 0x4000>;
260 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
261 reg = <0x02080000 0x4000>;
262 interrupts = <0 83 0x04>;
263 clocks = <&clks 62>, <&clks 145>;
264 clock-names = "ipg", "per";
269 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
270 reg = <0x02084000 0x4000>;
271 interrupts = <0 84 0x04>;
272 clocks = <&clks 62>, <&clks 146>;
273 clock-names = "ipg", "per";
278 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
279 reg = <0x02088000 0x4000>;
280 interrupts = <0 85 0x04>;
281 clocks = <&clks 62>, <&clks 147>;
282 clock-names = "ipg", "per";
287 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
288 reg = <0x0208c000 0x4000>;
289 interrupts = <0 86 0x04>;
290 clocks = <&clks 62>, <&clks 148>;
291 clock-names = "ipg", "per";
294 can1: flexcan@02090000 {
295 compatible = "fsl,imx6q-flexcan";
296 reg = <0x02090000 0x4000>;
297 interrupts = <0 110 0x04>;
298 clocks = <&clks 108>, <&clks 109>;
299 clock-names = "ipg", "per";
302 can2: flexcan@02094000 {
303 compatible = "fsl,imx6q-flexcan";
304 reg = <0x02094000 0x4000>;
305 interrupts = <0 111 0x04>;
306 clocks = <&clks 110>, <&clks 111>;
307 clock-names = "ipg", "per";
311 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
312 reg = <0x02098000 0x4000>;
313 interrupts = <0 55 0x04>;
314 clocks = <&clks 119>, <&clks 120>;
315 clock-names = "ipg", "per";
318 gpio1: gpio@0209c000 {
319 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
320 reg = <0x0209c000 0x4000>;
321 interrupts = <0 66 0x04 0 67 0x04>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
328 gpio2: gpio@020a0000 {
329 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
330 reg = <0x020a0000 0x4000>;
331 interrupts = <0 68 0x04 0 69 0x04>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
338 gpio3: gpio@020a4000 {
339 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
340 reg = <0x020a4000 0x4000>;
341 interrupts = <0 70 0x04 0 71 0x04>;
344 interrupt-controller;
345 #interrupt-cells = <2>;
348 gpio4: gpio@020a8000 {
349 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
350 reg = <0x020a8000 0x4000>;
351 interrupts = <0 72 0x04 0 73 0x04>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
358 gpio5: gpio@020ac000 {
359 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
360 reg = <0x020ac000 0x4000>;
361 interrupts = <0 74 0x04 0 75 0x04>;
364 interrupt-controller;
365 #interrupt-cells = <2>;
368 gpio6: gpio@020b0000 {
369 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
370 reg = <0x020b0000 0x4000>;
371 interrupts = <0 76 0x04 0 77 0x04>;
374 interrupt-controller;
375 #interrupt-cells = <2>;
378 gpio7: gpio@020b4000 {
379 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
380 reg = <0x020b4000 0x4000>;
381 interrupts = <0 78 0x04 0 79 0x04>;
384 interrupt-controller;
385 #interrupt-cells = <2>;
389 reg = <0x020b8000 0x4000>;
390 interrupts = <0 82 0x04>;
393 wdog1: wdog@020bc000 {
394 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
395 reg = <0x020bc000 0x4000>;
396 interrupts = <0 80 0x04>;
400 wdog2: wdog@020c0000 {
401 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
402 reg = <0x020c0000 0x4000>;
403 interrupts = <0 81 0x04>;
409 compatible = "fsl,imx6q-ccm";
410 reg = <0x020c4000 0x4000>;
411 interrupts = <0 87 0x04 0 88 0x04>;
415 anatop: anatop@020c8000 {
416 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
417 reg = <0x020c8000 0x1000>;
418 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
421 compatible = "fsl,anatop-regulator";
422 regulator-name = "vdd1p1";
423 regulator-min-microvolt = <800000>;
424 regulator-max-microvolt = <1375000>;
426 anatop-reg-offset = <0x110>;
427 anatop-vol-bit-shift = <8>;
428 anatop-vol-bit-width = <5>;
429 anatop-min-bit-val = <4>;
430 anatop-min-voltage = <800000>;
431 anatop-max-voltage = <1375000>;
435 compatible = "fsl,anatop-regulator";
436 regulator-name = "vdd3p0";
437 regulator-min-microvolt = <2800000>;
438 regulator-max-microvolt = <3150000>;
440 anatop-reg-offset = <0x120>;
441 anatop-vol-bit-shift = <8>;
442 anatop-vol-bit-width = <5>;
443 anatop-min-bit-val = <0>;
444 anatop-min-voltage = <2625000>;
445 anatop-max-voltage = <3400000>;
449 compatible = "fsl,anatop-regulator";
450 regulator-name = "vdd2p5";
451 regulator-min-microvolt = <2000000>;
452 regulator-max-microvolt = <2750000>;
454 anatop-reg-offset = <0x130>;
455 anatop-vol-bit-shift = <8>;
456 anatop-vol-bit-width = <5>;
457 anatop-min-bit-val = <0>;
458 anatop-min-voltage = <2000000>;
459 anatop-max-voltage = <2750000>;
462 reg_arm: regulator-vddcore@140 {
463 compatible = "fsl,anatop-regulator";
464 regulator-name = "cpu";
465 regulator-min-microvolt = <725000>;
466 regulator-max-microvolt = <1450000>;
468 anatop-reg-offset = <0x140>;
469 anatop-vol-bit-shift = <0>;
470 anatop-vol-bit-width = <5>;
471 anatop-delay-reg-offset = <0x170>;
472 anatop-delay-bit-shift = <24>;
473 anatop-delay-bit-width = <2>;
474 anatop-min-bit-val = <1>;
475 anatop-min-voltage = <725000>;
476 anatop-max-voltage = <1450000>;
479 reg_pu: regulator-vddpu@140 {
480 compatible = "fsl,anatop-regulator";
481 regulator-name = "vddpu";
482 regulator-min-microvolt = <725000>;
483 regulator-max-microvolt = <1450000>;
485 anatop-reg-offset = <0x140>;
486 anatop-vol-bit-shift = <9>;
487 anatop-vol-bit-width = <5>;
488 anatop-delay-reg-offset = <0x170>;
489 anatop-delay-bit-shift = <26>;
490 anatop-delay-bit-width = <2>;
491 anatop-min-bit-val = <1>;
492 anatop-min-voltage = <725000>;
493 anatop-max-voltage = <1450000>;
496 reg_soc: regulator-vddsoc@140 {
497 compatible = "fsl,anatop-regulator";
498 regulator-name = "vddsoc";
499 regulator-min-microvolt = <725000>;
500 regulator-max-microvolt = <1450000>;
502 anatop-reg-offset = <0x140>;
503 anatop-vol-bit-shift = <18>;
504 anatop-vol-bit-width = <5>;
505 anatop-delay-reg-offset = <0x170>;
506 anatop-delay-bit-shift = <28>;
507 anatop-delay-bit-width = <2>;
508 anatop-min-bit-val = <1>;
509 anatop-min-voltage = <725000>;
510 anatop-max-voltage = <1450000>;
515 compatible = "fsl,imx6q-tempmon";
516 interrupts = <0 49 0x04>;
517 fsl,tempmon = <&anatop>;
518 fsl,tempmon-data = <&ocotp>;
521 usbphy1: usbphy@020c9000 {
522 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
523 reg = <0x020c9000 0x1000>;
524 interrupts = <0 44 0x04>;
525 clocks = <&clks 182>;
528 usbphy2: usbphy@020ca000 {
529 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
530 reg = <0x020ca000 0x1000>;
531 interrupts = <0 45 0x04>;
532 clocks = <&clks 183>;
536 compatible = "fsl,sec-v4.0-mon", "simple-bus";
537 #address-cells = <1>;
539 ranges = <0 0x020cc000 0x4000>;
542 compatible = "fsl,sec-v4.0-mon-rtc-lp";
544 interrupts = <0 19 0x04 0 20 0x04>;
548 epit1: epit@020d0000 { /* EPIT1 */
549 reg = <0x020d0000 0x4000>;
550 interrupts = <0 56 0x04>;
553 epit2: epit@020d4000 { /* EPIT2 */
554 reg = <0x020d4000 0x4000>;
555 interrupts = <0 57 0x04>;
559 compatible = "fsl,imx6q-src", "fsl,imx51-src";
560 reg = <0x020d8000 0x4000>;
561 interrupts = <0 91 0x04 0 96 0x04>;
566 compatible = "fsl,imx6q-gpc";
567 reg = <0x020dc000 0x4000>;
568 interrupts = <0 89 0x04 0 90 0x04>;
571 gpr: iomuxc-gpr@020e0000 {
572 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
573 reg = <0x020e0000 0x38>;
576 iomuxc: iomuxc@020e0000 {
577 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
578 reg = <0x020e0000 0x4000>;
581 pinctrl_audmux_1: audmux-1 {
583 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
584 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
585 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
586 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
590 pinctrl_audmux_2: audmux-2 {
592 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
593 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
594 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
595 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
599 pinctrl_audmux_3: audmux-3 {
601 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000
602 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
603 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
609 pinctrl_ecspi1_1: ecspi1grp-1 {
611 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
612 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
613 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
617 pinctrl_ecspi1_2: ecspi1grp-2 {
619 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
620 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
621 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
627 pinctrl_ecspi3_1: ecspi3grp-1 {
629 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
630 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
631 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
637 pinctrl_enet_1: enetgrp-1 {
639 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
640 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
641 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
642 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
643 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
644 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
645 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
646 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
647 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
648 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
649 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
650 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
651 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
652 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
653 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
654 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
658 pinctrl_enet_2: enetgrp-2 {
660 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
661 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
662 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
663 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
664 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
665 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
666 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
667 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
668 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
669 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
670 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
671 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
672 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
673 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
674 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
678 pinctrl_enet_3: enetgrp-3 {
680 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
681 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
682 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
683 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
684 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
685 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
686 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
687 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
688 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
689 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
690 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
691 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
692 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
693 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
694 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
695 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
701 pinctrl_esai_1: esaigrp-1 {
703 MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
704 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
705 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
706 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
707 MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
708 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
709 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
710 MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
711 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
715 pinctrl_esai_2: esaigrp-2 {
717 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
718 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
719 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
720 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
721 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
722 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
723 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
724 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
725 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
726 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
732 pinctrl_flexcan1_1: flexcan1grp-1 {
734 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
735 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
739 pinctrl_flexcan1_2: flexcan1grp-2 {
741 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
742 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
748 pinctrl_flexcan2_1: flexcan2grp-1 {
750 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
751 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
757 pinctrl_gpmi_nand_1: gpmi-nand-1 {
759 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
760 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
761 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
762 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
763 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
764 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
765 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
766 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
767 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
768 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
769 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
770 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
771 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
772 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
773 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
774 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
775 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
781 pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
783 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
784 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
788 pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
790 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
791 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
795 pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
797 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
798 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
804 pinctrl_hdmi_cec_1: hdmicecgrp-1 {
806 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
810 pinctrl_hdmi_cec_2: hdmicecgrp-2 {
812 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
818 pinctrl_i2c1_1: i2c1grp-1 {
820 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
821 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
825 pinctrl_i2c1_2: i2c1grp-2 {
827 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
828 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
834 pinctrl_i2c2_1: i2c2grp-1 {
836 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
837 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
841 pinctrl_i2c2_2: i2c2grp-2 {
843 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
844 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
848 pinctrl_i2c2_3: i2c2grp-3 {
850 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
851 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
857 pinctrl_i2c3_1: i2c3grp-1 {
859 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
860 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
864 pinctrl_i2c3_2: i2c3grp-2 {
866 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
867 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
871 pinctrl_i2c3_3: i2c3grp-3 {
873 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
874 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
878 pinctrl_i2c3_4: i2c3grp-4 {
880 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
881 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
887 pinctrl_ipu1_1: ipu1grp-1 {
889 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
890 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
891 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
892 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
893 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
894 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
895 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
896 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
897 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
898 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
899 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
900 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
901 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
902 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
903 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
904 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
905 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
906 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
907 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
908 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
909 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
910 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
911 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
912 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
913 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
914 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
915 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
916 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
917 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
921 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
923 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
924 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
925 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
926 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
927 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
928 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
929 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
930 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
931 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
932 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
933 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
934 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
938 pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
940 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
941 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
942 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
943 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
944 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
945 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
946 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
947 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
948 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
949 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
950 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
951 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
952 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
953 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
954 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
955 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
956 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
957 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
958 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
964 pinctrl_mlb_1: mlbgrp-1 {
966 MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
967 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
968 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
972 pinctrl_mlb_2: mlbgrp-2 {
974 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
975 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
976 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
982 pinctrl_pwm0_1: pwm0grp-1 {
984 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
990 pinctrl_pwm3_1: pwm3grp-1 {
992 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
998 pinctrl_spdif_1: spdifgrp-1 {
1000 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
1004 pinctrl_spdif_2: spdifgrp-2 {
1006 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
1007 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1013 pinctrl_uart1_1: uart1grp-1 {
1015 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1016 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1022 pinctrl_uart2_1: uart2grp-1 {
1024 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
1025 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
1029 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
1031 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
1032 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
1033 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
1034 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
1040 pinctrl_uart3_1: uart3grp-1 {
1042 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
1043 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
1044 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
1045 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1049 pinctrl_uart3_2: uart3grp-2 {
1051 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1052 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1053 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
1054 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1060 pinctrl_uart4_1: uart4grp-1 {
1062 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1063 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1069 pinctrl_usbotg_1: usbotggrp-1 {
1071 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
1075 pinctrl_usbotg_2: usbotggrp-2 {
1077 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1083 pinctrl_usbh2_1: usbh2grp-1 {
1085 MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
1086 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
1090 pinctrl_usbh2_2: usbh2grp-2 {
1092 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
1098 pinctrl_usbh3_1: usbh3grp-1 {
1100 MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
1101 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
1105 pinctrl_usbh3_2: usbh3grp-2 {
1107 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
1113 pinctrl_usdhc1_1: usdhc1grp-1 {
1115 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1116 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1117 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1118 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1119 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1120 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1121 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
1122 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
1123 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
1124 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
1128 pinctrl_usdhc1_2: usdhc1grp-2 {
1130 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1131 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1132 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1133 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1134 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1135 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1141 pinctrl_usdhc2_1: usdhc2grp-1 {
1143 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1144 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1145 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1146 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1147 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1148 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1149 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
1150 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
1151 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
1152 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
1156 pinctrl_usdhc2_2: usdhc2grp-2 {
1158 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1159 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1160 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1161 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1162 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1163 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1169 pinctrl_usdhc3_1: usdhc3grp-1 {
1171 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1172 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1173 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1174 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1175 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1176 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1177 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1178 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1179 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1180 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1184 pinctrl_usdhc3_2: usdhc3grp-2 {
1186 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1187 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1188 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1189 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1190 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1191 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1197 pinctrl_usdhc4_1: usdhc4grp-1 {
1199 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1200 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1201 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1202 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1203 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1204 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1205 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1206 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1207 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1208 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1212 pinctrl_usdhc4_2: usdhc4grp-2 {
1214 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1215 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1216 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1217 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1218 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1219 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1225 pinctrl_weim_cs0_1: weim_cs0grp-1 {
1227 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
1231 pinctrl_weim_nor_1: weim_norgrp-1 {
1233 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
1234 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
1235 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1237 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1238 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1239 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1240 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1241 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1242 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1243 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1244 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1245 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1246 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1247 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1248 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1249 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1250 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1251 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1252 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1254 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1255 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1256 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1257 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1258 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1259 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1260 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1261 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1262 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
1263 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
1264 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
1265 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
1266 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
1267 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
1268 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
1269 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
1270 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
1271 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
1272 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
1273 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
1274 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
1275 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
1276 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
1277 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
1284 #address-cells = <1>;
1286 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
1288 status = "disabled";
1292 status = "disabled";
1297 status = "disabled";
1301 dcic1: dcic@020e4000 {
1302 reg = <0x020e4000 0x4000>;
1303 interrupts = <0 124 0x04>;
1306 dcic2: dcic@020e8000 {
1307 reg = <0x020e8000 0x4000>;
1308 interrupts = <0 125 0x04>;
1311 sdma: sdma@020ec000 {
1312 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
1313 reg = <0x020ec000 0x4000>;
1314 interrupts = <0 2 0x04>;
1315 clocks = <&clks 155>, <&clks 155>;
1316 clock-names = "ipg", "ahb";
1318 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
1322 aips-bus@02100000 { /* AIPS2 */
1323 compatible = "fsl,aips-bus", "simple-bus";
1324 #address-cells = <1>;
1326 reg = <0x02100000 0x100000>;
1330 reg = <0x02100000 0x40000>;
1331 interrupts = <0 105 0x04 0 106 0x04>;
1334 aipstz@0217c000 { /* AIPSTZ2 */
1335 reg = <0x0217c000 0x4000>;
1338 usbotg: usb@02184000 {
1339 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1340 reg = <0x02184000 0x200>;
1341 interrupts = <0 43 0x04>;
1342 clocks = <&clks 162>;
1343 fsl,usbphy = <&usbphy1>;
1344 fsl,usbmisc = <&usbmisc 0>;
1345 status = "disabled";
1348 usbh1: usb@02184200 {
1349 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1350 reg = <0x02184200 0x200>;
1351 interrupts = <0 40 0x04>;
1352 clocks = <&clks 162>;
1353 fsl,usbphy = <&usbphy2>;
1354 fsl,usbmisc = <&usbmisc 1>;
1355 status = "disabled";
1358 usbh2: usb@02184400 {
1359 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1360 reg = <0x02184400 0x200>;
1361 interrupts = <0 41 0x04>;
1362 clocks = <&clks 162>;
1363 fsl,usbmisc = <&usbmisc 2>;
1364 status = "disabled";
1367 usbh3: usb@02184600 {
1368 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1369 reg = <0x02184600 0x200>;
1370 interrupts = <0 42 0x04>;
1371 clocks = <&clks 162>;
1372 fsl,usbmisc = <&usbmisc 3>;
1373 status = "disabled";
1376 usbmisc: usbmisc@02184800 {
1378 compatible = "fsl,imx6q-usbmisc";
1379 reg = <0x02184800 0x200>;
1380 clocks = <&clks 162>;
1383 fec: ethernet@02188000 {
1384 compatible = "fsl,imx6q-fec";
1385 reg = <0x02188000 0x4000>;
1386 interrupts = <0 118 0x04 0 119 0x04>;
1387 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
1388 clock-names = "ipg", "ahb", "ptp";
1389 status = "disabled";
1393 reg = <0x0218c000 0x4000>;
1394 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
1397 usdhc1: usdhc@02190000 {
1398 compatible = "fsl,imx6q-usdhc";
1399 reg = <0x02190000 0x4000>;
1400 interrupts = <0 22 0x04>;
1401 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
1402 clock-names = "ipg", "ahb", "per";
1404 status = "disabled";
1407 usdhc2: usdhc@02194000 {
1408 compatible = "fsl,imx6q-usdhc";
1409 reg = <0x02194000 0x4000>;
1410 interrupts = <0 23 0x04>;
1411 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
1412 clock-names = "ipg", "ahb", "per";
1414 status = "disabled";
1417 usdhc3: usdhc@02198000 {
1418 compatible = "fsl,imx6q-usdhc";
1419 reg = <0x02198000 0x4000>;
1420 interrupts = <0 24 0x04>;
1421 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
1422 clock-names = "ipg", "ahb", "per";
1424 status = "disabled";
1427 usdhc4: usdhc@0219c000 {
1428 compatible = "fsl,imx6q-usdhc";
1429 reg = <0x0219c000 0x4000>;
1430 interrupts = <0 25 0x04>;
1431 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
1432 clock-names = "ipg", "ahb", "per";
1434 status = "disabled";
1437 i2c1: i2c@021a0000 {
1438 #address-cells = <1>;
1440 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1441 reg = <0x021a0000 0x4000>;
1442 interrupts = <0 36 0x04>;
1443 clocks = <&clks 125>;
1444 status = "disabled";
1447 i2c2: i2c@021a4000 {
1448 #address-cells = <1>;
1450 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1451 reg = <0x021a4000 0x4000>;
1452 interrupts = <0 37 0x04>;
1453 clocks = <&clks 126>;
1454 status = "disabled";
1457 i2c3: i2c@021a8000 {
1458 #address-cells = <1>;
1460 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1461 reg = <0x021a8000 0x4000>;
1462 interrupts = <0 38 0x04>;
1463 clocks = <&clks 127>;
1464 status = "disabled";
1468 reg = <0x021ac000 0x4000>;
1471 mmdc0: mmdc@021b0000 { /* MMDC0 */
1472 compatible = "fsl,imx6q-mmdc";
1473 reg = <0x021b0000 0x4000>;
1476 mmdc1: mmdc@021b4000 { /* MMDC1 */
1477 reg = <0x021b4000 0x4000>;
1480 weim: weim@021b8000 {
1481 compatible = "fsl,imx6q-weim";
1482 reg = <0x021b8000 0x4000>;
1483 interrupts = <0 14 0x04>;
1484 clocks = <&clks 196>;
1487 ocotp: ocotp@021bc000 {
1488 compatible = "fsl,imx6q-ocotp", "syscon";
1489 reg = <0x021bc000 0x4000>;
1492 tzasc@021d0000 { /* TZASC1 */
1493 reg = <0x021d0000 0x4000>;
1494 interrupts = <0 108 0x04>;
1497 tzasc@021d4000 { /* TZASC2 */
1498 reg = <0x021d4000 0x4000>;
1499 interrupts = <0 109 0x04>;
1502 audmux: audmux@021d8000 {
1503 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1504 reg = <0x021d8000 0x4000>;
1505 status = "disabled";
1508 mipi@021dc000 { /* MIPI-CSI */
1509 reg = <0x021dc000 0x4000>;
1512 mipi@021e0000 { /* MIPI-DSI */
1513 reg = <0x021e0000 0x4000>;
1517 reg = <0x021e4000 0x4000>;
1518 interrupts = <0 18 0x04>;
1521 uart2: serial@021e8000 {
1522 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1523 reg = <0x021e8000 0x4000>;
1524 interrupts = <0 27 0x04>;
1525 clocks = <&clks 160>, <&clks 161>;
1526 clock-names = "ipg", "per";
1527 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1528 dma-names = "rx", "tx";
1529 status = "disabled";
1532 uart3: serial@021ec000 {
1533 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1534 reg = <0x021ec000 0x4000>;
1535 interrupts = <0 28 0x04>;
1536 clocks = <&clks 160>, <&clks 161>;
1537 clock-names = "ipg", "per";
1538 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1539 dma-names = "rx", "tx";
1540 status = "disabled";
1543 uart4: serial@021f0000 {
1544 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1545 reg = <0x021f0000 0x4000>;
1546 interrupts = <0 29 0x04>;
1547 clocks = <&clks 160>, <&clks 161>;
1548 clock-names = "ipg", "per";
1549 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1550 dma-names = "rx", "tx";
1551 status = "disabled";
1554 uart5: serial@021f4000 {
1555 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1556 reg = <0x021f4000 0x4000>;
1557 interrupts = <0 30 0x04>;
1558 clocks = <&clks 160>, <&clks 161>;
1559 clock-names = "ipg", "per";
1560 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1561 dma-names = "rx", "tx";
1562 status = "disabled";
1566 ipu1: ipu@02400000 {
1568 compatible = "fsl,imx6q-ipu";
1569 reg = <0x02400000 0x400000>;
1570 interrupts = <0 6 0x4 0 5 0x4>;
1571 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1572 clock-names = "bus", "di0", "di1";