arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 gpio0 = &gpio1;
  18                 gpio1 = &gpio2;
  19                 gpio2 = &gpio3;
  20                 gpio3 = &gpio4;
  21                 gpio4 = &gpio5;
  22                 gpio5 = &gpio6;
  23                 gpio6 = &gpio7;
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 serial0 = &uart1;
  28                 serial1 = &uart2;
  29                 serial2 = &uart3;
  30                 serial3 = &uart4;
  31                 serial4 = &uart5;
  32                 spi0 = &ecspi1;
  33                 spi1 = &ecspi2;
  34                 spi2 = &ecspi3;
  35                 spi3 = &ecspi4;
  36         };
  37
  38         intc: interrupt-controller@00a01000 {
  39                 compatible = "arm,cortex-a9-gic";
  40                 #interrupt-cells = <3>;
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43                 interrupt-controller;
  44                 reg = <0x00a01000 0x1000>,
  45                       <0x00a00100 0x100>;
  46         };
  47
  48         clocks {
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51
  52                 ckil {
  53                         compatible = "fsl,imx-ckil", "fixed-clock";
  54                         clock-frequency = <32768>;
  55                 };
  56
  57                 ckih1 {
  58                         compatible = "fsl,imx-ckih1", "fixed-clock";
  59                         clock-frequency = <0>;
  60                 };
  61
  62                 osc {
  63                         compatible = "fsl,imx-osc", "fixed-clock";
  64                         clock-frequency = <24000000>;
  65                 };
  66         };
  67
  68         soc {
  69                 #address-cells = <1>;
  70                 #size-cells = <1>;
  71                 compatible = "simple-bus";
  72                 interrupt-parent = <&intc>;
  73                 ranges;
  74
  75                 dma_apbh: dma-apbh@00110000 {
  76                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  77                         reg = <0x00110000 0x2000>;
  78                         interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
  79                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  80                         #dma-cells = <1>;
  81                         dma-channels = <4>;
  82                         clocks = <&clks 106>;
  83                 };
  84
  85                 gpmi: gpmi-nand@00112000 {
  86                         compatible = "fsl,imx6q-gpmi-nand";
  87                         #address-cells = <1>;
  88                         #size-cells = <1>;
  89                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
  90                         reg-names = "gpmi-nand", "bch";
  91                         interrupts = <0 13 0x04>, <0 15 0x04>;
  92                         interrupt-names = "gpmi-dma", "bch";
  93                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
  94                                  <&clks 150>, <&clks 149>;
  95                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
  96                                       "gpmi_bch_apb", "per1_bch";
  97                         dmas = <&dma_apbh 0>;
  98                         dma-names = "rx-tx";
  99                         fsl,gpmi-dma-channel = <0>;
 100                         status = "disabled";
 101                 };
 102
 103                 ocram: sram@00900000 {
 104                         compatible = "mmio-sram";
 105                         reg = <0x00900000 0x3f000>;
 106                         clocks = <&clks 142>;
 107                 };
 108
 109                 timer@00a00600 {
 110                         compatible = "arm,cortex-a9-twd-timer";
 111                         reg = <0x00a00600 0x20>;
 112                         interrupts = <1 13 0xf01>;
 113                         clocks = <&clks 15>;
 114                 };
 115
 116                 L2: l2-cache@00a02000 {
 117                         compatible = "arm,pl310-cache";
 118                         reg = <0x00a02000 0x1000>;
 119                         interrupts = <0 92 0x04>;
 120                         cache-unified;
 121                         cache-level = <2>;
 122                         arm,tag-latency = <4 2 3>;
 123                         arm,data-latency = <4 2 3>;
 124                 };
 125
 126                 pmu {
 127                         compatible = "arm,cortex-a9-pmu";
 128                         interrupts = <0 94 0x04>;
 129                 };
 130
 131                 aips-bus@02000000 { /* AIPS1 */
 132                         compatible = "fsl,aips-bus", "simple-bus";
 133                         #address-cells = <1>;
 134                         #size-cells = <1>;
 135                         reg = <0x02000000 0x100000>;
 136                         ranges;
 137
 138                         spba-bus@02000000 {
 139                                 compatible = "fsl,spba-bus", "simple-bus";
 140                                 #address-cells = <1>;
 141                                 #size-cells = <1>;
 142                                 reg = <0x02000000 0x40000>;
 143                                 ranges;
 144
 145                                 spdif: spdif@02004000 {
 146                                         reg = <0x02004000 0x4000>;
 147                                         interrupts = <0 52 0x04>;
 148                                 };
 149
 150                                 ecspi1: ecspi@02008000 {
 151                                         #address-cells = <1>;
 152                                         #size-cells = <0>;
 153                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 154                                         reg = <0x02008000 0x4000>;
 155                                         interrupts = <0 31 0x04>;
 156                                         clocks = <&clks 112>, <&clks 112>;
 157                                         clock-names = "ipg", "per";
 158                                         status = "disabled";
 159                                 };
 160
 161                                 ecspi2: ecspi@0200c000 {
 162                                         #address-cells = <1>;
 163                                         #size-cells = <0>;
 164                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 165                                         reg = <0x0200c000 0x4000>;
 166                                         interrupts = <0 32 0x04>;
 167                                         clocks = <&clks 113>, <&clks 113>;
 168                                         clock-names = "ipg", "per";
 169                                         status = "disabled";
 170                                 };
 171
 172                                 ecspi3: ecspi@02010000 {
 173                                         #address-cells = <1>;
 174                                         #size-cells = <0>;
 175                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 176                                         reg = <0x02010000 0x4000>;
 177                                         interrupts = <0 33 0x04>;
 178                                         clocks = <&clks 114>, <&clks 114>;
 179                                         clock-names = "ipg", "per";
 180                                         status = "disabled";
 181                                 };
 182
 183                                 ecspi4: ecspi@02014000 {
 184                                         #address-cells = <1>;
 185                                         #size-cells = <0>;
 186                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 187                                         reg = <0x02014000 0x4000>;
 188                                         interrupts = <0 34 0x04>;
 189                                         clocks = <&clks 115>, <&clks 115>;
 190                                         clock-names = "ipg", "per";
 191                                         status = "disabled";
 192                                 };
 193
 194                                 uart1: serial@02020000 {
 195                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 196                                         reg = <0x02020000 0x4000>;
 197                                         interrupts = <0 26 0x04>;
 198                                         clocks = <&clks 160>, <&clks 161>;
 199                                         clock-names = "ipg", "per";
 200                                         status = "disabled";
 201                                 };
 202
 203                                 esai: esai@02024000 {
 204                                         reg = <0x02024000 0x4000>;
 205                                         interrupts = <0 51 0x04>;
 206                                 };
 207
 208                                 ssi1: ssi@02028000 {
 209                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 210                                         reg = <0x02028000 0x4000>;
 211                                         interrupts = <0 46 0x04>;
 212                                         clocks = <&clks 178>;
 213                                         fsl,fifo-depth = <15>;
 214                                         fsl,ssi-dma-events = <38 37>;
 215                                         status = "disabled";
 216                                 };
 217
 218                                 ssi2: ssi@0202c000 {
 219                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 220                                         reg = <0x0202c000 0x4000>;
 221                                         interrupts = <0 47 0x04>;
 222                                         clocks = <&clks 179>;
 223                                         fsl,fifo-depth = <15>;
 224                                         fsl,ssi-dma-events = <42 41>;
 225                                         status = "disabled";
 226                                 };
 227
 228                                 ssi3: ssi@02030000 {
 229                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 230                                         reg = <0x02030000 0x4000>;
 231                                         interrupts = <0 48 0x04>;
 232                                         clocks = <&clks 180>;
 233                                         fsl,fifo-depth = <15>;
 234                                         fsl,ssi-dma-events = <46 45>;
 235                                         status = "disabled";
 236                                 };
 237
 238                                 asrc: asrc@02034000 {
 239                                         reg = <0x02034000 0x4000>;
 240                                         interrupts = <0 50 0x04>;
 241                                 };
 242
 243                                 spba@0203c000 {
 244                                         reg = <0x0203c000 0x4000>;
 245                                 };
 246                         };
 247
 248                         vpu: vpu@02040000 {
 249                                 reg = <0x02040000 0x3c000>;
 250                                 interrupts = <0 3 0x04 0 12 0x04>;
 251                         };
 252
 253                         aipstz@0207c000 { /* AIPSTZ1 */
 254                                 reg = <0x0207c000 0x4000>;
 255                         };
 256
 257                         pwm1: pwm@02080000 {
 258                                 #pwm-cells = <2>;
 259                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 260                                 reg = <0x02080000 0x4000>;
 261                                 interrupts = <0 83 0x04>;
 262                                 clocks = <&clks 62>, <&clks 145>;
 263                                 clock-names = "ipg", "per";
 264                         };
 265
 266                         pwm2: pwm@02084000 {
 267                                 #pwm-cells = <2>;
 268                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 269                                 reg = <0x02084000 0x4000>;
 270                                 interrupts = <0 84 0x04>;
 271                                 clocks = <&clks 62>, <&clks 146>;
 272                                 clock-names = "ipg", "per";
 273                         };
 274
 275                         pwm3: pwm@02088000 {
 276                                 #pwm-cells = <2>;
 277                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 278                                 reg = <0x02088000 0x4000>;
 279                                 interrupts = <0 85 0x04>;
 280                                 clocks = <&clks 62>, <&clks 147>;
 281                                 clock-names = "ipg", "per";
 282                         };
 283
 284                         pwm4: pwm@0208c000 {
 285                                 #pwm-cells = <2>;
 286                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 287                                 reg = <0x0208c000 0x4000>;
 288                                 interrupts = <0 86 0x04>;
 289                                 clocks = <&clks 62>, <&clks 148>;
 290                                 clock-names = "ipg", "per";
 291                         };
 292
 293                         can1: flexcan@02090000 {
 294                                 compatible = "fsl,imx6q-flexcan";
 295                                 reg = <0x02090000 0x4000>;
 296                                 interrupts = <0 110 0x04>;
 297                                 clocks = <&clks 108>, <&clks 109>;
 298                                 clock-names = "ipg", "per";
 299                         };
 300
 301                         can2: flexcan@02094000 {
 302                                 compatible = "fsl,imx6q-flexcan";
 303                                 reg = <0x02094000 0x4000>;
 304                                 interrupts = <0 111 0x04>;
 305                                 clocks = <&clks 110>, <&clks 111>;
 306                                 clock-names = "ipg", "per";
 307                         };
 308
 309                         gpt: gpt@02098000 {
 310                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 311                                 reg = <0x02098000 0x4000>;
 312                                 interrupts = <0 55 0x04>;
 313                                 clocks = <&clks 119>, <&clks 120>;
 314                                 clock-names = "ipg", "per";
 315                         };
 316
 317                         gpio1: gpio@0209c000 {
 318                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 319                                 reg = <0x0209c000 0x4000>;
 320                                 interrupts = <0 66 0x04 0 67 0x04>;
 321                                 gpio-controller;
 322                                 #gpio-cells = <2>;
 323                                 interrupt-controller;
 324                                 #interrupt-cells = <2>;
 325                         };
 326
 327                         gpio2: gpio@020a0000 {
 328                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 329                                 reg = <0x020a0000 0x4000>;
 330                                 interrupts = <0 68 0x04 0 69 0x04>;
 331                                 gpio-controller;
 332                                 #gpio-cells = <2>;
 333                                 interrupt-controller;
 334                                 #interrupt-cells = <2>;
 335                         };
 336
 337                         gpio3: gpio@020a4000 {
 338                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 339                                 reg = <0x020a4000 0x4000>;
 340                                 interrupts = <0 70 0x04 0 71 0x04>;
 341                                 gpio-controller;
 342                                 #gpio-cells = <2>;
 343                                 interrupt-controller;
 344                                 #interrupt-cells = <2>;
 345                         };
 346
 347                         gpio4: gpio@020a8000 {
 348                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 349                                 reg = <0x020a8000 0x4000>;
 350                                 interrupts = <0 72 0x04 0 73 0x04>;
 351                                 gpio-controller;
 352                                 #gpio-cells = <2>;
 353                                 interrupt-controller;
 354                                 #interrupt-cells = <2>;
 355                         };
 356
 357                         gpio5: gpio@020ac000 {
 358                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 359                                 reg = <0x020ac000 0x4000>;
 360                                 interrupts = <0 74 0x04 0 75 0x04>;
 361                                 gpio-controller;
 362                                 #gpio-cells = <2>;
 363                                 interrupt-controller;
 364                                 #interrupt-cells = <2>;
 365                         };
 366
 367                         gpio6: gpio@020b0000 {
 368                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 369                                 reg = <0x020b0000 0x4000>;
 370                                 interrupts = <0 76 0x04 0 77 0x04>;
 371                                 gpio-controller;
 372                                 #gpio-cells = <2>;
 373                                 interrupt-controller;
 374                                 #interrupt-cells = <2>;
 375                         };
 376
 377                         gpio7: gpio@020b4000 {
 378                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 379                                 reg = <0x020b4000 0x4000>;
 380                                 interrupts = <0 78 0x04 0 79 0x04>;
 381                                 gpio-controller;
 382                                 #gpio-cells = <2>;
 383                                 interrupt-controller;
 384                                 #interrupt-cells = <2>;
 385                         };
 386
 387                         kpp: kpp@020b8000 {
 388                                 reg = <0x020b8000 0x4000>;
 389                                 interrupts = <0 82 0x04>;
 390                         };
 391
 392                         wdog1: wdog@020bc000 {
 393                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 394                                 reg = <0x020bc000 0x4000>;
 395                                 interrupts = <0 80 0x04>;
 396                                 clocks = <&clks 0>;
 397                         };
 398
 399                         wdog2: wdog@020c0000 {
 400                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 401                                 reg = <0x020c0000 0x4000>;
 402                                 interrupts = <0 81 0x04>;
 403                                 clocks = <&clks 0>;
 404                                 status = "disabled";
 405                         };
 406
 407                         clks: ccm@020c4000 {
 408                                 compatible = "fsl,imx6q-ccm";
 409                                 reg = <0x020c4000 0x4000>;
 410                                 interrupts = <0 87 0x04 0 88 0x04>;
 411                                 #clock-cells = <1>;
 412                         };
 413
 414                         anatop: anatop@020c8000 {
 415                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 416                                 reg = <0x020c8000 0x1000>;
 417                                 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 418
 419                                 regulator-1p1@110 {
 420                                         compatible = "fsl,anatop-regulator";
 421                                         regulator-name = "vdd1p1";
 422                                         regulator-min-microvolt = <800000>;
 423                                         regulator-max-microvolt = <1375000>;
 424                                         regulator-always-on;
 425                                         anatop-reg-offset = <0x110>;
 426                                         anatop-vol-bit-shift = <8>;
 427                                         anatop-vol-bit-width = <5>;
 428                                         anatop-min-bit-val = <4>;
 429                                         anatop-min-voltage = <800000>;
 430                                         anatop-max-voltage = <1375000>;
 431                                 };
 432
 433                                 regulator-3p0@120 {
 434                                         compatible = "fsl,anatop-regulator";
 435                                         regulator-name = "vdd3p0";
 436                                         regulator-min-microvolt = <2800000>;
 437                                         regulator-max-microvolt = <3150000>;
 438                                         regulator-always-on;
 439                                         anatop-reg-offset = <0x120>;
 440                                         anatop-vol-bit-shift = <8>;
 441                                         anatop-vol-bit-width = <5>;
 442                                         anatop-min-bit-val = <0>;
 443                                         anatop-min-voltage = <2625000>;
 444                                         anatop-max-voltage = <3400000>;
 445                                 };
 446
 447                                 regulator-2p5@130 {
 448                                         compatible = "fsl,anatop-regulator";
 449                                         regulator-name = "vdd2p5";
 450                                         regulator-min-microvolt = <2000000>;
 451                                         regulator-max-microvolt = <2750000>;
 452                                         regulator-always-on;
 453                                         anatop-reg-offset = <0x130>;
 454                                         anatop-vol-bit-shift = <8>;
 455                                         anatop-vol-bit-width = <5>;
 456                                         anatop-min-bit-val = <0>;
 457                                         anatop-min-voltage = <2000000>;
 458                                         anatop-max-voltage = <2750000>;
 459                                 };
 460
 461                                 reg_arm: regulator-vddcore@140 {
 462                                         compatible = "fsl,anatop-regulator";
 463                                         regulator-name = "cpu";
 464                                         regulator-min-microvolt = <725000>;
 465                                         regulator-max-microvolt = <1450000>;
 466                                         regulator-always-on;
 467                                         anatop-reg-offset = <0x140>;
 468                                         anatop-vol-bit-shift = <0>;
 469                                         anatop-vol-bit-width = <5>;
 470                                         anatop-delay-reg-offset = <0x170>;
 471                                         anatop-delay-bit-shift = <24>;
 472                                         anatop-delay-bit-width = <2>;
 473                                         anatop-min-bit-val = <1>;
 474                                         anatop-min-voltage = <725000>;
 475                                         anatop-max-voltage = <1450000>;
 476                                 };
 477
 478                                 reg_pu: regulator-vddpu@140 {
 479                                         compatible = "fsl,anatop-regulator";
 480                                         regulator-name = "vddpu";
 481                                         regulator-min-microvolt = <725000>;
 482                                         regulator-max-microvolt = <1450000>;
 483                                         regulator-always-on;
 484                                         anatop-reg-offset = <0x140>;
 485                                         anatop-vol-bit-shift = <9>;
 486                                         anatop-vol-bit-width = <5>;
 487                                         anatop-delay-reg-offset = <0x170>;
 488                                         anatop-delay-bit-shift = <26>;
 489                                         anatop-delay-bit-width = <2>;
 490                                         anatop-min-bit-val = <1>;
 491                                         anatop-min-voltage = <725000>;
 492                                         anatop-max-voltage = <1450000>;
 493                                 };
 494
 495                                 reg_soc: regulator-vddsoc@140 {
 496                                         compatible = "fsl,anatop-regulator";
 497                                         regulator-name = "vddsoc";
 498                                         regulator-min-microvolt = <725000>;
 499                                         regulator-max-microvolt = <1450000>;
 500                                         regulator-always-on;
 501                                         anatop-reg-offset = <0x140>;
 502                                         anatop-vol-bit-shift = <18>;
 503                                         anatop-vol-bit-width = <5>;
 504                                         anatop-delay-reg-offset = <0x170>;
 505                                         anatop-delay-bit-shift = <28>;
 506                                         anatop-delay-bit-width = <2>;
 507                                         anatop-min-bit-val = <1>;
 508                                         anatop-min-voltage = <725000>;
 509                                         anatop-max-voltage = <1450000>;
 510                                 };
 511                         };
 512
 513                         usbphy1: usbphy@020c9000 {
 514                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 515                                 reg = <0x020c9000 0x1000>;
 516                                 interrupts = <0 44 0x04>;
 517                                 clocks = <&clks 182>;
 518                         };
 519
 520                         usbphy2: usbphy@020ca000 {
 521                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 522                                 reg = <0x020ca000 0x1000>;
 523                                 interrupts = <0 45 0x04>;
 524                                 clocks = <&clks 183>;
 525                         };
 526
 527                         snvs@020cc000 {
 528                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 529                                 #address-cells = <1>;
 530                                 #size-cells = <1>;
 531                                 ranges = <0 0x020cc000 0x4000>;
 532
 533                                 snvs-rtc-lp@34 {
 534                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 535                                         reg = <0x34 0x58>;
 536                                         interrupts = <0 19 0x04 0 20 0x04>;
 537                                 };
 538                         };
 539
 540                         epit1: epit@020d0000 { /* EPIT1 */
 541                                 reg = <0x020d0000 0x4000>;
 542                                 interrupts = <0 56 0x04>;
 543                         };
 544
 545                         epit2: epit@020d4000 { /* EPIT2 */
 546                                 reg = <0x020d4000 0x4000>;
 547                                 interrupts = <0 57 0x04>;
 548                         };
 549
 550                         src: src@020d8000 {
 551                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 552                                 reg = <0x020d8000 0x4000>;
 553                                 interrupts = <0 91 0x04 0 96 0x04>;
 554                                 #reset-cells = <1>;
 555                         };
 556
 557                         gpc: gpc@020dc000 {
 558                                 compatible = "fsl,imx6q-gpc";
 559                                 reg = <0x020dc000 0x4000>;
 560                                 interrupts = <0 89 0x04 0 90 0x04>;
 561                         };
 562
 563                         gpr: iomuxc-gpr@020e0000 {
 564                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 565                                 reg = <0x020e0000 0x38>;
 566                         };
 567
 568                         ldb: ldb@020e0008 {
 569                                 #address-cells = <1>;
 570                                 #size-cells = <0>;
 571                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 572                                 gpr = <&gpr>;
 573                                 status = "disabled";
 574
 575                                 lvds-channel@0 {
 576                                         reg = <0>;
 577                                         crtcs = <&ipu1 0>;
 578                                         status = "disabled";
 579                                 };
 580
 581                                 lvds-channel@1 {
 582                                         reg = <1>;
 583                                         crtcs = <&ipu1 1>;
 584                                         status = "disabled";
 585                                 };
 586                         };
 587
 588                         dcic1: dcic@020e4000 {
 589                                 reg = <0x020e4000 0x4000>;
 590                                 interrupts = <0 124 0x04>;
 591                         };
 592
 593                         dcic2: dcic@020e8000 {
 594                                 reg = <0x020e8000 0x4000>;
 595                                 interrupts = <0 125 0x04>;
 596                         };
 597
 598                         sdma: sdma@020ec000 {
 599                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 600                                 reg = <0x020ec000 0x4000>;
 601                                 interrupts = <0 2 0x04>;
 602                                 clocks = <&clks 155>, <&clks 155>;
 603                                 clock-names = "ipg", "ahb";
 604                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 605                         };
 606                 };
 607
 608                 aips-bus@02100000 { /* AIPS2 */
 609                         compatible = "fsl,aips-bus", "simple-bus";
 610                         #address-cells = <1>;
 611                         #size-cells = <1>;
 612                         reg = <0x02100000 0x100000>;
 613                         ranges;
 614
 615                         caam@02100000 {
 616                                 reg = <0x02100000 0x40000>;
 617                                 interrupts = <0 105 0x04 0 106 0x04>;
 618                         };
 619
 620                         aipstz@0217c000 { /* AIPSTZ2 */
 621                                 reg = <0x0217c000 0x4000>;
 622                         };
 623
 624                         usbotg: usb@02184000 {
 625                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 626                                 reg = <0x02184000 0x200>;
 627                                 interrupts = <0 43 0x04>;
 628                                 clocks = <&clks 162>;
 629                                 fsl,usbphy = <&usbphy1>;
 630                                 fsl,usbmisc = <&usbmisc 0>;
 631                                 status = "disabled";
 632                         };
 633
 634                         usbh1: usb@02184200 {
 635                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 636                                 reg = <0x02184200 0x200>;
 637                                 interrupts = <0 40 0x04>;
 638                                 clocks = <&clks 162>;
 639                                 fsl,usbphy = <&usbphy2>;
 640                                 fsl,usbmisc = <&usbmisc 1>;
 641                                 status = "disabled";
 642                         };
 643
 644                         usbh2: usb@02184400 {
 645                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 646                                 reg = <0x02184400 0x200>;
 647                                 interrupts = <0 41 0x04>;
 648                                 clocks = <&clks 162>;
 649                                 fsl,usbmisc = <&usbmisc 2>;
 650                                 status = "disabled";
 651                         };
 652
 653                         usbh3: usb@02184600 {
 654                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 655                                 reg = <0x02184600 0x200>;
 656                                 interrupts = <0 42 0x04>;
 657                                 clocks = <&clks 162>;
 658                                 fsl,usbmisc = <&usbmisc 3>;
 659                                 status = "disabled";
 660                         };
 661
 662                         usbmisc: usbmisc@02184800 {
 663                                 #index-cells = <1>;
 664                                 compatible = "fsl,imx6q-usbmisc";
 665                                 reg = <0x02184800 0x200>;
 666                                 clocks = <&clks 162>;
 667                         };
 668
 669                         fec: ethernet@02188000 {
 670                                 compatible = "fsl,imx6q-fec";
 671                                 reg = <0x02188000 0x4000>;
 672                                 interrupts = <0 118 0x04 0 119 0x04>;
 673                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
 674                                 clock-names = "ipg", "ahb", "ptp";
 675                                 status = "disabled";
 676                         };
 677
 678                         mlb@0218c000 {
 679                                 reg = <0x0218c000 0x4000>;
 680                                 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
 681                         };
 682
 683                         usdhc1: usdhc@02190000 {
 684                                 compatible = "fsl,imx6q-usdhc";
 685                                 reg = <0x02190000 0x4000>;
 686                                 interrupts = <0 22 0x04>;
 687                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
 688                                 clock-names = "ipg", "ahb", "per";
 689                                 bus-width = <4>;
 690                                 status = "disabled";
 691                         };
 692
 693                         usdhc2: usdhc@02194000 {
 694                                 compatible = "fsl,imx6q-usdhc";
 695                                 reg = <0x02194000 0x4000>;
 696                                 interrupts = <0 23 0x04>;
 697                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
 698                                 clock-names = "ipg", "ahb", "per";
 699                                 bus-width = <4>;
 700                                 status = "disabled";
 701                         };
 702
 703                         usdhc3: usdhc@02198000 {
 704                                 compatible = "fsl,imx6q-usdhc";
 705                                 reg = <0x02198000 0x4000>;
 706                                 interrupts = <0 24 0x04>;
 707                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
 708                                 clock-names = "ipg", "ahb", "per";
 709                                 bus-width = <4>;
 710                                 status = "disabled";
 711                         };
 712
 713                         usdhc4: usdhc@0219c000 {
 714                                 compatible = "fsl,imx6q-usdhc";
 715                                 reg = <0x0219c000 0x4000>;
 716                                 interrupts = <0 25 0x04>;
 717                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
 718                                 clock-names = "ipg", "ahb", "per";
 719                                 bus-width = <4>;
 720                                 status = "disabled";
 721                         };
 722
 723                         i2c1: i2c@021a0000 {
 724                                 #address-cells = <1>;
 725                                 #size-cells = <0>;
 726                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 727                                 reg = <0x021a0000 0x4000>;
 728                                 interrupts = <0 36 0x04>;
 729                                 clocks = <&clks 125>;
 730                                 status = "disabled";
 731                         };
 732
 733                         i2c2: i2c@021a4000 {
 734                                 #address-cells = <1>;
 735                                 #size-cells = <0>;
 736                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 737                                 reg = <0x021a4000 0x4000>;
 738                                 interrupts = <0 37 0x04>;
 739                                 clocks = <&clks 126>;
 740                                 status = "disabled";
 741                         };
 742
 743                         i2c3: i2c@021a8000 {
 744                                 #address-cells = <1>;
 745                                 #size-cells = <0>;
 746                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 747                                 reg = <0x021a8000 0x4000>;
 748                                 interrupts = <0 38 0x04>;
 749                                 clocks = <&clks 127>;
 750                                 status = "disabled";
 751                         };
 752
 753                         romcp@021ac000 {
 754                                 reg = <0x021ac000 0x4000>;
 755                         };
 756
 757                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 758                                 compatible = "fsl,imx6q-mmdc";
 759                                 reg = <0x021b0000 0x4000>;
 760                         };
 761
 762                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 763                                 reg = <0x021b4000 0x4000>;
 764                         };
 765
 766                         weim: weim@021b8000 {
 767                                 compatible = "fsl,imx6q-weim";
 768                                 reg = <0x021b8000 0x4000>;
 769                                 interrupts = <0 14 0x04>;
 770                                 clocks = <&clks 196>;
 771                         };
 772
 773                         ocotp@021bc000 {
 774                                 compatible = "fsl,imx6q-ocotp";
 775                                 reg = <0x021bc000 0x4000>;
 776                         };
 777
 778                         tzasc@021d0000 { /* TZASC1 */
 779                                 reg = <0x021d0000 0x4000>;
 780                                 interrupts = <0 108 0x04>;
 781                         };
 782
 783                         tzasc@021d4000 { /* TZASC2 */
 784                                 reg = <0x021d4000 0x4000>;
 785                                 interrupts = <0 109 0x04>;
 786                         };
 787
 788                         audmux: audmux@021d8000 {
 789                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 790                                 reg = <0x021d8000 0x4000>;
 791                                 status = "disabled";
 792                         };
 793
 794                         mipi@021dc000 { /* MIPI-CSI */
 795                                 reg = <0x021dc000 0x4000>;
 796                         };
 797
 798                         mipi@021e0000 { /* MIPI-DSI */
 799                                 reg = <0x021e0000 0x4000>;
 800                         };
 801
 802                         vdoa@021e4000 {
 803                                 reg = <0x021e4000 0x4000>;
 804                                 interrupts = <0 18 0x04>;
 805                         };
 806
 807                         uart2: serial@021e8000 {
 808                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 809                                 reg = <0x021e8000 0x4000>;
 810                                 interrupts = <0 27 0x04>;
 811                                 clocks = <&clks 160>, <&clks 161>;
 812                                 clock-names = "ipg", "per";
 813                                 status = "disabled";
 814                         };
 815
 816                         uart3: serial@021ec000 {
 817                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 818                                 reg = <0x021ec000 0x4000>;
 819                                 interrupts = <0 28 0x04>;
 820                                 clocks = <&clks 160>, <&clks 161>;
 821                                 clock-names = "ipg", "per";
 822                                 status = "disabled";
 823                         };
 824
 825                         uart4: serial@021f0000 {
 826                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 827                                 reg = <0x021f0000 0x4000>;
 828                                 interrupts = <0 29 0x04>;
 829                                 clocks = <&clks 160>, <&clks 161>;
 830                                 clock-names = "ipg", "per";
 831                                 status = "disabled";
 832                         };
 833
 834                         uart5: serial@021f4000 {
 835                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 836                                 reg = <0x021f4000 0x4000>;
 837                                 interrupts = <0 30 0x04>;
 838                                 clocks = <&clks 160>, <&clks 161>;
 839                                 clock-names = "ipg", "per";
 840                                 status = "disabled";
 841                         };
 842                 };
 843
 844                 ipu1: ipu@02400000 {
 845                         #crtc-cells = <1>;
 846                         compatible = "fsl,imx6q-ipu";
 847                         reg = <0x02400000 0x400000>;
 848                         interrupts = <0 6 0x4 0 5 0x4>;
 849                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
 850                         clock-names = "bus", "di0", "di1";
 851                         resets = <&src 2>;
 852                 };
 853         };
 854 };