arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/clock/imx6qdl-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15
  16 #include "skeleton.dtsi"
  17
  18 / {
  19         aliases {
  20                 ethernet0 = &fec;
  21                 can0 = &can1;
  22                 can1 = &can2;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 gpio5 = &gpio6;
  29                 gpio6 = &gpio7;
  30                 i2c0 = &i2c1;
  31                 i2c1 = &i2c2;
  32                 i2c2 = &i2c3;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 mmc2 = &usdhc3;
  36                 mmc3 = &usdhc4;
  37                 serial0 = &uart1;
  38                 serial1 = &uart2;
  39                 serial2 = &uart3;
  40                 serial3 = &uart4;
  41                 serial4 = &uart5;
  42                 spi0 = &ecspi1;
  43                 spi1 = &ecspi2;
  44                 spi2 = &ecspi3;
  45                 spi3 = &ecspi4;
  46                 usbphy0 = &usbphy1;
  47                 usbphy1 = &usbphy2;
  48         };
  49
  50         intc: interrupt-controller@00a01000 {
  51                 compatible = "arm,cortex-a9-gic";
  52                 #interrupt-cells = <3>;
  53                 interrupt-controller;
  54                 reg = <0x00a01000 0x1000>,
  55                       <0x00a00100 0x100>;
  56         };
  57
  58         clocks {
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61
  62                 ckil {
  63                         compatible = "fsl,imx-ckil", "fixed-clock";
  64                         #clock-cells = <0>;
  65                         clock-frequency = <32768>;
  66                 };
  67
  68                 ckih1 {
  69                         compatible = "fsl,imx-ckih1", "fixed-clock";
  70                         #clock-cells = <0>;
  71                         clock-frequency = <0>;
  72                 };
  73
  74                 osc {
  75                         compatible = "fsl,imx-osc", "fixed-clock";
  76                         #clock-cells = <0>;
  77                         clock-frequency = <24000000>;
  78                 };
  79         };
  80
  81         soc {
  82                 #address-cells = <1>;
  83                 #size-cells = <1>;
  84                 compatible = "simple-bus";
  85                 interrupt-parent = <&intc>;
  86                 ranges;
  87
  88                 dma_apbh: dma-apbh@00110000 {
  89                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  90                         reg = <0x00110000 0x2000>;
  91                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
  94                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
  95                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  96                         #dma-cells = <1>;
  97                         dma-channels = <4>;
  98                         clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
  99                 };
 100
 101                 gpmi: gpmi-nand@00112000 {
 102                         compatible = "fsl,imx6q-gpmi-nand";
 103                         #address-cells = <1>;
 104                         #size-cells = <1>;
 105                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 106                         reg-names = "gpmi-nand", "bch";
 107                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 108                         interrupt-names = "bch";
 109                         clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
 110                                  <&clks IMX6QDL_CLK_GPMI_APB>,
 111                                  <&clks IMX6QDL_CLK_GPMI_BCH>,
 112                                  <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
 113                                  <&clks IMX6QDL_CLK_PER1_BCH>;
 114                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 115                                       "gpmi_bch_apb", "per1_bch";
 116                         dmas = <&dma_apbh 0>;
 117                         dma-names = "rx-tx";
 118                         status = "disabled";
 119                 };
 120
 121                 timer@00a00600 {
 122                         compatible = "arm,cortex-a9-twd-timer";
 123                         reg = <0x00a00600 0x20>;
 124                         interrupts = <1 13 0xf01>;
 125                         clocks = <&clks IMX6QDL_CLK_TWD>;
 126                 };
 127
 128                 L2: l2-cache@00a02000 {
 129                         compatible = "arm,pl310-cache";
 130                         reg = <0x00a02000 0x1000>;
 131                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 132                         cache-unified;
 133                         cache-level = <2>;
 134                         arm,tag-latency = <4 2 3>;
 135                         arm,data-latency = <4 2 3>;
 136                 };
 137
 138                 pcie: pcie@0x01000000 {
 139                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 140                         reg = <0x01ffc000 0x4000>; /* DBI */
 141                         #address-cells = <3>;
 142                         #size-cells = <2>;
 143                         device_type = "pci";
 144                         ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
 145                                   0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 146                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 147                         num-lanes = <1>;
 148                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 149                         interrupt-names = "msi";
 150                         #interrupt-cells = <1>;
 151                         interrupt-map-mask = <0 0 0 0x7>;
 152                         interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 153                                         <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 154                                         <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 155                                         <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 156                         clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
 157                                  <&clks IMX6QDL_CLK_LVDS1_GATE>,
 158                                  <&clks IMX6QDL_CLK_PCIE_REF_125M>;
 159                         clock-names = "pcie", "pcie_bus", "pcie_phy";
 160                         status = "disabled";
 161                 };
 162
 163                 pmu {
 164                         compatible = "arm,cortex-a9-pmu";
 165                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 166                 };
 167
 168                 aips-bus@02000000 { /* AIPS1 */
 169                         compatible = "fsl,aips-bus", "simple-bus";
 170                         #address-cells = <1>;
 171                         #size-cells = <1>;
 172                         reg = <0x02000000 0x100000>;
 173                         ranges;
 174
 175                         spba-bus@02000000 {
 176                                 compatible = "fsl,spba-bus", "simple-bus";
 177                                 #address-cells = <1>;
 178                                 #size-cells = <1>;
 179                                 reg = <0x02000000 0x40000>;
 180                                 ranges;
 181
 182                                 spdif: spdif@02004000 {
 183                                         compatible = "fsl,imx35-spdif";
 184                                         reg = <0x02004000 0x4000>;
 185                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 186                                         dmas = <&sdma 14 18 0>,
 187                                                <&sdma 15 18 0>;
 188                                         dma-names = "rx", "tx";
 189                                         clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
 190                                                  <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
 191                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
 192                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
 193                                                  <&clks IMX6QDL_CLK_DUMMY>;
 194                                         clock-names = "core",  "rxtx0",
 195                                                       "rxtx1", "rxtx2",
 196                                                       "rxtx3", "rxtx4",
 197                                                       "rxtx5", "rxtx6",
 198                                                       "rxtx7";
 199                                         status = "disabled";
 200                                 };
 201
 202                                 ecspi1: ecspi@02008000 {
 203                                         #address-cells = <1>;
 204                                         #size-cells = <0>;
 205                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 206                                         reg = <0x02008000 0x4000>;
 207                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 208                                         clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 209                                                  <&clks IMX6QDL_CLK_ECSPI1>;
 210                                         clock-names = "ipg", "per";
 211                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 212                                         dma-names = "rx", "tx";
 213                                         status = "disabled";
 214                                 };
 215
 216                                 ecspi2: ecspi@0200c000 {
 217                                         #address-cells = <1>;
 218                                         #size-cells = <0>;
 219                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 220                                         reg = <0x0200c000 0x4000>;
 221                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 222                                         clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 223                                                  <&clks IMX6QDL_CLK_ECSPI2>;
 224                                         clock-names = "ipg", "per";
 225                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 226                                         dma-names = "rx", "tx";
 227                                         status = "disabled";
 228                                 };
 229
 230                                 ecspi3: ecspi@02010000 {
 231                                         #address-cells = <1>;
 232                                         #size-cells = <0>;
 233                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 234                                         reg = <0x02010000 0x4000>;
 235                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 236                                         clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 237                                                  <&clks IMX6QDL_CLK_ECSPI3>;
 238                                         clock-names = "ipg", "per";
 239                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 240                                         dma-names = "rx", "tx";
 241                                         status = "disabled";
 242                                 };
 243
 244                                 ecspi4: ecspi@02014000 {
 245                                         #address-cells = <1>;
 246                                         #size-cells = <0>;
 247                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 248                                         reg = <0x02014000 0x4000>;
 249                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 250                                         clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 251                                                  <&clks IMX6QDL_CLK_ECSPI4>;
 252                                         clock-names = "ipg", "per";
 253                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 254                                         dma-names = "rx", "tx";
 255                                         status = "disabled";
 256                                 };
 257
 258                                 uart1: serial@02020000 {
 259                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 260                                         reg = <0x02020000 0x4000>;
 261                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 262                                         clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 263                                                  <&clks IMX6QDL_CLK_UART_SERIAL>;
 264                                         clock-names = "ipg", "per";
 265                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 266                                         dma-names = "rx", "tx";
 267                                         status = "disabled";
 268                                 };
 269
 270                                 esai: esai@02024000 {
 271                                         reg = <0x02024000 0x4000>;
 272                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 273                                 };
 274
 275                                 ssi1: ssi@02028000 {
 276                                         compatible = "fsl,imx6q-ssi",
 277                                                         "fsl,imx51-ssi",
 278                                                         "fsl,imx21-ssi";
 279                                         reg = <0x02028000 0x4000>;
 280                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 281                                         clocks = <&clks IMX6QDL_CLK_SSI1_IPG>;
 282                                         dmas = <&sdma 37 1 0>,
 283                                                <&sdma 38 1 0>;
 284                                         dma-names = "rx", "tx";
 285                                         fsl,fifo-depth = <15>;
 286                                         status = "disabled";
 287                                 };
 288
 289                                 ssi2: ssi@0202c000 {
 290                                         compatible = "fsl,imx6q-ssi",
 291                                                         "fsl,imx51-ssi",
 292                                                         "fsl,imx21-ssi";
 293                                         reg = <0x0202c000 0x4000>;
 294                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 295                                         clocks = <&clks IMX6QDL_CLK_SSI2_IPG>;
 296                                         dmas = <&sdma 41 1 0>,
 297                                                <&sdma 42 1 0>;
 298                                         dma-names = "rx", "tx";
 299                                         fsl,fifo-depth = <15>;
 300                                         status = "disabled";
 301                                 };
 302
 303                                 ssi3: ssi@02030000 {
 304                                         compatible = "fsl,imx6q-ssi",
 305                                                         "fsl,imx51-ssi",
 306                                                         "fsl,imx21-ssi";
 307                                         reg = <0x02030000 0x4000>;
 308                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 309                                         clocks = <&clks IMX6QDL_CLK_SSI3_IPG>;
 310                                         dmas = <&sdma 45 1 0>,
 311                                                <&sdma 46 1 0>;
 312                                         dma-names = "rx", "tx";
 313                                         fsl,fifo-depth = <15>;
 314                                         status = "disabled";
 315                                 };
 316
 317                                 asrc: asrc@02034000 {
 318                                         reg = <0x02034000 0x4000>;
 319                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 320                                 };
 321
 322                                 spba@0203c000 {
 323                                         reg = <0x0203c000 0x4000>;
 324                                 };
 325                         };
 326
 327                         vpu: vpu@02040000 {
 328                                 reg = <0x02040000 0x3c000>;
 329                                 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
 330                                              <0 12 IRQ_TYPE_LEVEL_HIGH>;
 331                         };
 332
 333                         aipstz@0207c000 { /* AIPSTZ1 */
 334                                 reg = <0x0207c000 0x4000>;
 335                         };
 336
 337                         pwm1: pwm@02080000 {
 338                                 #pwm-cells = <2>;
 339                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 340                                 reg = <0x02080000 0x4000>;
 341                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 342                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 343                                          <&clks IMX6QDL_CLK_PWM1>;
 344                                 clock-names = "ipg", "per";
 345                         };
 346
 347                         pwm2: pwm@02084000 {
 348                                 #pwm-cells = <2>;
 349                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 350                                 reg = <0x02084000 0x4000>;
 351                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 352                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 353                                          <&clks IMX6QDL_CLK_PWM2>;
 354                                 clock-names = "ipg", "per";
 355                         };
 356
 357                         pwm3: pwm@02088000 {
 358                                 #pwm-cells = <2>;
 359                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 360                                 reg = <0x02088000 0x4000>;
 361                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 362                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 363                                          <&clks IMX6QDL_CLK_PWM3>;
 364                                 clock-names = "ipg", "per";
 365                         };
 366
 367                         pwm4: pwm@0208c000 {
 368                                 #pwm-cells = <2>;
 369                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 370                                 reg = <0x0208c000 0x4000>;
 371                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 372                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 373                                          <&clks IMX6QDL_CLK_PWM4>;
 374                                 clock-names = "ipg", "per";
 375                         };
 376
 377                         can1: flexcan@02090000 {
 378                                 compatible = "fsl,imx6q-flexcan";
 379                                 reg = <0x02090000 0x4000>;
 380                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 381                                 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
 382                                          <&clks IMX6QDL_CLK_CAN1_SERIAL>;
 383                                 clock-names = "ipg", "per";
 384                                 status = "disabled";
 385                         };
 386
 387                         can2: flexcan@02094000 {
 388                                 compatible = "fsl,imx6q-flexcan";
 389                                 reg = <0x02094000 0x4000>;
 390                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 391                                 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
 392                                          <&clks IMX6QDL_CLK_CAN2_SERIAL>;
 393                                 clock-names = "ipg", "per";
 394                                 status = "disabled";
 395                         };
 396
 397                         gpt: gpt@02098000 {
 398                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 399                                 reg = <0x02098000 0x4000>;
 400                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 401                                 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
 402                                          <&clks IMX6QDL_CLK_GPT_IPG_PER>;
 403                                 clock-names = "ipg", "per";
 404                         };
 405
 406                         gpio1: gpio@0209c000 {
 407                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 408                                 reg = <0x0209c000 0x4000>;
 409                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 410                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 411                                 gpio-controller;
 412                                 #gpio-cells = <2>;
 413                                 interrupt-controller;
 414                                 #interrupt-cells = <2>;
 415                         };
 416
 417                         gpio2: gpio@020a0000 {
 418                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 419                                 reg = <0x020a0000 0x4000>;
 420                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 421                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 422                                 gpio-controller;
 423                                 #gpio-cells = <2>;
 424                                 interrupt-controller;
 425                                 #interrupt-cells = <2>;
 426                         };
 427
 428                         gpio3: gpio@020a4000 {
 429                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 430                                 reg = <0x020a4000 0x4000>;
 431                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 432                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 433                                 gpio-controller;
 434                                 #gpio-cells = <2>;
 435                                 interrupt-controller;
 436                                 #interrupt-cells = <2>;
 437                         };
 438
 439                         gpio4: gpio@020a8000 {
 440                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 441                                 reg = <0x020a8000 0x4000>;
 442                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 443                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 444                                 gpio-controller;
 445                                 #gpio-cells = <2>;
 446                                 interrupt-controller;
 447                                 #interrupt-cells = <2>;
 448                         };
 449
 450                         gpio5: gpio@020ac000 {
 451                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 452                                 reg = <0x020ac000 0x4000>;
 453                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 454                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 455                                 gpio-controller;
 456                                 #gpio-cells = <2>;
 457                                 interrupt-controller;
 458                                 #interrupt-cells = <2>;
 459                         };
 460
 461                         gpio6: gpio@020b0000 {
 462                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 463                                 reg = <0x020b0000 0x4000>;
 464                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 465                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 466                                 gpio-controller;
 467                                 #gpio-cells = <2>;
 468                                 interrupt-controller;
 469                                 #interrupt-cells = <2>;
 470                         };
 471
 472                         gpio7: gpio@020b4000 {
 473                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 474                                 reg = <0x020b4000 0x4000>;
 475                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 476                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 477                                 gpio-controller;
 478                                 #gpio-cells = <2>;
 479                                 interrupt-controller;
 480                                 #interrupt-cells = <2>;
 481                         };
 482
 483                         kpp: kpp@020b8000 {
 484                                 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
 485                                 reg = <0x020b8000 0x4000>;
 486                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 487                                 clocks = <&clks IMX6QDL_CLK_IPG>;
 488                         };
 489
 490                         wdog1: wdog@020bc000 {
 491                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 492                                 reg = <0x020bc000 0x4000>;
 493                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 494                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 495                         };
 496
 497                         wdog2: wdog@020c0000 {
 498                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 499                                 reg = <0x020c0000 0x4000>;
 500                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 501                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 502                                 status = "disabled";
 503                         };
 504
 505                         clks: ccm@020c4000 {
 506                                 compatible = "fsl,imx6q-ccm";
 507                                 reg = <0x020c4000 0x4000>;
 508                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 509                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 510                                 #clock-cells = <1>;
 511                         };
 512
 513                         anatop: anatop@020c8000 {
 514                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 515                                 reg = <0x020c8000 0x1000>;
 516                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 517                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 518                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 519
 520                                 regulator-1p1@110 {
 521                                         compatible = "fsl,anatop-regulator";
 522                                         regulator-name = "vdd1p1";
 523                                         regulator-min-microvolt = <800000>;
 524                                         regulator-max-microvolt = <1375000>;
 525                                         regulator-always-on;
 526                                         anatop-reg-offset = <0x110>;
 527                                         anatop-vol-bit-shift = <8>;
 528                                         anatop-vol-bit-width = <5>;
 529                                         anatop-min-bit-val = <4>;
 530                                         anatop-min-voltage = <800000>;
 531                                         anatop-max-voltage = <1375000>;
 532                                 };
 533
 534                                 regulator-3p0@120 {
 535                                         compatible = "fsl,anatop-regulator";
 536                                         regulator-name = "vdd3p0";
 537                                         regulator-min-microvolt = <2800000>;
 538                                         regulator-max-microvolt = <3150000>;
 539                                         regulator-always-on;
 540                                         anatop-reg-offset = <0x120>;
 541                                         anatop-vol-bit-shift = <8>;
 542                                         anatop-vol-bit-width = <5>;
 543                                         anatop-min-bit-val = <0>;
 544                                         anatop-min-voltage = <2625000>;
 545                                         anatop-max-voltage = <3400000>;
 546                                 };
 547
 548                                 regulator-2p5@130 {
 549                                         compatible = "fsl,anatop-regulator";
 550                                         regulator-name = "vdd2p5";
 551                                         regulator-min-microvolt = <2000000>;
 552                                         regulator-max-microvolt = <2750000>;
 553                                         regulator-always-on;
 554                                         anatop-reg-offset = <0x130>;
 555                                         anatop-vol-bit-shift = <8>;
 556                                         anatop-vol-bit-width = <5>;
 557                                         anatop-min-bit-val = <0>;
 558                                         anatop-min-voltage = <2000000>;
 559                                         anatop-max-voltage = <2750000>;
 560                                 };
 561
 562                                 reg_arm: regulator-vddcore@140 {
 563                                         compatible = "fsl,anatop-regulator";
 564                                         regulator-name = "vddarm";
 565                                         regulator-min-microvolt = <725000>;
 566                                         regulator-max-microvolt = <1450000>;
 567                                         regulator-always-on;
 568                                         anatop-reg-offset = <0x140>;
 569                                         anatop-vol-bit-shift = <0>;
 570                                         anatop-vol-bit-width = <5>;
 571                                         anatop-delay-reg-offset = <0x170>;
 572                                         anatop-delay-bit-shift = <24>;
 573                                         anatop-delay-bit-width = <2>;
 574                                         anatop-min-bit-val = <1>;
 575                                         anatop-min-voltage = <725000>;
 576                                         anatop-max-voltage = <1450000>;
 577                                 };
 578
 579                                 reg_pu: regulator-vddpu@140 {
 580                                         compatible = "fsl,anatop-regulator";
 581                                         regulator-name = "vddpu";
 582                                         regulator-min-microvolt = <725000>;
 583                                         regulator-max-microvolt = <1450000>;
 584                                         regulator-always-on;
 585                                         anatop-reg-offset = <0x140>;
 586                                         anatop-vol-bit-shift = <9>;
 587                                         anatop-vol-bit-width = <5>;
 588                                         anatop-delay-reg-offset = <0x170>;
 589                                         anatop-delay-bit-shift = <26>;
 590                                         anatop-delay-bit-width = <2>;
 591                                         anatop-min-bit-val = <1>;
 592                                         anatop-min-voltage = <725000>;
 593                                         anatop-max-voltage = <1450000>;
 594                                 };
 595
 596                                 reg_soc: regulator-vddsoc@140 {
 597                                         compatible = "fsl,anatop-regulator";
 598                                         regulator-name = "vddsoc";
 599                                         regulator-min-microvolt = <725000>;
 600                                         regulator-max-microvolt = <1450000>;
 601                                         regulator-always-on;
 602                                         anatop-reg-offset = <0x140>;
 603                                         anatop-vol-bit-shift = <18>;
 604                                         anatop-vol-bit-width = <5>;
 605                                         anatop-delay-reg-offset = <0x170>;
 606                                         anatop-delay-bit-shift = <28>;
 607                                         anatop-delay-bit-width = <2>;
 608                                         anatop-min-bit-val = <1>;
 609                                         anatop-min-voltage = <725000>;
 610                                         anatop-max-voltage = <1450000>;
 611                                 };
 612                         };
 613
 614                         tempmon: tempmon {
 615                                 compatible = "fsl,imx6q-tempmon";
 616                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 617                                 fsl,tempmon = <&anatop>;
 618                                 fsl,tempmon-data = <&ocotp>;
 619                                 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 620                         };
 621
 622                         usbphy1: usbphy@020c9000 {
 623                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 624                                 reg = <0x020c9000 0x1000>;
 625                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 626                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 627                                 fsl,anatop = <&anatop>;
 628                         };
 629
 630                         usbphy2: usbphy@020ca000 {
 631                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 632                                 reg = <0x020ca000 0x1000>;
 633                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 634                                 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
 635                                 fsl,anatop = <&anatop>;
 636                         };
 637
 638                         snvs@020cc000 {
 639                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 640                                 #address-cells = <1>;
 641                                 #size-cells = <1>;
 642                                 ranges = <0 0x020cc000 0x4000>;
 643
 644                                 snvs-rtc-lp@34 {
 645                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 646                                         reg = <0x34 0x58>;
 647                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 648                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 649                                 };
 650                         };
 651
 652                         epit1: epit@020d0000 { /* EPIT1 */
 653                                 reg = <0x020d0000 0x4000>;
 654                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 655                         };
 656
 657                         epit2: epit@020d4000 { /* EPIT2 */
 658                                 reg = <0x020d4000 0x4000>;
 659                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 660                         };
 661
 662                         src: src@020d8000 {
 663                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 664                                 reg = <0x020d8000 0x4000>;
 665                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 666                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 667                                 #reset-cells = <1>;
 668                         };
 669
 670                         gpc: gpc@020dc000 {
 671                                 compatible = "fsl,imx6q-gpc";
 672                                 reg = <0x020dc000 0x4000>;
 673                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 674                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 675                         };
 676
 677                         gpr: iomuxc-gpr@020e0000 {
 678                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 679                                 reg = <0x020e0000 0x38>;
 680                         };
 681
 682                         iomuxc: iomuxc@020e0000 {
 683                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 684                                 reg = <0x020e0000 0x4000>;
 685                         };
 686
 687                         ldb: ldb@020e0008 {
 688                                 #address-cells = <1>;
 689                                 #size-cells = <0>;
 690                                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
 691                                 gpr = <&gpr>;
 692                                 status = "disabled";
 693
 694                                 lvds-channel@0 {
 695                                         #address-cells = <1>;
 696                                         #size-cells = <0>;
 697                                         reg = <0>;
 698                                         status = "disabled";
 699
 700                                         port@0 {
 701                                                 reg = <0>;
 702
 703                                                 lvds0_mux_0: endpoint {
 704                                                         remote-endpoint = <&ipu1_di0_lvds0>;
 705                                                 };
 706                                         };
 707
 708                                         port@1 {
 709                                                 reg = <1>;
 710
 711                                                 lvds0_mux_1: endpoint {
 712                                                         remote-endpoint = <&ipu1_di1_lvds0>;
 713                                                 };
 714                                         };
 715                                 };
 716
 717                                 lvds-channel@1 {
 718                                         #address-cells = <1>;
 719                                         #size-cells = <0>;
 720                                         reg = <1>;
 721                                         status = "disabled";
 722
 723                                         port@0 {
 724                                                 reg = <0>;
 725
 726                                                 lvds1_mux_0: endpoint {
 727                                                         remote-endpoint = <&ipu1_di0_lvds1>;
 728                                                 };
 729                                         };
 730
 731                                         port@1 {
 732                                                 reg = <1>;
 733
 734                                                 lvds1_mux_1: endpoint {
 735                                                         remote-endpoint = <&ipu1_di1_lvds1>;
 736                                                 };
 737                                         };
 738                                 };
 739                         };
 740
 741                         hdmi: hdmi@0120000 {
 742                                 #address-cells = <1>;
 743                                 #size-cells = <0>;
 744                                 reg = <0x00120000 0x9000>;
 745                                 interrupts = <0 115 0x04>;
 746                                 gpr = <&gpr>;
 747                                 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
 748                                          <&clks IMX6QDL_CLK_HDMI_ISFR>;
 749                                 clock-names = "iahb", "isfr";
 750                                 status = "disabled";
 751
 752                                 port@0 {
 753                                         reg = <0>;
 754
 755                                         hdmi_mux_0: endpoint {
 756                                                 remote-endpoint = <&ipu1_di0_hdmi>;
 757                                         };
 758                                 };
 759
 760                                 port@1 {
 761                                         reg = <1>;
 762
 763                                         hdmi_mux_1: endpoint {
 764                                                 remote-endpoint = <&ipu1_di1_hdmi>;
 765                                         };
 766                                 };
 767                         };
 768
 769                         dcic1: dcic@020e4000 {
 770                                 reg = <0x020e4000 0x4000>;
 771                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 772                         };
 773
 774                         dcic2: dcic@020e8000 {
 775                                 reg = <0x020e8000 0x4000>;
 776                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 777                         };
 778
 779                         sdma: sdma@020ec000 {
 780                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 781                                 reg = <0x020ec000 0x4000>;
 782                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 783                                 clocks = <&clks IMX6QDL_CLK_SDMA>,
 784                                          <&clks IMX6QDL_CLK_SDMA>;
 785                                 clock-names = "ipg", "ahb";
 786                                 #dma-cells = <3>;
 787                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 788                         };
 789                 };
 790
 791                 aips-bus@02100000 { /* AIPS2 */
 792                         compatible = "fsl,aips-bus", "simple-bus";
 793                         #address-cells = <1>;
 794                         #size-cells = <1>;
 795                         reg = <0x02100000 0x100000>;
 796                         ranges;
 797
 798                         caam@02100000 {
 799                                 reg = <0x02100000 0x40000>;
 800                                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
 801                                              <0 106 IRQ_TYPE_LEVEL_HIGH>;
 802                         };
 803
 804                         aipstz@0217c000 { /* AIPSTZ2 */
 805                                 reg = <0x0217c000 0x4000>;
 806                         };
 807
 808                         usbotg: usb@02184000 {
 809                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 810                                 reg = <0x02184000 0x200>;
 811                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 812                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 813                                 fsl,usbphy = <&usbphy1>;
 814                                 fsl,usbmisc = <&usbmisc 0>;
 815                                 status = "disabled";
 816                         };
 817
 818                         usbh1: usb@02184200 {
 819                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 820                                 reg = <0x02184200 0x200>;
 821                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 822                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 823                                 fsl,usbphy = <&usbphy2>;
 824                                 fsl,usbmisc = <&usbmisc 1>;
 825                                 status = "disabled";
 826                         };
 827
 828                         usbh2: usb@02184400 {
 829                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 830                                 reg = <0x02184400 0x200>;
 831                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 832                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 833                                 fsl,usbmisc = <&usbmisc 2>;
 834                                 status = "disabled";
 835                         };
 836
 837                         usbh3: usb@02184600 {
 838                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 839                                 reg = <0x02184600 0x200>;
 840                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 841                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 842                                 fsl,usbmisc = <&usbmisc 3>;
 843                                 status = "disabled";
 844                         };
 845
 846                         usbmisc: usbmisc@02184800 {
 847                                 #index-cells = <1>;
 848                                 compatible = "fsl,imx6q-usbmisc";
 849                                 reg = <0x02184800 0x200>;
 850                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 851                         };
 852
 853                         fec: ethernet@02188000 {
 854                                 compatible = "fsl,imx6q-fec";
 855                                 reg = <0x02188000 0x4000>;
 856                                 interrupts-extended =
 857                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
 858                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 859                                 clocks = <&clks IMX6QDL_CLK_ENET>,
 860                                          <&clks IMX6QDL_CLK_ENET>,
 861                                          <&clks IMX6QDL_CLK_ENET_REF>;
 862                                 clock-names = "ipg", "ahb", "ptp";
 863                                 status = "disabled";
 864                         };
 865
 866                         mlb@0218c000 {
 867                                 reg = <0x0218c000 0x4000>;
 868                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 869                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
 870                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
 871                         };
 872
 873                         usdhc1: usdhc@02190000 {
 874                                 compatible = "fsl,imx6q-usdhc";
 875                                 reg = <0x02190000 0x4000>;
 876                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 877                                 clocks = <&clks IMX6QDL_CLK_USDHC1>,
 878                                          <&clks IMX6QDL_CLK_USDHC1>,
 879                                          <&clks IMX6QDL_CLK_USDHC1>;
 880                                 clock-names = "ipg", "ahb", "per";
 881                                 bus-width = <4>;
 882                                 status = "disabled";
 883                         };
 884
 885                         usdhc2: usdhc@02194000 {
 886                                 compatible = "fsl,imx6q-usdhc";
 887                                 reg = <0x02194000 0x4000>;
 888                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 889                                 clocks = <&clks IMX6QDL_CLK_USDHC2>,
 890                                          <&clks IMX6QDL_CLK_USDHC2>,
 891                                          <&clks IMX6QDL_CLK_USDHC2>;
 892                                 clock-names = "ipg", "ahb", "per";
 893                                 bus-width = <4>;
 894                                 status = "disabled";
 895                         };
 896
 897                         usdhc3: usdhc@02198000 {
 898                                 compatible = "fsl,imx6q-usdhc";
 899                                 reg = <0x02198000 0x4000>;
 900                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 901                                 clocks = <&clks IMX6QDL_CLK_USDHC3>,
 902                                          <&clks IMX6QDL_CLK_USDHC3>,
 903                                          <&clks IMX6QDL_CLK_USDHC3>;
 904                                 clock-names = "ipg", "ahb", "per";
 905                                 bus-width = <4>;
 906                                 status = "disabled";
 907                         };
 908
 909                         usdhc4: usdhc@0219c000 {
 910                                 compatible = "fsl,imx6q-usdhc";
 911                                 reg = <0x0219c000 0x4000>;
 912                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 913                                 clocks = <&clks IMX6QDL_CLK_USDHC4>,
 914                                          <&clks IMX6QDL_CLK_USDHC4>,
 915                                          <&clks IMX6QDL_CLK_USDHC4>;
 916                                 clock-names = "ipg", "ahb", "per";
 917                                 bus-width = <4>;
 918                                 status = "disabled";
 919                         };
 920
 921                         i2c1: i2c@021a0000 {
 922                                 #address-cells = <1>;
 923                                 #size-cells = <0>;
 924                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 925                                 reg = <0x021a0000 0x4000>;
 926                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 927                                 clocks = <&clks IMX6QDL_CLK_I2C1>;
 928                                 status = "disabled";
 929                         };
 930
 931                         i2c2: i2c@021a4000 {
 932                                 #address-cells = <1>;
 933                                 #size-cells = <0>;
 934                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 935                                 reg = <0x021a4000 0x4000>;
 936                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 937                                 clocks = <&clks IMX6QDL_CLK_I2C2>;
 938                                 status = "disabled";
 939                         };
 940
 941                         i2c3: i2c@021a8000 {
 942                                 #address-cells = <1>;
 943                                 #size-cells = <0>;
 944                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 945                                 reg = <0x021a8000 0x4000>;
 946                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 947                                 clocks = <&clks IMX6QDL_CLK_I2C3>;
 948                                 status = "disabled";
 949                         };
 950
 951                         romcp@021ac000 {
 952                                 reg = <0x021ac000 0x4000>;
 953                         };
 954
 955                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 956                                 compatible = "fsl,imx6q-mmdc";
 957                                 reg = <0x021b0000 0x4000>;
 958                         };
 959
 960                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 961                                 reg = <0x021b4000 0x4000>;
 962                         };
 963
 964                         weim: weim@021b8000 {
 965                                 compatible = "fsl,imx6q-weim";
 966                                 reg = <0x021b8000 0x4000>;
 967                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 968                                 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
 969                         };
 970
 971                         ocotp: ocotp@021bc000 {
 972                                 compatible = "fsl,imx6q-ocotp", "syscon";
 973                                 reg = <0x021bc000 0x4000>;
 974                         };
 975
 976                         tzasc@021d0000 { /* TZASC1 */
 977                                 reg = <0x021d0000 0x4000>;
 978                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 979                         };
 980
 981                         tzasc@021d4000 { /* TZASC2 */
 982                                 reg = <0x021d4000 0x4000>;
 983                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 984                         };
 985
 986                         audmux: audmux@021d8000 {
 987                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 988                                 reg = <0x021d8000 0x4000>;
 989                                 status = "disabled";
 990                         };
 991
 992                         mipi_csi: mipi@021dc000 {
 993                                 reg = <0x021dc000 0x4000>;
 994                         };
 995
 996                         mipi_dsi: mipi@021e0000 {
 997                                 #address-cells = <1>;
 998                                 #size-cells = <0>;
 999                                 reg = <0x021e0000 0x4000>;
1000                                 status = "disabled";
1001
1002                                 port@0 {
1003                                         reg = <0>;
1004
1005                                         mipi_mux_0: endpoint {
1006                                                 remote-endpoint = <&ipu1_di0_mipi>;
1007                                         };
1008                                 };
1009
1010                                 port@1 {
1011                                         reg = <1>;
1012
1013                                         mipi_mux_1: endpoint {
1014                                                 remote-endpoint = <&ipu1_di1_mipi>;
1015                                         };
1016                                 };
1017                         };
1018
1019                         vdoa@021e4000 {
1020                                 reg = <0x021e4000 0x4000>;
1021                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1022                         };
1023
1024                         uart2: serial@021e8000 {
1025                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1026                                 reg = <0x021e8000 0x4000>;
1027                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1028                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1029                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1030                                 clock-names = "ipg", "per";
1031                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1032                                 dma-names = "rx", "tx";
1033                                 status = "disabled";
1034                         };
1035
1036                         uart3: serial@021ec000 {
1037                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1038                                 reg = <0x021ec000 0x4000>;
1039                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1040                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1041                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1042                                 clock-names = "ipg", "per";
1043                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1044                                 dma-names = "rx", "tx";
1045                                 status = "disabled";
1046                         };
1047
1048                         uart4: serial@021f0000 {
1049                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1050                                 reg = <0x021f0000 0x4000>;
1051                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1052                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1053                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1054                                 clock-names = "ipg", "per";
1055                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1056                                 dma-names = "rx", "tx";
1057                                 status = "disabled";
1058                         };
1059
1060                         uart5: serial@021f4000 {
1061                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1062                                 reg = <0x021f4000 0x4000>;
1063                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1064                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1065                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1066                                 clock-names = "ipg", "per";
1067                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1068                                 dma-names = "rx", "tx";
1069                                 status = "disabled";
1070                         };
1071                 };
1072
1073                 ipu1: ipu@02400000 {
1074                         #address-cells = <1>;
1075                         #size-cells = <0>;
1076                         compatible = "fsl,imx6q-ipu";
1077                         reg = <0x02400000 0x400000>;
1078                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1079                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1080                         clocks = <&clks IMX6QDL_CLK_IPU1>,
1081                                  <&clks IMX6QDL_CLK_IPU1_DI0>,
1082                                  <&clks IMX6QDL_CLK_IPU1_DI1>;
1083                         clock-names = "bus", "di0", "di1";
1084                         resets = <&src 2>;
1085
1086                         ipu1_csi0: port@0 {
1087                                 reg = <0>;
1088                         };
1089
1090                         ipu1_csi1: port@1 {
1091                                 reg = <1>;
1092                         };
1093
1094                         ipu1_di0: port@2 {
1095                                 #address-cells = <1>;
1096                                 #size-cells = <0>;
1097                                 reg = <2>;
1098
1099                                 ipu1_di0_disp0: endpoint@0 {
1100                                 };
1101
1102                                 ipu1_di0_hdmi: endpoint@1 {
1103                                         remote-endpoint = <&hdmi_mux_0>;
1104                                 };
1105
1106                                 ipu1_di0_mipi: endpoint@2 {
1107                                         remote-endpoint = <&mipi_mux_0>;
1108                                 };
1109
1110                                 ipu1_di0_lvds0: endpoint@3 {
1111                                         remote-endpoint = <&lvds0_mux_0>;
1112                                 };
1113
1114                                 ipu1_di0_lvds1: endpoint@4 {
1115                                         remote-endpoint = <&lvds1_mux_0>;
1116                                 };
1117                         };
1118
1119                         ipu1_di1: port@3 {
1120                                 #address-cells = <1>;
1121                                 #size-cells = <0>;
1122                                 reg = <3>;
1123
1124                                 ipu1_di0_disp1: endpoint@0 {
1125                                 };
1126
1127                                 ipu1_di1_hdmi: endpoint@1 {
1128                                         remote-endpoint = <&hdmi_mux_1>;
1129                                 };
1130
1131                                 ipu1_di1_mipi: endpoint@2 {
1132                                         remote-endpoint = <&mipi_mux_1>;
1133                                 };
1134
1135                                 ipu1_di1_lvds0: endpoint@3 {
1136                                         remote-endpoint = <&lvds0_mux_1>;
1137                                 };
1138
1139                                 ipu1_di1_lvds1: endpoint@4 {
1140                                         remote-endpoint = <&lvds1_mux_1>;
1141                                 };
1142                         };
1143                 };
1144         };
1145 };