2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <dt-bindings/clock/imx6qdl-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include "skeleton.dtsi"
50 intc: interrupt-controller@00a01000 {
51 compatible = "arm,cortex-a9-gic";
52 #interrupt-cells = <3>;
54 reg = <0x00a01000 0x1000>,
63 compatible = "fsl,imx-ckil", "fixed-clock";
65 clock-frequency = <32768>;
69 compatible = "fsl,imx-ckih1", "fixed-clock";
71 clock-frequency = <0>;
75 compatible = "fsl,imx-osc", "fixed-clock";
77 clock-frequency = <24000000>;
84 compatible = "simple-bus";
85 interrupt-parent = <&intc>;
88 dma_apbh: dma-apbh@00110000 {
89 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
90 reg = <0x00110000 0x2000>;
91 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
92 <0 13 IRQ_TYPE_LEVEL_HIGH>,
93 <0 13 IRQ_TYPE_LEVEL_HIGH>,
94 <0 13 IRQ_TYPE_LEVEL_HIGH>;
95 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
98 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
101 gpmi: gpmi-nand@00112000 {
102 compatible = "fsl,imx6q-gpmi-nand";
103 #address-cells = <1>;
105 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
106 reg-names = "gpmi-nand", "bch";
107 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
108 interrupt-names = "bch";
109 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
110 <&clks IMX6QDL_CLK_GPMI_APB>,
111 <&clks IMX6QDL_CLK_GPMI_BCH>,
112 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
113 <&clks IMX6QDL_CLK_PER1_BCH>;
114 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
115 "gpmi_bch_apb", "per1_bch";
116 dmas = <&dma_apbh 0>;
122 compatible = "arm,cortex-a9-twd-timer";
123 reg = <0x00a00600 0x20>;
124 interrupts = <1 13 0xf01>;
125 clocks = <&clks IMX6QDL_CLK_TWD>;
128 L2: l2-cache@00a02000 {
129 compatible = "arm,pl310-cache";
130 reg = <0x00a02000 0x1000>;
131 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
134 arm,tag-latency = <4 2 3>;
135 arm,data-latency = <4 2 3>;
138 pcie: pcie@0x01000000 {
139 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
140 reg = <0x01ffc000 0x04000>,
141 <0x01f00000 0x80000>;
142 reg-names = "dbi", "config";
143 #address-cells = <3>;
146 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
147 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
148 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
150 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-names = "msi";
152 #interrupt-cells = <1>;
153 interrupt-map-mask = <0 0 0 0x7>;
154 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
155 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
156 <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
157 <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
159 <&clks IMX6QDL_CLK_LVDS1_GATE>,
160 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
161 clock-names = "pcie", "pcie_bus", "pcie_phy";
166 compatible = "arm,cortex-a9-pmu";
167 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
170 aips-bus@02000000 { /* AIPS1 */
171 compatible = "fsl,aips-bus", "simple-bus";
172 #address-cells = <1>;
174 reg = <0x02000000 0x100000>;
178 compatible = "fsl,spba-bus", "simple-bus";
179 #address-cells = <1>;
181 reg = <0x02000000 0x40000>;
184 spdif: spdif@02004000 {
185 compatible = "fsl,imx35-spdif";
186 reg = <0x02004000 0x4000>;
187 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
188 dmas = <&sdma 14 18 0>,
190 dma-names = "rx", "tx";
191 clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
192 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
193 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
194 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
195 <&clks IMX6QDL_CLK_DUMMY>;
196 clock-names = "core", "rxtx0",
204 ecspi1: ecspi@02008000 {
205 #address-cells = <1>;
207 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
208 reg = <0x02008000 0x4000>;
209 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
211 <&clks IMX6QDL_CLK_ECSPI1>;
212 clock-names = "ipg", "per";
213 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
214 dma-names = "rx", "tx";
218 ecspi2: ecspi@0200c000 {
219 #address-cells = <1>;
221 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
222 reg = <0x0200c000 0x4000>;
223 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
225 <&clks IMX6QDL_CLK_ECSPI2>;
226 clock-names = "ipg", "per";
227 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
228 dma-names = "rx", "tx";
232 ecspi3: ecspi@02010000 {
233 #address-cells = <1>;
235 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
236 reg = <0x02010000 0x4000>;
237 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
239 <&clks IMX6QDL_CLK_ECSPI3>;
240 clock-names = "ipg", "per";
241 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
242 dma-names = "rx", "tx";
246 ecspi4: ecspi@02014000 {
247 #address-cells = <1>;
249 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
250 reg = <0x02014000 0x4000>;
251 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
253 <&clks IMX6QDL_CLK_ECSPI4>;
254 clock-names = "ipg", "per";
255 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
256 dma-names = "rx", "tx";
260 uart1: serial@02020000 {
261 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
262 reg = <0x02020000 0x4000>;
263 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
265 <&clks IMX6QDL_CLK_UART_SERIAL>;
266 clock-names = "ipg", "per";
267 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
268 dma-names = "rx", "tx";
272 esai: esai@02024000 {
273 reg = <0x02024000 0x4000>;
274 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
278 #sound-dai-cells = <0>;
279 compatible = "fsl,imx6q-ssi",
281 reg = <0x02028000 0x4000>;
282 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
284 <&clks IMX6QDL_CLK_SSI1>;
285 clock-names = "ipg", "baud";
286 dmas = <&sdma 37 1 0>,
288 dma-names = "rx", "tx";
289 fsl,fifo-depth = <15>;
294 #sound-dai-cells = <0>;
295 compatible = "fsl,imx6q-ssi",
297 reg = <0x0202c000 0x4000>;
298 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
300 <&clks IMX6QDL_CLK_SSI2>;
301 clock-names = "ipg", "baud";
302 dmas = <&sdma 41 1 0>,
304 dma-names = "rx", "tx";
305 fsl,fifo-depth = <15>;
310 #sound-dai-cells = <0>;
311 compatible = "fsl,imx6q-ssi",
313 reg = <0x02030000 0x4000>;
314 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
316 <&clks IMX6QDL_CLK_SSI3>;
317 clock-names = "ipg", "baud";
318 dmas = <&sdma 45 1 0>,
320 dma-names = "rx", "tx";
321 fsl,fifo-depth = <15>;
325 asrc: asrc@02034000 {
326 reg = <0x02034000 0x4000>;
327 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
331 reg = <0x0203c000 0x4000>;
336 reg = <0x02040000 0x3c000>;
337 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
338 <0 12 IRQ_TYPE_LEVEL_HIGH>;
341 aipstz@0207c000 { /* AIPSTZ1 */
342 reg = <0x0207c000 0x4000>;
347 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
348 reg = <0x02080000 0x4000>;
349 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&clks IMX6QDL_CLK_IPG>,
351 <&clks IMX6QDL_CLK_PWM1>;
352 clock-names = "ipg", "per";
357 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
358 reg = <0x02084000 0x4000>;
359 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&clks IMX6QDL_CLK_IPG>,
361 <&clks IMX6QDL_CLK_PWM2>;
362 clock-names = "ipg", "per";
367 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
368 reg = <0x02088000 0x4000>;
369 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clks IMX6QDL_CLK_IPG>,
371 <&clks IMX6QDL_CLK_PWM3>;
372 clock-names = "ipg", "per";
377 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
378 reg = <0x0208c000 0x4000>;
379 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&clks IMX6QDL_CLK_IPG>,
381 <&clks IMX6QDL_CLK_PWM4>;
382 clock-names = "ipg", "per";
385 can1: flexcan@02090000 {
386 compatible = "fsl,imx6q-flexcan";
387 reg = <0x02090000 0x4000>;
388 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
390 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
391 clock-names = "ipg", "per";
395 can2: flexcan@02094000 {
396 compatible = "fsl,imx6q-flexcan";
397 reg = <0x02094000 0x4000>;
398 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
400 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
401 clock-names = "ipg", "per";
406 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
407 reg = <0x02098000 0x4000>;
408 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
410 <&clks IMX6QDL_CLK_GPT_IPG_PER>;
411 clock-names = "ipg", "per";
414 gpio1: gpio@0209c000 {
415 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
416 reg = <0x0209c000 0x4000>;
417 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
418 <0 67 IRQ_TYPE_LEVEL_HIGH>;
421 interrupt-controller;
422 #interrupt-cells = <2>;
425 gpio2: gpio@020a0000 {
426 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
427 reg = <0x020a0000 0x4000>;
428 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
429 <0 69 IRQ_TYPE_LEVEL_HIGH>;
432 interrupt-controller;
433 #interrupt-cells = <2>;
436 gpio3: gpio@020a4000 {
437 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
438 reg = <0x020a4000 0x4000>;
439 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
440 <0 71 IRQ_TYPE_LEVEL_HIGH>;
443 interrupt-controller;
444 #interrupt-cells = <2>;
447 gpio4: gpio@020a8000 {
448 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
449 reg = <0x020a8000 0x4000>;
450 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
451 <0 73 IRQ_TYPE_LEVEL_HIGH>;
454 interrupt-controller;
455 #interrupt-cells = <2>;
458 gpio5: gpio@020ac000 {
459 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
460 reg = <0x020ac000 0x4000>;
461 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
462 <0 75 IRQ_TYPE_LEVEL_HIGH>;
465 interrupt-controller;
466 #interrupt-cells = <2>;
469 gpio6: gpio@020b0000 {
470 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
471 reg = <0x020b0000 0x4000>;
472 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
473 <0 77 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
480 gpio7: gpio@020b4000 {
481 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
482 reg = <0x020b4000 0x4000>;
483 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
484 <0 79 IRQ_TYPE_LEVEL_HIGH>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
492 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
493 reg = <0x020b8000 0x4000>;
494 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&clks IMX6QDL_CLK_IPG>;
499 wdog1: wdog@020bc000 {
500 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
501 reg = <0x020bc000 0x4000>;
502 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clks IMX6QDL_CLK_DUMMY>;
506 wdog2: wdog@020c0000 {
507 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
508 reg = <0x020c0000 0x4000>;
509 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&clks IMX6QDL_CLK_DUMMY>;
515 compatible = "fsl,imx6q-ccm";
516 reg = <0x020c4000 0x4000>;
517 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
518 <0 88 IRQ_TYPE_LEVEL_HIGH>;
522 anatop: anatop@020c8000 {
523 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
524 reg = <0x020c8000 0x1000>;
525 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
526 <0 54 IRQ_TYPE_LEVEL_HIGH>,
527 <0 127 IRQ_TYPE_LEVEL_HIGH>;
530 compatible = "fsl,anatop-regulator";
531 regulator-name = "vdd1p1";
532 regulator-min-microvolt = <800000>;
533 regulator-max-microvolt = <1375000>;
535 anatop-reg-offset = <0x110>;
536 anatop-vol-bit-shift = <8>;
537 anatop-vol-bit-width = <5>;
538 anatop-min-bit-val = <4>;
539 anatop-min-voltage = <800000>;
540 anatop-max-voltage = <1375000>;
544 compatible = "fsl,anatop-regulator";
545 regulator-name = "vdd3p0";
546 regulator-min-microvolt = <2800000>;
547 regulator-max-microvolt = <3150000>;
549 anatop-reg-offset = <0x120>;
550 anatop-vol-bit-shift = <8>;
551 anatop-vol-bit-width = <5>;
552 anatop-min-bit-val = <0>;
553 anatop-min-voltage = <2625000>;
554 anatop-max-voltage = <3400000>;
558 compatible = "fsl,anatop-regulator";
559 regulator-name = "vdd2p5";
560 regulator-min-microvolt = <2000000>;
561 regulator-max-microvolt = <2750000>;
563 anatop-reg-offset = <0x130>;
564 anatop-vol-bit-shift = <8>;
565 anatop-vol-bit-width = <5>;
566 anatop-min-bit-val = <0>;
567 anatop-min-voltage = <2000000>;
568 anatop-max-voltage = <2750000>;
571 reg_arm: regulator-vddcore@140 {
572 compatible = "fsl,anatop-regulator";
573 regulator-name = "vddarm";
574 regulator-min-microvolt = <725000>;
575 regulator-max-microvolt = <1450000>;
577 anatop-reg-offset = <0x140>;
578 anatop-vol-bit-shift = <0>;
579 anatop-vol-bit-width = <5>;
580 anatop-delay-reg-offset = <0x170>;
581 anatop-delay-bit-shift = <24>;
582 anatop-delay-bit-width = <2>;
583 anatop-min-bit-val = <1>;
584 anatop-min-voltage = <725000>;
585 anatop-max-voltage = <1450000>;
588 reg_pu: regulator-vddpu@140 {
589 compatible = "fsl,anatop-regulator";
590 regulator-name = "vddpu";
591 regulator-min-microvolt = <725000>;
592 regulator-max-microvolt = <1450000>;
594 anatop-reg-offset = <0x140>;
595 anatop-vol-bit-shift = <9>;
596 anatop-vol-bit-width = <5>;
597 anatop-delay-reg-offset = <0x170>;
598 anatop-delay-bit-shift = <26>;
599 anatop-delay-bit-width = <2>;
600 anatop-min-bit-val = <1>;
601 anatop-min-voltage = <725000>;
602 anatop-max-voltage = <1450000>;
605 reg_soc: regulator-vddsoc@140 {
606 compatible = "fsl,anatop-regulator";
607 regulator-name = "vddsoc";
608 regulator-min-microvolt = <725000>;
609 regulator-max-microvolt = <1450000>;
611 anatop-reg-offset = <0x140>;
612 anatop-vol-bit-shift = <18>;
613 anatop-vol-bit-width = <5>;
614 anatop-delay-reg-offset = <0x170>;
615 anatop-delay-bit-shift = <28>;
616 anatop-delay-bit-width = <2>;
617 anatop-min-bit-val = <1>;
618 anatop-min-voltage = <725000>;
619 anatop-max-voltage = <1450000>;
624 compatible = "fsl,imx6q-tempmon";
625 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
626 fsl,tempmon = <&anatop>;
627 fsl,tempmon-data = <&ocotp>;
628 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
631 usbphy1: usbphy@020c9000 {
632 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
633 reg = <0x020c9000 0x1000>;
634 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
636 fsl,anatop = <&anatop>;
639 usbphy2: usbphy@020ca000 {
640 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
641 reg = <0x020ca000 0x1000>;
642 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
644 fsl,anatop = <&anatop>;
648 compatible = "fsl,sec-v4.0-mon", "simple-bus";
649 #address-cells = <1>;
651 ranges = <0 0x020cc000 0x4000>;
654 compatible = "fsl,sec-v4.0-mon-rtc-lp";
656 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
657 <0 20 IRQ_TYPE_LEVEL_HIGH>;
661 epit1: epit@020d0000 { /* EPIT1 */
662 reg = <0x020d0000 0x4000>;
663 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
666 epit2: epit@020d4000 { /* EPIT2 */
667 reg = <0x020d4000 0x4000>;
668 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
672 compatible = "fsl,imx6q-src", "fsl,imx51-src";
673 reg = <0x020d8000 0x4000>;
674 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
675 <0 96 IRQ_TYPE_LEVEL_HIGH>;
680 compatible = "fsl,imx6q-gpc";
681 reg = <0x020dc000 0x4000>;
682 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
683 <0 90 IRQ_TYPE_LEVEL_HIGH>;
686 gpr: iomuxc-gpr@020e0000 {
687 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
688 reg = <0x020e0000 0x38>;
691 iomuxc: iomuxc@020e0000 {
692 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
693 reg = <0x020e0000 0x4000>;
697 #address-cells = <1>;
699 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
704 #address-cells = <1>;
712 lvds0_mux_0: endpoint {
713 remote-endpoint = <&ipu1_di0_lvds0>;
720 lvds0_mux_1: endpoint {
721 remote-endpoint = <&ipu1_di1_lvds0>;
727 #address-cells = <1>;
735 lvds1_mux_0: endpoint {
736 remote-endpoint = <&ipu1_di0_lvds1>;
743 lvds1_mux_1: endpoint {
744 remote-endpoint = <&ipu1_di1_lvds1>;
751 #address-cells = <1>;
753 reg = <0x00120000 0x9000>;
754 interrupts = <0 115 0x04>;
756 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
757 <&clks IMX6QDL_CLK_HDMI_ISFR>;
758 clock-names = "iahb", "isfr";
764 hdmi_mux_0: endpoint {
765 remote-endpoint = <&ipu1_di0_hdmi>;
772 hdmi_mux_1: endpoint {
773 remote-endpoint = <&ipu1_di1_hdmi>;
778 dcic1: dcic@020e4000 {
779 reg = <0x020e4000 0x4000>;
780 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
783 dcic2: dcic@020e8000 {
784 reg = <0x020e8000 0x4000>;
785 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
788 sdma: sdma@020ec000 {
789 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
790 reg = <0x020ec000 0x4000>;
791 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&clks IMX6QDL_CLK_SDMA>,
793 <&clks IMX6QDL_CLK_SDMA>;
794 clock-names = "ipg", "ahb";
796 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
800 aips-bus@02100000 { /* AIPS2 */
801 compatible = "fsl,aips-bus", "simple-bus";
802 #address-cells = <1>;
804 reg = <0x02100000 0x100000>;
808 reg = <0x02100000 0x40000>;
809 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
810 <0 106 IRQ_TYPE_LEVEL_HIGH>;
813 aipstz@0217c000 { /* AIPSTZ2 */
814 reg = <0x0217c000 0x4000>;
817 usbotg: usb@02184000 {
818 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
819 reg = <0x02184000 0x200>;
820 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&clks IMX6QDL_CLK_USBOH3>;
822 fsl,usbphy = <&usbphy1>;
823 fsl,usbmisc = <&usbmisc 0>;
827 usbh1: usb@02184200 {
828 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
829 reg = <0x02184200 0x200>;
830 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&clks IMX6QDL_CLK_USBOH3>;
832 fsl,usbphy = <&usbphy2>;
833 fsl,usbmisc = <&usbmisc 1>;
837 usbh2: usb@02184400 {
838 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
839 reg = <0x02184400 0x200>;
840 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&clks IMX6QDL_CLK_USBOH3>;
842 fsl,usbmisc = <&usbmisc 2>;
846 usbh3: usb@02184600 {
847 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
848 reg = <0x02184600 0x200>;
849 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&clks IMX6QDL_CLK_USBOH3>;
851 fsl,usbmisc = <&usbmisc 3>;
855 usbmisc: usbmisc@02184800 {
857 compatible = "fsl,imx6q-usbmisc";
858 reg = <0x02184800 0x200>;
859 clocks = <&clks IMX6QDL_CLK_USBOH3>;
862 fec: ethernet@02188000 {
863 compatible = "fsl,imx6q-fec";
864 reg = <0x02188000 0x4000>;
865 interrupts-extended =
866 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
867 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&clks IMX6QDL_CLK_ENET>,
869 <&clks IMX6QDL_CLK_ENET>,
870 <&clks IMX6QDL_CLK_ENET_REF>;
871 clock-names = "ipg", "ahb", "ptp";
876 reg = <0x0218c000 0x4000>;
877 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
878 <0 117 IRQ_TYPE_LEVEL_HIGH>,
879 <0 126 IRQ_TYPE_LEVEL_HIGH>;
882 usdhc1: usdhc@02190000 {
883 compatible = "fsl,imx6q-usdhc";
884 reg = <0x02190000 0x4000>;
885 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&clks IMX6QDL_CLK_USDHC1>,
887 <&clks IMX6QDL_CLK_USDHC1>,
888 <&clks IMX6QDL_CLK_USDHC1>;
889 clock-names = "ipg", "ahb", "per";
894 usdhc2: usdhc@02194000 {
895 compatible = "fsl,imx6q-usdhc";
896 reg = <0x02194000 0x4000>;
897 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&clks IMX6QDL_CLK_USDHC2>,
899 <&clks IMX6QDL_CLK_USDHC2>,
900 <&clks IMX6QDL_CLK_USDHC2>;
901 clock-names = "ipg", "ahb", "per";
906 usdhc3: usdhc@02198000 {
907 compatible = "fsl,imx6q-usdhc";
908 reg = <0x02198000 0x4000>;
909 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
910 clocks = <&clks IMX6QDL_CLK_USDHC3>,
911 <&clks IMX6QDL_CLK_USDHC3>,
912 <&clks IMX6QDL_CLK_USDHC3>;
913 clock-names = "ipg", "ahb", "per";
918 usdhc4: usdhc@0219c000 {
919 compatible = "fsl,imx6q-usdhc";
920 reg = <0x0219c000 0x4000>;
921 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
922 clocks = <&clks IMX6QDL_CLK_USDHC4>,
923 <&clks IMX6QDL_CLK_USDHC4>,
924 <&clks IMX6QDL_CLK_USDHC4>;
925 clock-names = "ipg", "ahb", "per";
931 #address-cells = <1>;
933 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
934 reg = <0x021a0000 0x4000>;
935 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clks IMX6QDL_CLK_I2C1>;
941 #address-cells = <1>;
943 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
944 reg = <0x021a4000 0x4000>;
945 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&clks IMX6QDL_CLK_I2C2>;
951 #address-cells = <1>;
953 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
954 reg = <0x021a8000 0x4000>;
955 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&clks IMX6QDL_CLK_I2C3>;
961 reg = <0x021ac000 0x4000>;
964 mmdc0: mmdc@021b0000 { /* MMDC0 */
965 compatible = "fsl,imx6q-mmdc";
966 reg = <0x021b0000 0x4000>;
969 mmdc1: mmdc@021b4000 { /* MMDC1 */
970 reg = <0x021b4000 0x4000>;
973 weim: weim@021b8000 {
974 compatible = "fsl,imx6q-weim";
975 reg = <0x021b8000 0x4000>;
976 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
977 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
980 ocotp: ocotp@021bc000 {
981 compatible = "fsl,imx6q-ocotp", "syscon";
982 reg = <0x021bc000 0x4000>;
985 tzasc@021d0000 { /* TZASC1 */
986 reg = <0x021d0000 0x4000>;
987 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
990 tzasc@021d4000 { /* TZASC2 */
991 reg = <0x021d4000 0x4000>;
992 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
995 audmux: audmux@021d8000 {
996 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
997 reg = <0x021d8000 0x4000>;
1001 mipi_csi: mipi@021dc000 {
1002 reg = <0x021dc000 0x4000>;
1005 mipi_dsi: mipi@021e0000 {
1006 #address-cells = <1>;
1008 reg = <0x021e0000 0x4000>;
1009 status = "disabled";
1014 mipi_mux_0: endpoint {
1015 remote-endpoint = <&ipu1_di0_mipi>;
1022 mipi_mux_1: endpoint {
1023 remote-endpoint = <&ipu1_di1_mipi>;
1029 reg = <0x021e4000 0x4000>;
1030 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1033 uart2: serial@021e8000 {
1034 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1035 reg = <0x021e8000 0x4000>;
1036 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1038 <&clks IMX6QDL_CLK_UART_SERIAL>;
1039 clock-names = "ipg", "per";
1040 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1041 dma-names = "rx", "tx";
1042 status = "disabled";
1045 uart3: serial@021ec000 {
1046 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1047 reg = <0x021ec000 0x4000>;
1048 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1050 <&clks IMX6QDL_CLK_UART_SERIAL>;
1051 clock-names = "ipg", "per";
1052 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1053 dma-names = "rx", "tx";
1054 status = "disabled";
1057 uart4: serial@021f0000 {
1058 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1059 reg = <0x021f0000 0x4000>;
1060 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1062 <&clks IMX6QDL_CLK_UART_SERIAL>;
1063 clock-names = "ipg", "per";
1064 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1065 dma-names = "rx", "tx";
1066 status = "disabled";
1069 uart5: serial@021f4000 {
1070 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1071 reg = <0x021f4000 0x4000>;
1072 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1074 <&clks IMX6QDL_CLK_UART_SERIAL>;
1075 clock-names = "ipg", "per";
1076 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1077 dma-names = "rx", "tx";
1078 status = "disabled";
1082 ipu1: ipu@02400000 {
1083 #address-cells = <1>;
1085 compatible = "fsl,imx6q-ipu";
1086 reg = <0x02400000 0x400000>;
1087 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1088 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1089 clocks = <&clks IMX6QDL_CLK_IPU1>,
1090 <&clks IMX6QDL_CLK_IPU1_DI0>,
1091 <&clks IMX6QDL_CLK_IPU1_DI1>;
1092 clock-names = "bus", "di0", "di1";
1104 #address-cells = <1>;
1108 ipu1_di0_disp0: endpoint@0 {
1111 ipu1_di0_hdmi: endpoint@1 {
1112 remote-endpoint = <&hdmi_mux_0>;
1115 ipu1_di0_mipi: endpoint@2 {
1116 remote-endpoint = <&mipi_mux_0>;
1119 ipu1_di0_lvds0: endpoint@3 {
1120 remote-endpoint = <&lvds0_mux_0>;
1123 ipu1_di0_lvds1: endpoint@4 {
1124 remote-endpoint = <&lvds1_mux_0>;
1129 #address-cells = <1>;
1133 ipu1_di0_disp1: endpoint@0 {
1136 ipu1_di1_hdmi: endpoint@1 {
1137 remote-endpoint = <&hdmi_mux_1>;
1140 ipu1_di1_mipi: endpoint@2 {
1141 remote-endpoint = <&mipi_mux_1>;
1144 ipu1_di1_lvds0: endpoint@3 {
1145 remote-endpoint = <&lvds0_mux_1>;
1148 ipu1_di1_lvds1: endpoint@4 {
1149 remote-endpoint = <&lvds1_mux_1>;