2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
38 intc: interrupt-controller@00a01000 {
39 compatible = "arm,cortex-a9-gic";
40 #interrupt-cells = <3>;
44 reg = <0x00a01000 0x1000>,
53 compatible = "fsl,imx-ckil", "fixed-clock";
54 clock-frequency = <32768>;
58 compatible = "fsl,imx-ckih1", "fixed-clock";
59 clock-frequency = <0>;
63 compatible = "fsl,imx-osc", "fixed-clock";
64 clock-frequency = <24000000>;
71 compatible = "simple-bus";
72 interrupt-parent = <&intc>;
75 dma_apbh: dma-apbh@00110000 {
76 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
77 reg = <0x00110000 0x2000>;
78 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
79 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
85 gpmi: gpmi-nand@00112000 {
86 compatible = "fsl,imx6q-gpmi-nand";
89 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
90 reg-names = "gpmi-nand", "bch";
91 interrupts = <0 15 0x04>;
92 interrupt-names = "bch";
93 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
94 <&clks 150>, <&clks 149>;
95 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
96 "gpmi_bch_apb", "per1_bch";
103 compatible = "arm,cortex-a9-twd-timer";
104 reg = <0x00a00600 0x20>;
105 interrupts = <1 13 0xf01>;
109 L2: l2-cache@00a02000 {
110 compatible = "arm,pl310-cache";
111 reg = <0x00a02000 0x1000>;
112 interrupts = <0 92 0x04>;
115 arm,tag-latency = <4 2 3>;
116 arm,data-latency = <4 2 3>;
120 compatible = "arm,cortex-a9-pmu";
121 interrupts = <0 94 0x04>;
124 aips-bus@02000000 { /* AIPS1 */
125 compatible = "fsl,aips-bus", "simple-bus";
126 #address-cells = <1>;
128 reg = <0x02000000 0x100000>;
132 compatible = "fsl,spba-bus", "simple-bus";
133 #address-cells = <1>;
135 reg = <0x02000000 0x40000>;
138 spdif: spdif@02004000 {
139 compatible = "fsl,imx35-spdif";
140 reg = <0x02004000 0x4000>;
141 interrupts = <0 52 0x04>;
142 dmas = <&sdma 14 18 0>,
144 dma-names = "rx", "tx";
145 clocks = <&clks 197>, <&clks 3>,
146 <&clks 197>, <&clks 107>,
147 <&clks 0>, <&clks 118>,
148 <&clks 62>, <&clks 139>,
150 clock-names = "core", "rxtx0",
158 ecspi1: ecspi@02008000 {
159 #address-cells = <1>;
161 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
162 reg = <0x02008000 0x4000>;
163 interrupts = <0 31 0x04>;
164 clocks = <&clks 112>, <&clks 112>;
165 clock-names = "ipg", "per";
169 ecspi2: ecspi@0200c000 {
170 #address-cells = <1>;
172 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
173 reg = <0x0200c000 0x4000>;
174 interrupts = <0 32 0x04>;
175 clocks = <&clks 113>, <&clks 113>;
176 clock-names = "ipg", "per";
180 ecspi3: ecspi@02010000 {
181 #address-cells = <1>;
183 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
184 reg = <0x02010000 0x4000>;
185 interrupts = <0 33 0x04>;
186 clocks = <&clks 114>, <&clks 114>;
187 clock-names = "ipg", "per";
191 ecspi4: ecspi@02014000 {
192 #address-cells = <1>;
194 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
195 reg = <0x02014000 0x4000>;
196 interrupts = <0 34 0x04>;
197 clocks = <&clks 115>, <&clks 115>;
198 clock-names = "ipg", "per";
202 uart1: serial@02020000 {
203 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
204 reg = <0x02020000 0x4000>;
205 interrupts = <0 26 0x04>;
206 clocks = <&clks 160>, <&clks 161>;
207 clock-names = "ipg", "per";
208 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
209 dma-names = "rx", "tx";
213 esai: esai@02024000 {
214 reg = <0x02024000 0x4000>;
215 interrupts = <0 51 0x04>;
219 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
220 reg = <0x02028000 0x4000>;
221 interrupts = <0 46 0x04>;
222 clocks = <&clks 178>;
223 dmas = <&sdma 37 1 0>,
225 dma-names = "rx", "tx";
226 fsl,fifo-depth = <15>;
227 fsl,ssi-dma-events = <38 37>;
232 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
233 reg = <0x0202c000 0x4000>;
234 interrupts = <0 47 0x04>;
235 clocks = <&clks 179>;
236 dmas = <&sdma 41 1 0>,
238 dma-names = "rx", "tx";
239 fsl,fifo-depth = <15>;
240 fsl,ssi-dma-events = <42 41>;
245 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
246 reg = <0x02030000 0x4000>;
247 interrupts = <0 48 0x04>;
248 clocks = <&clks 180>;
249 dmas = <&sdma 45 1 0>,
251 dma-names = "rx", "tx";
252 fsl,fifo-depth = <15>;
253 fsl,ssi-dma-events = <46 45>;
257 asrc: asrc@02034000 {
258 reg = <0x02034000 0x4000>;
259 interrupts = <0 50 0x04>;
263 reg = <0x0203c000 0x4000>;
268 reg = <0x02040000 0x3c000>;
269 interrupts = <0 3 0x04 0 12 0x04>;
272 aipstz@0207c000 { /* AIPSTZ1 */
273 reg = <0x0207c000 0x4000>;
278 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
279 reg = <0x02080000 0x4000>;
280 interrupts = <0 83 0x04>;
281 clocks = <&clks 62>, <&clks 145>;
282 clock-names = "ipg", "per";
287 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
288 reg = <0x02084000 0x4000>;
289 interrupts = <0 84 0x04>;
290 clocks = <&clks 62>, <&clks 146>;
291 clock-names = "ipg", "per";
296 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
297 reg = <0x02088000 0x4000>;
298 interrupts = <0 85 0x04>;
299 clocks = <&clks 62>, <&clks 147>;
300 clock-names = "ipg", "per";
305 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
306 reg = <0x0208c000 0x4000>;
307 interrupts = <0 86 0x04>;
308 clocks = <&clks 62>, <&clks 148>;
309 clock-names = "ipg", "per";
312 can1: flexcan@02090000 {
313 compatible = "fsl,imx6q-flexcan";
314 reg = <0x02090000 0x4000>;
315 interrupts = <0 110 0x04>;
316 clocks = <&clks 108>, <&clks 109>;
317 clock-names = "ipg", "per";
320 can2: flexcan@02094000 {
321 compatible = "fsl,imx6q-flexcan";
322 reg = <0x02094000 0x4000>;
323 interrupts = <0 111 0x04>;
324 clocks = <&clks 110>, <&clks 111>;
325 clock-names = "ipg", "per";
329 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
330 reg = <0x02098000 0x4000>;
331 interrupts = <0 55 0x04>;
332 clocks = <&clks 119>, <&clks 120>;
333 clock-names = "ipg", "per";
336 gpio1: gpio@0209c000 {
337 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
338 reg = <0x0209c000 0x4000>;
339 interrupts = <0 66 0x04 0 67 0x04>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
346 gpio2: gpio@020a0000 {
347 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
348 reg = <0x020a0000 0x4000>;
349 interrupts = <0 68 0x04 0 69 0x04>;
352 interrupt-controller;
353 #interrupt-cells = <2>;
356 gpio3: gpio@020a4000 {
357 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
358 reg = <0x020a4000 0x4000>;
359 interrupts = <0 70 0x04 0 71 0x04>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
366 gpio4: gpio@020a8000 {
367 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
368 reg = <0x020a8000 0x4000>;
369 interrupts = <0 72 0x04 0 73 0x04>;
372 interrupt-controller;
373 #interrupt-cells = <2>;
376 gpio5: gpio@020ac000 {
377 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
378 reg = <0x020ac000 0x4000>;
379 interrupts = <0 74 0x04 0 75 0x04>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
386 gpio6: gpio@020b0000 {
387 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
388 reg = <0x020b0000 0x4000>;
389 interrupts = <0 76 0x04 0 77 0x04>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
396 gpio7: gpio@020b4000 {
397 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
398 reg = <0x020b4000 0x4000>;
399 interrupts = <0 78 0x04 0 79 0x04>;
402 interrupt-controller;
403 #interrupt-cells = <2>;
407 reg = <0x020b8000 0x4000>;
408 interrupts = <0 82 0x04>;
411 wdog1: wdog@020bc000 {
412 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
413 reg = <0x020bc000 0x4000>;
414 interrupts = <0 80 0x04>;
418 wdog2: wdog@020c0000 {
419 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
420 reg = <0x020c0000 0x4000>;
421 interrupts = <0 81 0x04>;
427 compatible = "fsl,imx6q-ccm";
428 reg = <0x020c4000 0x4000>;
429 interrupts = <0 87 0x04 0 88 0x04>;
433 anatop: anatop@020c8000 {
434 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
435 reg = <0x020c8000 0x1000>;
436 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
439 compatible = "fsl,anatop-regulator";
440 regulator-name = "vdd1p1";
441 regulator-min-microvolt = <800000>;
442 regulator-max-microvolt = <1375000>;
444 anatop-reg-offset = <0x110>;
445 anatop-vol-bit-shift = <8>;
446 anatop-vol-bit-width = <5>;
447 anatop-min-bit-val = <4>;
448 anatop-min-voltage = <800000>;
449 anatop-max-voltage = <1375000>;
453 compatible = "fsl,anatop-regulator";
454 regulator-name = "vdd3p0";
455 regulator-min-microvolt = <2800000>;
456 regulator-max-microvolt = <3150000>;
458 anatop-reg-offset = <0x120>;
459 anatop-vol-bit-shift = <8>;
460 anatop-vol-bit-width = <5>;
461 anatop-min-bit-val = <0>;
462 anatop-min-voltage = <2625000>;
463 anatop-max-voltage = <3400000>;
467 compatible = "fsl,anatop-regulator";
468 regulator-name = "vdd2p5";
469 regulator-min-microvolt = <2000000>;
470 regulator-max-microvolt = <2750000>;
472 anatop-reg-offset = <0x130>;
473 anatop-vol-bit-shift = <8>;
474 anatop-vol-bit-width = <5>;
475 anatop-min-bit-val = <0>;
476 anatop-min-voltage = <2000000>;
477 anatop-max-voltage = <2750000>;
480 reg_arm: regulator-vddcore@140 {
481 compatible = "fsl,anatop-regulator";
482 regulator-name = "cpu";
483 regulator-min-microvolt = <725000>;
484 regulator-max-microvolt = <1450000>;
486 anatop-reg-offset = <0x140>;
487 anatop-vol-bit-shift = <0>;
488 anatop-vol-bit-width = <5>;
489 anatop-delay-reg-offset = <0x170>;
490 anatop-delay-bit-shift = <24>;
491 anatop-delay-bit-width = <2>;
492 anatop-min-bit-val = <1>;
493 anatop-min-voltage = <725000>;
494 anatop-max-voltage = <1450000>;
497 reg_pu: regulator-vddpu@140 {
498 compatible = "fsl,anatop-regulator";
499 regulator-name = "vddpu";
500 regulator-min-microvolt = <725000>;
501 regulator-max-microvolt = <1450000>;
503 anatop-reg-offset = <0x140>;
504 anatop-vol-bit-shift = <9>;
505 anatop-vol-bit-width = <5>;
506 anatop-delay-reg-offset = <0x170>;
507 anatop-delay-bit-shift = <26>;
508 anatop-delay-bit-width = <2>;
509 anatop-min-bit-val = <1>;
510 anatop-min-voltage = <725000>;
511 anatop-max-voltage = <1450000>;
514 reg_soc: regulator-vddsoc@140 {
515 compatible = "fsl,anatop-regulator";
516 regulator-name = "vddsoc";
517 regulator-min-microvolt = <725000>;
518 regulator-max-microvolt = <1450000>;
520 anatop-reg-offset = <0x140>;
521 anatop-vol-bit-shift = <18>;
522 anatop-vol-bit-width = <5>;
523 anatop-delay-reg-offset = <0x170>;
524 anatop-delay-bit-shift = <28>;
525 anatop-delay-bit-width = <2>;
526 anatop-min-bit-val = <1>;
527 anatop-min-voltage = <725000>;
528 anatop-max-voltage = <1450000>;
533 compatible = "fsl,imx6q-tempmon";
534 interrupts = <0 49 0x04>;
535 fsl,tempmon = <&anatop>;
536 fsl,tempmon-data = <&ocotp>;
539 usbphy1: usbphy@020c9000 {
540 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
541 reg = <0x020c9000 0x1000>;
542 interrupts = <0 44 0x04>;
543 clocks = <&clks 182>;
546 usbphy2: usbphy@020ca000 {
547 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
548 reg = <0x020ca000 0x1000>;
549 interrupts = <0 45 0x04>;
550 clocks = <&clks 183>;
554 compatible = "fsl,sec-v4.0-mon", "simple-bus";
555 #address-cells = <1>;
557 ranges = <0 0x020cc000 0x4000>;
560 compatible = "fsl,sec-v4.0-mon-rtc-lp";
562 interrupts = <0 19 0x04 0 20 0x04>;
566 epit1: epit@020d0000 { /* EPIT1 */
567 reg = <0x020d0000 0x4000>;
568 interrupts = <0 56 0x04>;
571 epit2: epit@020d4000 { /* EPIT2 */
572 reg = <0x020d4000 0x4000>;
573 interrupts = <0 57 0x04>;
577 compatible = "fsl,imx6q-src", "fsl,imx51-src";
578 reg = <0x020d8000 0x4000>;
579 interrupts = <0 91 0x04 0 96 0x04>;
584 compatible = "fsl,imx6q-gpc";
585 reg = <0x020dc000 0x4000>;
586 interrupts = <0 89 0x04 0 90 0x04>;
589 gpr: iomuxc-gpr@020e0000 {
590 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
591 reg = <0x020e0000 0x38>;
594 iomuxc: iomuxc@020e0000 {
595 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
596 reg = <0x020e0000 0x4000>;
599 pinctrl_audmux_1: audmux-1 {
601 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
602 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
603 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
604 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
608 pinctrl_audmux_2: audmux-2 {
610 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
611 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
612 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
613 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
617 pinctrl_audmux_3: audmux-3 {
619 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000
620 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
621 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
627 pinctrl_ecspi1_1: ecspi1grp-1 {
629 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
630 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
631 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
635 pinctrl_ecspi1_2: ecspi1grp-2 {
637 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
638 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
639 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
645 pinctrl_ecspi3_1: ecspi3grp-1 {
647 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
648 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
649 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
655 pinctrl_enet_1: enetgrp-1 {
657 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
658 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
659 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
660 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
661 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
662 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
663 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
664 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
665 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
666 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
667 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
668 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
669 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
670 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
671 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
672 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
676 pinctrl_enet_2: enetgrp-2 {
678 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
679 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
680 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
681 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
682 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
683 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
684 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
685 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
686 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
687 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
688 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
689 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
690 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
691 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
692 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
696 pinctrl_enet_3: enetgrp-3 {
698 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
699 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
700 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
701 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
702 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
703 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
704 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
705 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
706 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
707 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
708 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
709 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
710 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
711 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
712 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
713 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
719 pinctrl_esai_1: esaigrp-1 {
721 MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
722 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
723 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
724 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
725 MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
726 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
727 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
728 MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
729 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
733 pinctrl_esai_2: esaigrp-2 {
735 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
736 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
737 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
738 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
739 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
740 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
741 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
742 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
743 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
744 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
750 pinctrl_flexcan1_1: flexcan1grp-1 {
752 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
753 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
757 pinctrl_flexcan1_2: flexcan1grp-2 {
759 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
760 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
766 pinctrl_flexcan2_1: flexcan2grp-1 {
768 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
769 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
775 pinctrl_gpmi_nand_1: gpmi-nand-1 {
777 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
778 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
779 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
780 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
781 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
782 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
783 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
784 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
785 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
786 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
787 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
788 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
789 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
790 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
791 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
792 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
793 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
799 pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
801 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
802 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
806 pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
808 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
809 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
813 pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
815 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
816 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
822 pinctrl_hdmi_cec_1: hdmicecgrp-1 {
824 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
828 pinctrl_hdmi_cec_2: hdmicecgrp-2 {
830 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
836 pinctrl_i2c1_1: i2c1grp-1 {
838 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
839 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
843 pinctrl_i2c1_2: i2c1grp-2 {
845 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
846 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
852 pinctrl_i2c2_1: i2c2grp-1 {
854 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
855 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
859 pinctrl_i2c2_2: i2c2grp-2 {
861 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
862 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
866 pinctrl_i2c2_3: i2c2grp-3 {
868 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
869 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
875 pinctrl_i2c3_1: i2c3grp-1 {
877 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
878 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
882 pinctrl_i2c3_2: i2c3grp-2 {
884 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
885 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
889 pinctrl_i2c3_3: i2c3grp-3 {
891 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
892 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
896 pinctrl_i2c3_4: i2c3grp-4 {
898 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
899 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
905 pinctrl_ipu1_1: ipu1grp-1 {
907 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
908 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
909 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
910 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
911 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
912 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
913 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
914 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
915 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
916 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
917 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
918 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
919 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
920 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
921 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
922 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
923 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
924 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
925 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
926 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
927 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
928 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
929 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
930 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
931 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
932 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
933 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
934 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
935 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
939 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
941 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
942 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
943 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
944 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
945 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
946 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
947 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
948 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
949 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
950 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
951 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
952 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
956 pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
958 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
959 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
960 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
961 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
962 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
963 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
964 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
965 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
966 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
967 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
968 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
969 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
970 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
971 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
972 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
973 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
974 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
975 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
976 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
982 pinctrl_mlb_1: mlbgrp-1 {
984 MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
985 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
986 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
990 pinctrl_mlb_2: mlbgrp-2 {
992 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
993 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
994 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
1000 pinctrl_pwm0_1: pwm0grp-1 {
1002 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
1008 pinctrl_pwm3_1: pwm3grp-1 {
1010 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
1016 pinctrl_spdif_1: spdifgrp-1 {
1018 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
1022 pinctrl_spdif_2: spdifgrp-2 {
1024 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
1025 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1029 pinctrl_spdif_3: spdifgrp-3 {
1031 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
1037 pinctrl_uart1_1: uart1grp-1 {
1039 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1040 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1046 pinctrl_uart2_1: uart2grp-1 {
1048 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
1049 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
1053 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
1055 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
1056 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
1057 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
1058 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
1064 pinctrl_uart3_1: uart3grp-1 {
1066 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
1067 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
1068 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
1069 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1073 pinctrl_uart3_2: uart3grp-2 {
1075 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1076 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1077 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
1078 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1084 pinctrl_uart4_1: uart4grp-1 {
1086 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1087 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1093 pinctrl_usbotg_1: usbotggrp-1 {
1095 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
1099 pinctrl_usbotg_2: usbotggrp-2 {
1101 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1107 pinctrl_usbh2_1: usbh2grp-1 {
1109 MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
1110 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
1114 pinctrl_usbh2_2: usbh2grp-2 {
1116 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
1122 pinctrl_usbh3_1: usbh3grp-1 {
1124 MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
1125 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
1129 pinctrl_usbh3_2: usbh3grp-2 {
1131 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
1137 pinctrl_usdhc1_1: usdhc1grp-1 {
1139 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1140 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1141 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1142 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1143 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1144 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1145 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
1146 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
1147 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
1148 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
1152 pinctrl_usdhc1_2: usdhc1grp-2 {
1154 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1155 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1156 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1157 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1158 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1159 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1165 pinctrl_usdhc2_1: usdhc2grp-1 {
1167 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1168 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1169 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1170 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1171 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1172 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1173 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
1174 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
1175 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
1176 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
1180 pinctrl_usdhc2_2: usdhc2grp-2 {
1182 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1183 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1184 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1185 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1186 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1187 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1193 pinctrl_usdhc3_1: usdhc3grp-1 {
1195 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1196 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1197 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1198 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1199 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1200 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1201 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1202 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1203 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1204 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1208 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */
1210 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
1211 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
1212 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
1213 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
1214 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
1215 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
1216 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
1217 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
1218 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
1219 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
1223 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */
1225 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
1226 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
1227 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
1228 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
1229 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
1230 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
1231 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
1232 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
1233 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
1234 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
1238 pinctrl_usdhc3_2: usdhc3grp-2 {
1240 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1241 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1242 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1243 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1244 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1245 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1251 pinctrl_usdhc4_1: usdhc4grp-1 {
1253 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1254 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1255 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1256 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1257 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1258 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1259 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1260 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1261 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1262 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1266 pinctrl_usdhc4_2: usdhc4grp-2 {
1268 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1269 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1270 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1271 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1272 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1273 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1279 pinctrl_weim_cs0_1: weim_cs0grp-1 {
1281 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
1285 pinctrl_weim_nor_1: weim_norgrp-1 {
1287 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
1288 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
1289 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1291 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1292 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1293 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1294 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1295 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1296 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1297 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1298 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1299 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1300 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1301 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1302 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1303 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1304 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1305 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1306 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1308 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1309 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1310 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1311 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1312 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1313 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1314 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1315 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1316 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
1317 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
1318 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
1319 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
1320 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
1321 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
1322 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
1323 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
1324 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
1325 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
1326 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
1327 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
1328 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
1329 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
1330 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
1331 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
1338 #address-cells = <1>;
1340 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
1342 status = "disabled";
1346 status = "disabled";
1351 status = "disabled";
1355 dcic1: dcic@020e4000 {
1356 reg = <0x020e4000 0x4000>;
1357 interrupts = <0 124 0x04>;
1360 dcic2: dcic@020e8000 {
1361 reg = <0x020e8000 0x4000>;
1362 interrupts = <0 125 0x04>;
1365 sdma: sdma@020ec000 {
1366 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
1367 reg = <0x020ec000 0x4000>;
1368 interrupts = <0 2 0x04>;
1369 clocks = <&clks 155>, <&clks 155>;
1370 clock-names = "ipg", "ahb";
1372 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
1376 aips-bus@02100000 { /* AIPS2 */
1377 compatible = "fsl,aips-bus", "simple-bus";
1378 #address-cells = <1>;
1380 reg = <0x02100000 0x100000>;
1384 reg = <0x02100000 0x40000>;
1385 interrupts = <0 105 0x04 0 106 0x04>;
1388 aipstz@0217c000 { /* AIPSTZ2 */
1389 reg = <0x0217c000 0x4000>;
1392 usbotg: usb@02184000 {
1393 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1394 reg = <0x02184000 0x200>;
1395 interrupts = <0 43 0x04>;
1396 clocks = <&clks 162>;
1397 fsl,usbphy = <&usbphy1>;
1398 fsl,usbmisc = <&usbmisc 0>;
1399 status = "disabled";
1402 usbh1: usb@02184200 {
1403 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1404 reg = <0x02184200 0x200>;
1405 interrupts = <0 40 0x04>;
1406 clocks = <&clks 162>;
1407 fsl,usbphy = <&usbphy2>;
1408 fsl,usbmisc = <&usbmisc 1>;
1409 status = "disabled";
1412 usbh2: usb@02184400 {
1413 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1414 reg = <0x02184400 0x200>;
1415 interrupts = <0 41 0x04>;
1416 clocks = <&clks 162>;
1417 fsl,usbmisc = <&usbmisc 2>;
1418 status = "disabled";
1421 usbh3: usb@02184600 {
1422 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1423 reg = <0x02184600 0x200>;
1424 interrupts = <0 42 0x04>;
1425 clocks = <&clks 162>;
1426 fsl,usbmisc = <&usbmisc 3>;
1427 status = "disabled";
1430 usbmisc: usbmisc@02184800 {
1432 compatible = "fsl,imx6q-usbmisc";
1433 reg = <0x02184800 0x200>;
1434 clocks = <&clks 162>;
1437 fec: ethernet@02188000 {
1438 compatible = "fsl,imx6q-fec";
1439 reg = <0x02188000 0x4000>;
1440 interrupts = <0 118 0x04 0 119 0x04>;
1441 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
1442 clock-names = "ipg", "ahb", "ptp";
1443 status = "disabled";
1447 reg = <0x0218c000 0x4000>;
1448 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
1451 usdhc1: usdhc@02190000 {
1452 compatible = "fsl,imx6q-usdhc";
1453 reg = <0x02190000 0x4000>;
1454 interrupts = <0 22 0x04>;
1455 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
1456 clock-names = "ipg", "ahb", "per";
1458 status = "disabled";
1461 usdhc2: usdhc@02194000 {
1462 compatible = "fsl,imx6q-usdhc";
1463 reg = <0x02194000 0x4000>;
1464 interrupts = <0 23 0x04>;
1465 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
1466 clock-names = "ipg", "ahb", "per";
1468 status = "disabled";
1471 usdhc3: usdhc@02198000 {
1472 compatible = "fsl,imx6q-usdhc";
1473 reg = <0x02198000 0x4000>;
1474 interrupts = <0 24 0x04>;
1475 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
1476 clock-names = "ipg", "ahb", "per";
1478 status = "disabled";
1481 usdhc4: usdhc@0219c000 {
1482 compatible = "fsl,imx6q-usdhc";
1483 reg = <0x0219c000 0x4000>;
1484 interrupts = <0 25 0x04>;
1485 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
1486 clock-names = "ipg", "ahb", "per";
1488 status = "disabled";
1491 i2c1: i2c@021a0000 {
1492 #address-cells = <1>;
1494 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1495 reg = <0x021a0000 0x4000>;
1496 interrupts = <0 36 0x04>;
1497 clocks = <&clks 125>;
1498 status = "disabled";
1501 i2c2: i2c@021a4000 {
1502 #address-cells = <1>;
1504 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1505 reg = <0x021a4000 0x4000>;
1506 interrupts = <0 37 0x04>;
1507 clocks = <&clks 126>;
1508 status = "disabled";
1511 i2c3: i2c@021a8000 {
1512 #address-cells = <1>;
1514 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1515 reg = <0x021a8000 0x4000>;
1516 interrupts = <0 38 0x04>;
1517 clocks = <&clks 127>;
1518 status = "disabled";
1522 reg = <0x021ac000 0x4000>;
1525 mmdc0: mmdc@021b0000 { /* MMDC0 */
1526 compatible = "fsl,imx6q-mmdc";
1527 reg = <0x021b0000 0x4000>;
1530 mmdc1: mmdc@021b4000 { /* MMDC1 */
1531 reg = <0x021b4000 0x4000>;
1534 weim: weim@021b8000 {
1535 compatible = "fsl,imx6q-weim";
1536 reg = <0x021b8000 0x4000>;
1537 interrupts = <0 14 0x04>;
1538 clocks = <&clks 196>;
1541 ocotp: ocotp@021bc000 {
1542 compatible = "fsl,imx6q-ocotp", "syscon";
1543 reg = <0x021bc000 0x4000>;
1546 tzasc@021d0000 { /* TZASC1 */
1547 reg = <0x021d0000 0x4000>;
1548 interrupts = <0 108 0x04>;
1551 tzasc@021d4000 { /* TZASC2 */
1552 reg = <0x021d4000 0x4000>;
1553 interrupts = <0 109 0x04>;
1556 audmux: audmux@021d8000 {
1557 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1558 reg = <0x021d8000 0x4000>;
1559 status = "disabled";
1562 mipi@021dc000 { /* MIPI-CSI */
1563 reg = <0x021dc000 0x4000>;
1566 mipi@021e0000 { /* MIPI-DSI */
1567 reg = <0x021e0000 0x4000>;
1571 reg = <0x021e4000 0x4000>;
1572 interrupts = <0 18 0x04>;
1575 uart2: serial@021e8000 {
1576 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1577 reg = <0x021e8000 0x4000>;
1578 interrupts = <0 27 0x04>;
1579 clocks = <&clks 160>, <&clks 161>;
1580 clock-names = "ipg", "per";
1581 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1582 dma-names = "rx", "tx";
1583 status = "disabled";
1586 uart3: serial@021ec000 {
1587 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1588 reg = <0x021ec000 0x4000>;
1589 interrupts = <0 28 0x04>;
1590 clocks = <&clks 160>, <&clks 161>;
1591 clock-names = "ipg", "per";
1592 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1593 dma-names = "rx", "tx";
1594 status = "disabled";
1597 uart4: serial@021f0000 {
1598 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1599 reg = <0x021f0000 0x4000>;
1600 interrupts = <0 29 0x04>;
1601 clocks = <&clks 160>, <&clks 161>;
1602 clock-names = "ipg", "per";
1603 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1604 dma-names = "rx", "tx";
1605 status = "disabled";
1608 uart5: serial@021f4000 {
1609 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1610 reg = <0x021f4000 0x4000>;
1611 interrupts = <0 30 0x04>;
1612 clocks = <&clks 160>, <&clks 161>;
1613 clock-names = "ipg", "per";
1614 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1615 dma-names = "rx", "tx";
1616 status = "disabled";
1620 ipu1: ipu@02400000 {
1622 compatible = "fsl,imx6q-ipu";
1623 reg = <0x02400000 0x400000>;
1624 interrupts = <0 6 0x4 0 5 0x4>;
1625 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1626 clock-names = "bus", "di0", "di1";